omap.c 37 KB

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  1. /*
  2. * linux/drivers/mmc/host/omap.c
  3. *
  4. * Copyright (C) 2004 Nokia Corporation
  5. * Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
  6. * Misc hacks here and there by Tony Lindgren <tony@atomide.com>
  7. * Other hacks (DMA, SD, etc) by David Brownell
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/moduleparam.h>
  15. #include <linux/init.h>
  16. #include <linux/ioport.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/dmaengine.h>
  20. #include <linux/dma-mapping.h>
  21. #include <linux/delay.h>
  22. #include <linux/spinlock.h>
  23. #include <linux/timer.h>
  24. #include <linux/of.h>
  25. #include <linux/mmc/host.h>
  26. #include <linux/mmc/card.h>
  27. #include <linux/mmc/mmc.h>
  28. #include <linux/clk.h>
  29. #include <linux/scatterlist.h>
  30. #include <linux/slab.h>
  31. #include <linux/platform_data/mmc-omap.h>
  32. #define OMAP_MMC_REG_CMD 0x00
  33. #define OMAP_MMC_REG_ARGL 0x01
  34. #define OMAP_MMC_REG_ARGH 0x02
  35. #define OMAP_MMC_REG_CON 0x03
  36. #define OMAP_MMC_REG_STAT 0x04
  37. #define OMAP_MMC_REG_IE 0x05
  38. #define OMAP_MMC_REG_CTO 0x06
  39. #define OMAP_MMC_REG_DTO 0x07
  40. #define OMAP_MMC_REG_DATA 0x08
  41. #define OMAP_MMC_REG_BLEN 0x09
  42. #define OMAP_MMC_REG_NBLK 0x0a
  43. #define OMAP_MMC_REG_BUF 0x0b
  44. #define OMAP_MMC_REG_SDIO 0x0d
  45. #define OMAP_MMC_REG_REV 0x0f
  46. #define OMAP_MMC_REG_RSP0 0x10
  47. #define OMAP_MMC_REG_RSP1 0x11
  48. #define OMAP_MMC_REG_RSP2 0x12
  49. #define OMAP_MMC_REG_RSP3 0x13
  50. #define OMAP_MMC_REG_RSP4 0x14
  51. #define OMAP_MMC_REG_RSP5 0x15
  52. #define OMAP_MMC_REG_RSP6 0x16
  53. #define OMAP_MMC_REG_RSP7 0x17
  54. #define OMAP_MMC_REG_IOSR 0x18
  55. #define OMAP_MMC_REG_SYSC 0x19
  56. #define OMAP_MMC_REG_SYSS 0x1a
  57. #define OMAP_MMC_STAT_CARD_ERR (1 << 14)
  58. #define OMAP_MMC_STAT_CARD_IRQ (1 << 13)
  59. #define OMAP_MMC_STAT_OCR_BUSY (1 << 12)
  60. #define OMAP_MMC_STAT_A_EMPTY (1 << 11)
  61. #define OMAP_MMC_STAT_A_FULL (1 << 10)
  62. #define OMAP_MMC_STAT_CMD_CRC (1 << 8)
  63. #define OMAP_MMC_STAT_CMD_TOUT (1 << 7)
  64. #define OMAP_MMC_STAT_DATA_CRC (1 << 6)
  65. #define OMAP_MMC_STAT_DATA_TOUT (1 << 5)
  66. #define OMAP_MMC_STAT_END_BUSY (1 << 4)
  67. #define OMAP_MMC_STAT_END_OF_DATA (1 << 3)
  68. #define OMAP_MMC_STAT_CARD_BUSY (1 << 2)
  69. #define OMAP_MMC_STAT_END_OF_CMD (1 << 0)
  70. #define mmc_omap7xx() (host->features & MMC_OMAP7XX)
  71. #define mmc_omap15xx() (host->features & MMC_OMAP15XX)
  72. #define mmc_omap16xx() (host->features & MMC_OMAP16XX)
  73. #define MMC_OMAP1_MASK (MMC_OMAP7XX | MMC_OMAP15XX | MMC_OMAP16XX)
  74. #define mmc_omap1() (host->features & MMC_OMAP1_MASK)
  75. #define mmc_omap2() (!mmc_omap1())
  76. #define OMAP_MMC_REG(host, reg) (OMAP_MMC_REG_##reg << (host)->reg_shift)
  77. #define OMAP_MMC_READ(host, reg) __raw_readw((host)->virt_base + OMAP_MMC_REG(host, reg))
  78. #define OMAP_MMC_WRITE(host, reg, val) __raw_writew((val), (host)->virt_base + OMAP_MMC_REG(host, reg))
  79. /*
  80. * Command types
  81. */
  82. #define OMAP_MMC_CMDTYPE_BC 0
  83. #define OMAP_MMC_CMDTYPE_BCR 1
  84. #define OMAP_MMC_CMDTYPE_AC 2
  85. #define OMAP_MMC_CMDTYPE_ADTC 3
  86. #define DRIVER_NAME "mmci-omap"
  87. /* Specifies how often in millisecs to poll for card status changes
  88. * when the cover switch is open */
  89. #define OMAP_MMC_COVER_POLL_DELAY 500
  90. struct mmc_omap_host;
  91. struct mmc_omap_slot {
  92. int id;
  93. unsigned int vdd;
  94. u16 saved_con;
  95. u16 bus_mode;
  96. u16 power_mode;
  97. unsigned int fclk_freq;
  98. struct tasklet_struct cover_tasklet;
  99. struct timer_list cover_timer;
  100. unsigned cover_open;
  101. struct mmc_request *mrq;
  102. struct mmc_omap_host *host;
  103. struct mmc_host *mmc;
  104. struct omap_mmc_slot_data *pdata;
  105. };
  106. struct mmc_omap_host {
  107. int initialized;
  108. struct mmc_request * mrq;
  109. struct mmc_command * cmd;
  110. struct mmc_data * data;
  111. struct mmc_host * mmc;
  112. struct device * dev;
  113. unsigned char id; /* 16xx chips have 2 MMC blocks */
  114. struct clk * iclk;
  115. struct clk * fclk;
  116. struct dma_chan *dma_rx;
  117. u32 dma_rx_burst;
  118. struct dma_chan *dma_tx;
  119. u32 dma_tx_burst;
  120. void __iomem *virt_base;
  121. unsigned int phys_base;
  122. int irq;
  123. unsigned char bus_mode;
  124. unsigned int reg_shift;
  125. struct work_struct cmd_abort_work;
  126. unsigned abort:1;
  127. struct timer_list cmd_abort_timer;
  128. struct work_struct slot_release_work;
  129. struct mmc_omap_slot *next_slot;
  130. struct work_struct send_stop_work;
  131. struct mmc_data *stop_data;
  132. unsigned int sg_len;
  133. int sg_idx;
  134. u16 * buffer;
  135. u32 buffer_bytes_left;
  136. u32 total_bytes_left;
  137. unsigned features;
  138. unsigned brs_received:1, dma_done:1;
  139. unsigned dma_in_use:1;
  140. spinlock_t dma_lock;
  141. struct mmc_omap_slot *slots[OMAP_MMC_MAX_SLOTS];
  142. struct mmc_omap_slot *current_slot;
  143. spinlock_t slot_lock;
  144. wait_queue_head_t slot_wq;
  145. int nr_slots;
  146. struct timer_list clk_timer;
  147. spinlock_t clk_lock; /* for changing enabled state */
  148. unsigned int fclk_enabled:1;
  149. struct workqueue_struct *mmc_omap_wq;
  150. struct omap_mmc_platform_data *pdata;
  151. };
  152. static void mmc_omap_fclk_offdelay(struct mmc_omap_slot *slot)
  153. {
  154. unsigned long tick_ns;
  155. if (slot != NULL && slot->host->fclk_enabled && slot->fclk_freq > 0) {
  156. tick_ns = DIV_ROUND_UP(NSEC_PER_SEC, slot->fclk_freq);
  157. ndelay(8 * tick_ns);
  158. }
  159. }
  160. static void mmc_omap_fclk_enable(struct mmc_omap_host *host, unsigned int enable)
  161. {
  162. unsigned long flags;
  163. spin_lock_irqsave(&host->clk_lock, flags);
  164. if (host->fclk_enabled != enable) {
  165. host->fclk_enabled = enable;
  166. if (enable)
  167. clk_enable(host->fclk);
  168. else
  169. clk_disable(host->fclk);
  170. }
  171. spin_unlock_irqrestore(&host->clk_lock, flags);
  172. }
  173. static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
  174. {
  175. struct mmc_omap_host *host = slot->host;
  176. unsigned long flags;
  177. if (claimed)
  178. goto no_claim;
  179. spin_lock_irqsave(&host->slot_lock, flags);
  180. while (host->mmc != NULL) {
  181. spin_unlock_irqrestore(&host->slot_lock, flags);
  182. wait_event(host->slot_wq, host->mmc == NULL);
  183. spin_lock_irqsave(&host->slot_lock, flags);
  184. }
  185. host->mmc = slot->mmc;
  186. spin_unlock_irqrestore(&host->slot_lock, flags);
  187. no_claim:
  188. del_timer(&host->clk_timer);
  189. if (host->current_slot != slot || !claimed)
  190. mmc_omap_fclk_offdelay(host->current_slot);
  191. if (host->current_slot != slot) {
  192. OMAP_MMC_WRITE(host, CON, slot->saved_con & 0xFC00);
  193. if (host->pdata->switch_slot != NULL)
  194. host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id);
  195. host->current_slot = slot;
  196. }
  197. if (claimed) {
  198. mmc_omap_fclk_enable(host, 1);
  199. /* Doing the dummy read here seems to work around some bug
  200. * at least in OMAP24xx silicon where the command would not
  201. * start after writing the CMD register. Sigh. */
  202. OMAP_MMC_READ(host, CON);
  203. OMAP_MMC_WRITE(host, CON, slot->saved_con);
  204. } else
  205. mmc_omap_fclk_enable(host, 0);
  206. }
  207. static void mmc_omap_start_request(struct mmc_omap_host *host,
  208. struct mmc_request *req);
  209. static void mmc_omap_slot_release_work(struct work_struct *work)
  210. {
  211. struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
  212. slot_release_work);
  213. struct mmc_omap_slot *next_slot = host->next_slot;
  214. struct mmc_request *rq;
  215. host->next_slot = NULL;
  216. mmc_omap_select_slot(next_slot, 1);
  217. rq = next_slot->mrq;
  218. next_slot->mrq = NULL;
  219. mmc_omap_start_request(host, rq);
  220. }
  221. static void mmc_omap_release_slot(struct mmc_omap_slot *slot, int clk_enabled)
  222. {
  223. struct mmc_omap_host *host = slot->host;
  224. unsigned long flags;
  225. int i;
  226. BUG_ON(slot == NULL || host->mmc == NULL);
  227. if (clk_enabled)
  228. /* Keeps clock running for at least 8 cycles on valid freq */
  229. mod_timer(&host->clk_timer, jiffies + HZ/10);
  230. else {
  231. del_timer(&host->clk_timer);
  232. mmc_omap_fclk_offdelay(slot);
  233. mmc_omap_fclk_enable(host, 0);
  234. }
  235. spin_lock_irqsave(&host->slot_lock, flags);
  236. /* Check for any pending requests */
  237. for (i = 0; i < host->nr_slots; i++) {
  238. struct mmc_omap_slot *new_slot;
  239. if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
  240. continue;
  241. BUG_ON(host->next_slot != NULL);
  242. new_slot = host->slots[i];
  243. /* The current slot should not have a request in queue */
  244. BUG_ON(new_slot == host->current_slot);
  245. host->next_slot = new_slot;
  246. host->mmc = new_slot->mmc;
  247. spin_unlock_irqrestore(&host->slot_lock, flags);
  248. queue_work(host->mmc_omap_wq, &host->slot_release_work);
  249. return;
  250. }
  251. host->mmc = NULL;
  252. wake_up(&host->slot_wq);
  253. spin_unlock_irqrestore(&host->slot_lock, flags);
  254. }
  255. static inline
  256. int mmc_omap_cover_is_open(struct mmc_omap_slot *slot)
  257. {
  258. if (slot->pdata->get_cover_state)
  259. return slot->pdata->get_cover_state(mmc_dev(slot->mmc),
  260. slot->id);
  261. return 0;
  262. }
  263. static ssize_t
  264. mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
  265. char *buf)
  266. {
  267. struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
  268. struct mmc_omap_slot *slot = mmc_priv(mmc);
  269. return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" :
  270. "closed");
  271. }
  272. static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
  273. static ssize_t
  274. mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
  275. char *buf)
  276. {
  277. struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
  278. struct mmc_omap_slot *slot = mmc_priv(mmc);
  279. return sprintf(buf, "%s\n", slot->pdata->name);
  280. }
  281. static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
  282. static void
  283. mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
  284. {
  285. u32 cmdreg;
  286. u32 resptype;
  287. u32 cmdtype;
  288. u16 irq_mask;
  289. host->cmd = cmd;
  290. resptype = 0;
  291. cmdtype = 0;
  292. /* Our hardware needs to know exact type */
  293. switch (mmc_resp_type(cmd)) {
  294. case MMC_RSP_NONE:
  295. break;
  296. case MMC_RSP_R1:
  297. case MMC_RSP_R1B:
  298. /* resp 1, 1b, 6, 7 */
  299. resptype = 1;
  300. break;
  301. case MMC_RSP_R2:
  302. resptype = 2;
  303. break;
  304. case MMC_RSP_R3:
  305. resptype = 3;
  306. break;
  307. default:
  308. dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
  309. break;
  310. }
  311. if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
  312. cmdtype = OMAP_MMC_CMDTYPE_ADTC;
  313. } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
  314. cmdtype = OMAP_MMC_CMDTYPE_BC;
  315. } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
  316. cmdtype = OMAP_MMC_CMDTYPE_BCR;
  317. } else {
  318. cmdtype = OMAP_MMC_CMDTYPE_AC;
  319. }
  320. cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
  321. if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
  322. cmdreg |= 1 << 6;
  323. if (cmd->flags & MMC_RSP_BUSY)
  324. cmdreg |= 1 << 11;
  325. if (host->data && !(host->data->flags & MMC_DATA_WRITE))
  326. cmdreg |= 1 << 15;
  327. mod_timer(&host->cmd_abort_timer, jiffies + HZ/2);
  328. OMAP_MMC_WRITE(host, CTO, 200);
  329. OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
  330. OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
  331. irq_mask = OMAP_MMC_STAT_A_EMPTY | OMAP_MMC_STAT_A_FULL |
  332. OMAP_MMC_STAT_CMD_CRC | OMAP_MMC_STAT_CMD_TOUT |
  333. OMAP_MMC_STAT_DATA_CRC | OMAP_MMC_STAT_DATA_TOUT |
  334. OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR |
  335. OMAP_MMC_STAT_END_OF_DATA;
  336. if (cmd->opcode == MMC_ERASE)
  337. irq_mask &= ~OMAP_MMC_STAT_DATA_TOUT;
  338. OMAP_MMC_WRITE(host, IE, irq_mask);
  339. OMAP_MMC_WRITE(host, CMD, cmdreg);
  340. }
  341. static void
  342. mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data,
  343. int abort)
  344. {
  345. enum dma_data_direction dma_data_dir;
  346. struct device *dev = mmc_dev(host->mmc);
  347. struct dma_chan *c;
  348. if (data->flags & MMC_DATA_WRITE) {
  349. dma_data_dir = DMA_TO_DEVICE;
  350. c = host->dma_tx;
  351. } else {
  352. dma_data_dir = DMA_FROM_DEVICE;
  353. c = host->dma_rx;
  354. }
  355. if (c) {
  356. if (data->error) {
  357. dmaengine_terminate_all(c);
  358. /* Claim nothing transferred on error... */
  359. data->bytes_xfered = 0;
  360. }
  361. dev = c->device->dev;
  362. }
  363. dma_unmap_sg(dev, data->sg, host->sg_len, dma_data_dir);
  364. }
  365. static void mmc_omap_send_stop_work(struct work_struct *work)
  366. {
  367. struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
  368. send_stop_work);
  369. struct mmc_omap_slot *slot = host->current_slot;
  370. struct mmc_data *data = host->stop_data;
  371. unsigned long tick_ns;
  372. tick_ns = DIV_ROUND_UP(NSEC_PER_SEC, slot->fclk_freq);
  373. ndelay(8*tick_ns);
  374. mmc_omap_start_command(host, data->stop);
  375. }
  376. static void
  377. mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
  378. {
  379. if (host->dma_in_use)
  380. mmc_omap_release_dma(host, data, data->error);
  381. host->data = NULL;
  382. host->sg_len = 0;
  383. /* NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing
  384. * dozens of requests until the card finishes writing data.
  385. * It'd be cheaper to just wait till an EOFB interrupt arrives...
  386. */
  387. if (!data->stop) {
  388. struct mmc_host *mmc;
  389. host->mrq = NULL;
  390. mmc = host->mmc;
  391. mmc_omap_release_slot(host->current_slot, 1);
  392. mmc_request_done(mmc, data->mrq);
  393. return;
  394. }
  395. host->stop_data = data;
  396. queue_work(host->mmc_omap_wq, &host->send_stop_work);
  397. }
  398. static void
  399. mmc_omap_send_abort(struct mmc_omap_host *host, int maxloops)
  400. {
  401. struct mmc_omap_slot *slot = host->current_slot;
  402. unsigned int restarts, passes, timeout;
  403. u16 stat = 0;
  404. /* Sending abort takes 80 clocks. Have some extra and round up */
  405. timeout = DIV_ROUND_UP(120 * USEC_PER_SEC, slot->fclk_freq);
  406. restarts = 0;
  407. while (restarts < maxloops) {
  408. OMAP_MMC_WRITE(host, STAT, 0xFFFF);
  409. OMAP_MMC_WRITE(host, CMD, (3 << 12) | (1 << 7));
  410. passes = 0;
  411. while (passes < timeout) {
  412. stat = OMAP_MMC_READ(host, STAT);
  413. if (stat & OMAP_MMC_STAT_END_OF_CMD)
  414. goto out;
  415. udelay(1);
  416. passes++;
  417. }
  418. restarts++;
  419. }
  420. out:
  421. OMAP_MMC_WRITE(host, STAT, stat);
  422. }
  423. static void
  424. mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data)
  425. {
  426. if (host->dma_in_use)
  427. mmc_omap_release_dma(host, data, 1);
  428. host->data = NULL;
  429. host->sg_len = 0;
  430. mmc_omap_send_abort(host, 10000);
  431. }
  432. static void
  433. mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
  434. {
  435. unsigned long flags;
  436. int done;
  437. if (!host->dma_in_use) {
  438. mmc_omap_xfer_done(host, data);
  439. return;
  440. }
  441. done = 0;
  442. spin_lock_irqsave(&host->dma_lock, flags);
  443. if (host->dma_done)
  444. done = 1;
  445. else
  446. host->brs_received = 1;
  447. spin_unlock_irqrestore(&host->dma_lock, flags);
  448. if (done)
  449. mmc_omap_xfer_done(host, data);
  450. }
  451. static void
  452. mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
  453. {
  454. unsigned long flags;
  455. int done;
  456. done = 0;
  457. spin_lock_irqsave(&host->dma_lock, flags);
  458. if (host->brs_received)
  459. done = 1;
  460. else
  461. host->dma_done = 1;
  462. spin_unlock_irqrestore(&host->dma_lock, flags);
  463. if (done)
  464. mmc_omap_xfer_done(host, data);
  465. }
  466. static void
  467. mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
  468. {
  469. host->cmd = NULL;
  470. del_timer(&host->cmd_abort_timer);
  471. if (cmd->flags & MMC_RSP_PRESENT) {
  472. if (cmd->flags & MMC_RSP_136) {
  473. /* response type 2 */
  474. cmd->resp[3] =
  475. OMAP_MMC_READ(host, RSP0) |
  476. (OMAP_MMC_READ(host, RSP1) << 16);
  477. cmd->resp[2] =
  478. OMAP_MMC_READ(host, RSP2) |
  479. (OMAP_MMC_READ(host, RSP3) << 16);
  480. cmd->resp[1] =
  481. OMAP_MMC_READ(host, RSP4) |
  482. (OMAP_MMC_READ(host, RSP5) << 16);
  483. cmd->resp[0] =
  484. OMAP_MMC_READ(host, RSP6) |
  485. (OMAP_MMC_READ(host, RSP7) << 16);
  486. } else {
  487. /* response types 1, 1b, 3, 4, 5, 6 */
  488. cmd->resp[0] =
  489. OMAP_MMC_READ(host, RSP6) |
  490. (OMAP_MMC_READ(host, RSP7) << 16);
  491. }
  492. }
  493. if (host->data == NULL || cmd->error) {
  494. struct mmc_host *mmc;
  495. if (host->data != NULL)
  496. mmc_omap_abort_xfer(host, host->data);
  497. host->mrq = NULL;
  498. mmc = host->mmc;
  499. mmc_omap_release_slot(host->current_slot, 1);
  500. mmc_request_done(mmc, cmd->mrq);
  501. }
  502. }
  503. /*
  504. * Abort stuck command. Can occur when card is removed while it is being
  505. * read.
  506. */
  507. static void mmc_omap_abort_command(struct work_struct *work)
  508. {
  509. struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
  510. cmd_abort_work);
  511. BUG_ON(!host->cmd);
  512. dev_dbg(mmc_dev(host->mmc), "Aborting stuck command CMD%d\n",
  513. host->cmd->opcode);
  514. if (host->cmd->error == 0)
  515. host->cmd->error = -ETIMEDOUT;
  516. if (host->data == NULL) {
  517. struct mmc_command *cmd;
  518. struct mmc_host *mmc;
  519. cmd = host->cmd;
  520. host->cmd = NULL;
  521. mmc_omap_send_abort(host, 10000);
  522. host->mrq = NULL;
  523. mmc = host->mmc;
  524. mmc_omap_release_slot(host->current_slot, 1);
  525. mmc_request_done(mmc, cmd->mrq);
  526. } else
  527. mmc_omap_cmd_done(host, host->cmd);
  528. host->abort = 0;
  529. enable_irq(host->irq);
  530. }
  531. static void
  532. mmc_omap_cmd_timer(struct timer_list *t)
  533. {
  534. struct mmc_omap_host *host = from_timer(host, t, cmd_abort_timer);
  535. unsigned long flags;
  536. spin_lock_irqsave(&host->slot_lock, flags);
  537. if (host->cmd != NULL && !host->abort) {
  538. OMAP_MMC_WRITE(host, IE, 0);
  539. disable_irq(host->irq);
  540. host->abort = 1;
  541. queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
  542. }
  543. spin_unlock_irqrestore(&host->slot_lock, flags);
  544. }
  545. /* PIO only */
  546. static void
  547. mmc_omap_sg_to_buf(struct mmc_omap_host *host)
  548. {
  549. struct scatterlist *sg;
  550. sg = host->data->sg + host->sg_idx;
  551. host->buffer_bytes_left = sg->length;
  552. host->buffer = sg_virt(sg);
  553. if (host->buffer_bytes_left > host->total_bytes_left)
  554. host->buffer_bytes_left = host->total_bytes_left;
  555. }
  556. static void
  557. mmc_omap_clk_timer(struct timer_list *t)
  558. {
  559. struct mmc_omap_host *host = from_timer(host, t, clk_timer);
  560. mmc_omap_fclk_enable(host, 0);
  561. }
  562. /* PIO only */
  563. static void
  564. mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
  565. {
  566. int n, nwords;
  567. if (host->buffer_bytes_left == 0) {
  568. host->sg_idx++;
  569. BUG_ON(host->sg_idx == host->sg_len);
  570. mmc_omap_sg_to_buf(host);
  571. }
  572. n = 64;
  573. if (n > host->buffer_bytes_left)
  574. n = host->buffer_bytes_left;
  575. /* Round up to handle odd number of bytes to transfer */
  576. nwords = DIV_ROUND_UP(n, 2);
  577. host->buffer_bytes_left -= n;
  578. host->total_bytes_left -= n;
  579. host->data->bytes_xfered += n;
  580. if (write) {
  581. __raw_writesw(host->virt_base + OMAP_MMC_REG(host, DATA),
  582. host->buffer, nwords);
  583. } else {
  584. __raw_readsw(host->virt_base + OMAP_MMC_REG(host, DATA),
  585. host->buffer, nwords);
  586. }
  587. host->buffer += nwords;
  588. }
  589. #ifdef CONFIG_MMC_DEBUG
  590. static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status)
  591. {
  592. static const char *mmc_omap_status_bits[] = {
  593. "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
  594. "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
  595. };
  596. int i;
  597. char res[64], *buf = res;
  598. buf += sprintf(buf, "MMC IRQ 0x%x:", status);
  599. for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
  600. if (status & (1 << i))
  601. buf += sprintf(buf, " %s", mmc_omap_status_bits[i]);
  602. dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
  603. }
  604. #else
  605. static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status)
  606. {
  607. }
  608. #endif
  609. static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
  610. {
  611. struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
  612. u16 status;
  613. int end_command;
  614. int end_transfer;
  615. int transfer_error, cmd_error;
  616. if (host->cmd == NULL && host->data == NULL) {
  617. status = OMAP_MMC_READ(host, STAT);
  618. dev_info(mmc_dev(host->slots[0]->mmc),
  619. "Spurious IRQ 0x%04x\n", status);
  620. if (status != 0) {
  621. OMAP_MMC_WRITE(host, STAT, status);
  622. OMAP_MMC_WRITE(host, IE, 0);
  623. }
  624. return IRQ_HANDLED;
  625. }
  626. end_command = 0;
  627. end_transfer = 0;
  628. transfer_error = 0;
  629. cmd_error = 0;
  630. while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
  631. int cmd;
  632. OMAP_MMC_WRITE(host, STAT, status);
  633. if (host->cmd != NULL)
  634. cmd = host->cmd->opcode;
  635. else
  636. cmd = -1;
  637. dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
  638. status, cmd);
  639. mmc_omap_report_irq(host, status);
  640. if (host->total_bytes_left) {
  641. if ((status & OMAP_MMC_STAT_A_FULL) ||
  642. (status & OMAP_MMC_STAT_END_OF_DATA))
  643. mmc_omap_xfer_data(host, 0);
  644. if (status & OMAP_MMC_STAT_A_EMPTY)
  645. mmc_omap_xfer_data(host, 1);
  646. }
  647. if (status & OMAP_MMC_STAT_END_OF_DATA)
  648. end_transfer = 1;
  649. if (status & OMAP_MMC_STAT_DATA_TOUT) {
  650. dev_dbg(mmc_dev(host->mmc), "data timeout (CMD%d)\n",
  651. cmd);
  652. if (host->data) {
  653. host->data->error = -ETIMEDOUT;
  654. transfer_error = 1;
  655. }
  656. }
  657. if (status & OMAP_MMC_STAT_DATA_CRC) {
  658. if (host->data) {
  659. host->data->error = -EILSEQ;
  660. dev_dbg(mmc_dev(host->mmc),
  661. "data CRC error, bytes left %d\n",
  662. host->total_bytes_left);
  663. transfer_error = 1;
  664. } else {
  665. dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
  666. }
  667. }
  668. if (status & OMAP_MMC_STAT_CMD_TOUT) {
  669. /* Timeouts are routine with some commands */
  670. if (host->cmd) {
  671. struct mmc_omap_slot *slot =
  672. host->current_slot;
  673. if (slot == NULL ||
  674. !mmc_omap_cover_is_open(slot))
  675. dev_err(mmc_dev(host->mmc),
  676. "command timeout (CMD%d)\n",
  677. cmd);
  678. host->cmd->error = -ETIMEDOUT;
  679. end_command = 1;
  680. cmd_error = 1;
  681. }
  682. }
  683. if (status & OMAP_MMC_STAT_CMD_CRC) {
  684. if (host->cmd) {
  685. dev_err(mmc_dev(host->mmc),
  686. "command CRC error (CMD%d, arg 0x%08x)\n",
  687. cmd, host->cmd->arg);
  688. host->cmd->error = -EILSEQ;
  689. end_command = 1;
  690. cmd_error = 1;
  691. } else
  692. dev_err(mmc_dev(host->mmc),
  693. "command CRC error without cmd?\n");
  694. }
  695. if (status & OMAP_MMC_STAT_CARD_ERR) {
  696. dev_dbg(mmc_dev(host->mmc),
  697. "ignoring card status error (CMD%d)\n",
  698. cmd);
  699. end_command = 1;
  700. }
  701. /*
  702. * NOTE: On 1610 the END_OF_CMD may come too early when
  703. * starting a write
  704. */
  705. if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
  706. (!(status & OMAP_MMC_STAT_A_EMPTY))) {
  707. end_command = 1;
  708. }
  709. }
  710. if (cmd_error && host->data) {
  711. del_timer(&host->cmd_abort_timer);
  712. host->abort = 1;
  713. OMAP_MMC_WRITE(host, IE, 0);
  714. disable_irq_nosync(host->irq);
  715. queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
  716. return IRQ_HANDLED;
  717. }
  718. if (end_command && host->cmd)
  719. mmc_omap_cmd_done(host, host->cmd);
  720. if (host->data != NULL) {
  721. if (transfer_error)
  722. mmc_omap_xfer_done(host, host->data);
  723. else if (end_transfer)
  724. mmc_omap_end_of_data(host, host->data);
  725. }
  726. return IRQ_HANDLED;
  727. }
  728. void omap_mmc_notify_cover_event(struct device *dev, int num, int is_closed)
  729. {
  730. int cover_open;
  731. struct mmc_omap_host *host = dev_get_drvdata(dev);
  732. struct mmc_omap_slot *slot = host->slots[num];
  733. BUG_ON(num >= host->nr_slots);
  734. /* Other subsystems can call in here before we're initialised. */
  735. if (host->nr_slots == 0 || !host->slots[num])
  736. return;
  737. cover_open = mmc_omap_cover_is_open(slot);
  738. if (cover_open != slot->cover_open) {
  739. slot->cover_open = cover_open;
  740. sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch");
  741. }
  742. tasklet_hi_schedule(&slot->cover_tasklet);
  743. }
  744. static void mmc_omap_cover_timer(struct timer_list *t)
  745. {
  746. struct mmc_omap_slot *slot = from_timer(slot, t, cover_timer);
  747. tasklet_schedule(&slot->cover_tasklet);
  748. }
  749. static void mmc_omap_cover_handler(unsigned long param)
  750. {
  751. struct mmc_omap_slot *slot = (struct mmc_omap_slot *)param;
  752. int cover_open = mmc_omap_cover_is_open(slot);
  753. mmc_detect_change(slot->mmc, 0);
  754. if (!cover_open)
  755. return;
  756. /*
  757. * If no card is inserted, we postpone polling until
  758. * the cover has been closed.
  759. */
  760. if (slot->mmc->card == NULL)
  761. return;
  762. mod_timer(&slot->cover_timer,
  763. jiffies + msecs_to_jiffies(OMAP_MMC_COVER_POLL_DELAY));
  764. }
  765. static void mmc_omap_dma_callback(void *priv)
  766. {
  767. struct mmc_omap_host *host = priv;
  768. struct mmc_data *data = host->data;
  769. /* If we got to the end of DMA, assume everything went well */
  770. data->bytes_xfered += data->blocks * data->blksz;
  771. mmc_omap_dma_done(host, data);
  772. }
  773. static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
  774. {
  775. u16 reg;
  776. reg = OMAP_MMC_READ(host, SDIO);
  777. reg &= ~(1 << 5);
  778. OMAP_MMC_WRITE(host, SDIO, reg);
  779. /* Set maximum timeout */
  780. OMAP_MMC_WRITE(host, CTO, 0xfd);
  781. }
  782. static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
  783. {
  784. unsigned int timeout, cycle_ns;
  785. u16 reg;
  786. cycle_ns = 1000000000 / host->current_slot->fclk_freq;
  787. timeout = req->data->timeout_ns / cycle_ns;
  788. timeout += req->data->timeout_clks;
  789. /* Check if we need to use timeout multiplier register */
  790. reg = OMAP_MMC_READ(host, SDIO);
  791. if (timeout > 0xffff) {
  792. reg |= (1 << 5);
  793. timeout /= 1024;
  794. } else
  795. reg &= ~(1 << 5);
  796. OMAP_MMC_WRITE(host, SDIO, reg);
  797. OMAP_MMC_WRITE(host, DTO, timeout);
  798. }
  799. static void
  800. mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
  801. {
  802. struct mmc_data *data = req->data;
  803. int i, use_dma = 1, block_size;
  804. struct scatterlist *sg;
  805. unsigned sg_len;
  806. host->data = data;
  807. if (data == NULL) {
  808. OMAP_MMC_WRITE(host, BLEN, 0);
  809. OMAP_MMC_WRITE(host, NBLK, 0);
  810. OMAP_MMC_WRITE(host, BUF, 0);
  811. host->dma_in_use = 0;
  812. set_cmd_timeout(host, req);
  813. return;
  814. }
  815. block_size = data->blksz;
  816. OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
  817. OMAP_MMC_WRITE(host, BLEN, block_size - 1);
  818. set_data_timeout(host, req);
  819. /* cope with calling layer confusion; it issues "single
  820. * block" writes using multi-block scatterlists.
  821. */
  822. sg_len = (data->blocks == 1) ? 1 : data->sg_len;
  823. /* Only do DMA for entire blocks */
  824. for_each_sg(data->sg, sg, sg_len, i) {
  825. if ((sg->length % block_size) != 0) {
  826. use_dma = 0;
  827. break;
  828. }
  829. }
  830. host->sg_idx = 0;
  831. if (use_dma) {
  832. enum dma_data_direction dma_data_dir;
  833. struct dma_async_tx_descriptor *tx;
  834. struct dma_chan *c;
  835. u32 burst, *bp;
  836. u16 buf;
  837. /*
  838. * FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx
  839. * and 24xx. Use 16 or 32 word frames when the
  840. * blocksize is at least that large. Blocksize is
  841. * usually 512 bytes; but not for some SD reads.
  842. */
  843. burst = mmc_omap15xx() ? 32 : 64;
  844. if (burst > data->blksz)
  845. burst = data->blksz;
  846. burst >>= 1;
  847. if (data->flags & MMC_DATA_WRITE) {
  848. c = host->dma_tx;
  849. bp = &host->dma_tx_burst;
  850. buf = 0x0f80 | (burst - 1) << 0;
  851. dma_data_dir = DMA_TO_DEVICE;
  852. } else {
  853. c = host->dma_rx;
  854. bp = &host->dma_rx_burst;
  855. buf = 0x800f | (burst - 1) << 8;
  856. dma_data_dir = DMA_FROM_DEVICE;
  857. }
  858. if (!c)
  859. goto use_pio;
  860. /* Only reconfigure if we have a different burst size */
  861. if (*bp != burst) {
  862. struct dma_slave_config cfg = {
  863. .src_addr = host->phys_base +
  864. OMAP_MMC_REG(host, DATA),
  865. .dst_addr = host->phys_base +
  866. OMAP_MMC_REG(host, DATA),
  867. .src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES,
  868. .dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES,
  869. .src_maxburst = burst,
  870. .dst_maxburst = burst,
  871. };
  872. if (dmaengine_slave_config(c, &cfg))
  873. goto use_pio;
  874. *bp = burst;
  875. }
  876. host->sg_len = dma_map_sg(c->device->dev, data->sg, sg_len,
  877. dma_data_dir);
  878. if (host->sg_len == 0)
  879. goto use_pio;
  880. tx = dmaengine_prep_slave_sg(c, data->sg, host->sg_len,
  881. data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
  882. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  883. if (!tx)
  884. goto use_pio;
  885. OMAP_MMC_WRITE(host, BUF, buf);
  886. tx->callback = mmc_omap_dma_callback;
  887. tx->callback_param = host;
  888. dmaengine_submit(tx);
  889. host->brs_received = 0;
  890. host->dma_done = 0;
  891. host->dma_in_use = 1;
  892. return;
  893. }
  894. use_pio:
  895. /* Revert to PIO? */
  896. OMAP_MMC_WRITE(host, BUF, 0x1f1f);
  897. host->total_bytes_left = data->blocks * block_size;
  898. host->sg_len = sg_len;
  899. mmc_omap_sg_to_buf(host);
  900. host->dma_in_use = 0;
  901. }
  902. static void mmc_omap_start_request(struct mmc_omap_host *host,
  903. struct mmc_request *req)
  904. {
  905. BUG_ON(host->mrq != NULL);
  906. host->mrq = req;
  907. /* only touch fifo AFTER the controller readies it */
  908. mmc_omap_prepare_data(host, req);
  909. mmc_omap_start_command(host, req->cmd);
  910. if (host->dma_in_use) {
  911. struct dma_chan *c = host->data->flags & MMC_DATA_WRITE ?
  912. host->dma_tx : host->dma_rx;
  913. dma_async_issue_pending(c);
  914. }
  915. }
  916. static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
  917. {
  918. struct mmc_omap_slot *slot = mmc_priv(mmc);
  919. struct mmc_omap_host *host = slot->host;
  920. unsigned long flags;
  921. spin_lock_irqsave(&host->slot_lock, flags);
  922. if (host->mmc != NULL) {
  923. BUG_ON(slot->mrq != NULL);
  924. slot->mrq = req;
  925. spin_unlock_irqrestore(&host->slot_lock, flags);
  926. return;
  927. } else
  928. host->mmc = mmc;
  929. spin_unlock_irqrestore(&host->slot_lock, flags);
  930. mmc_omap_select_slot(slot, 1);
  931. mmc_omap_start_request(host, req);
  932. }
  933. static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on,
  934. int vdd)
  935. {
  936. struct mmc_omap_host *host;
  937. host = slot->host;
  938. if (slot->pdata->set_power != NULL)
  939. slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on,
  940. vdd);
  941. if (mmc_omap2()) {
  942. u16 w;
  943. if (power_on) {
  944. w = OMAP_MMC_READ(host, CON);
  945. OMAP_MMC_WRITE(host, CON, w | (1 << 11));
  946. } else {
  947. w = OMAP_MMC_READ(host, CON);
  948. OMAP_MMC_WRITE(host, CON, w & ~(1 << 11));
  949. }
  950. }
  951. }
  952. static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
  953. {
  954. struct mmc_omap_slot *slot = mmc_priv(mmc);
  955. struct mmc_omap_host *host = slot->host;
  956. int func_clk_rate = clk_get_rate(host->fclk);
  957. int dsor;
  958. if (ios->clock == 0)
  959. return 0;
  960. dsor = func_clk_rate / ios->clock;
  961. if (dsor < 1)
  962. dsor = 1;
  963. if (func_clk_rate / dsor > ios->clock)
  964. dsor++;
  965. if (dsor > 250)
  966. dsor = 250;
  967. slot->fclk_freq = func_clk_rate / dsor;
  968. if (ios->bus_width == MMC_BUS_WIDTH_4)
  969. dsor |= 1 << 15;
  970. return dsor;
  971. }
  972. static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  973. {
  974. struct mmc_omap_slot *slot = mmc_priv(mmc);
  975. struct mmc_omap_host *host = slot->host;
  976. int i, dsor;
  977. int clk_enabled, init_stream;
  978. mmc_omap_select_slot(slot, 0);
  979. dsor = mmc_omap_calc_divisor(mmc, ios);
  980. if (ios->vdd != slot->vdd)
  981. slot->vdd = ios->vdd;
  982. clk_enabled = 0;
  983. init_stream = 0;
  984. switch (ios->power_mode) {
  985. case MMC_POWER_OFF:
  986. mmc_omap_set_power(slot, 0, ios->vdd);
  987. break;
  988. case MMC_POWER_UP:
  989. /* Cannot touch dsor yet, just power up MMC */
  990. mmc_omap_set_power(slot, 1, ios->vdd);
  991. slot->power_mode = ios->power_mode;
  992. goto exit;
  993. case MMC_POWER_ON:
  994. mmc_omap_fclk_enable(host, 1);
  995. clk_enabled = 1;
  996. dsor |= 1 << 11;
  997. if (slot->power_mode != MMC_POWER_ON)
  998. init_stream = 1;
  999. break;
  1000. }
  1001. slot->power_mode = ios->power_mode;
  1002. if (slot->bus_mode != ios->bus_mode) {
  1003. if (slot->pdata->set_bus_mode != NULL)
  1004. slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id,
  1005. ios->bus_mode);
  1006. slot->bus_mode = ios->bus_mode;
  1007. }
  1008. /* On insanely high arm_per frequencies something sometimes
  1009. * goes somehow out of sync, and the POW bit is not being set,
  1010. * which results in the while loop below getting stuck.
  1011. * Writing to the CON register twice seems to do the trick. */
  1012. for (i = 0; i < 2; i++)
  1013. OMAP_MMC_WRITE(host, CON, dsor);
  1014. slot->saved_con = dsor;
  1015. if (init_stream) {
  1016. /* worst case at 400kHz, 80 cycles makes 200 microsecs */
  1017. int usecs = 250;
  1018. /* Send clock cycles, poll completion */
  1019. OMAP_MMC_WRITE(host, IE, 0);
  1020. OMAP_MMC_WRITE(host, STAT, 0xffff);
  1021. OMAP_MMC_WRITE(host, CMD, 1 << 7);
  1022. while (usecs > 0 && (OMAP_MMC_READ(host, STAT) & 1) == 0) {
  1023. udelay(1);
  1024. usecs--;
  1025. }
  1026. OMAP_MMC_WRITE(host, STAT, 1);
  1027. }
  1028. exit:
  1029. mmc_omap_release_slot(slot, clk_enabled);
  1030. }
  1031. static const struct mmc_host_ops mmc_omap_ops = {
  1032. .request = mmc_omap_request,
  1033. .set_ios = mmc_omap_set_ios,
  1034. };
  1035. static int mmc_omap_new_slot(struct mmc_omap_host *host, int id)
  1036. {
  1037. struct mmc_omap_slot *slot = NULL;
  1038. struct mmc_host *mmc;
  1039. int r;
  1040. mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
  1041. if (mmc == NULL)
  1042. return -ENOMEM;
  1043. slot = mmc_priv(mmc);
  1044. slot->host = host;
  1045. slot->mmc = mmc;
  1046. slot->id = id;
  1047. slot->power_mode = MMC_POWER_UNDEFINED;
  1048. slot->pdata = &host->pdata->slots[id];
  1049. host->slots[id] = slot;
  1050. mmc->caps = 0;
  1051. if (host->pdata->slots[id].wires >= 4)
  1052. mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_ERASE;
  1053. mmc->ops = &mmc_omap_ops;
  1054. mmc->f_min = 400000;
  1055. if (mmc_omap2())
  1056. mmc->f_max = 48000000;
  1057. else
  1058. mmc->f_max = 24000000;
  1059. if (host->pdata->max_freq)
  1060. mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
  1061. mmc->ocr_avail = slot->pdata->ocr_mask;
  1062. /* Use scatterlist DMA to reduce per-transfer costs.
  1063. * NOTE max_seg_size assumption that small blocks aren't
  1064. * normally used (except e.g. for reading SD registers).
  1065. */
  1066. mmc->max_segs = 32;
  1067. mmc->max_blk_size = 2048; /* BLEN is 11 bits (+1) */
  1068. mmc->max_blk_count = 2048; /* NBLK is 11 bits (+1) */
  1069. mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
  1070. mmc->max_seg_size = mmc->max_req_size;
  1071. if (slot->pdata->get_cover_state != NULL) {
  1072. timer_setup(&slot->cover_timer, mmc_omap_cover_timer, 0);
  1073. tasklet_init(&slot->cover_tasklet, mmc_omap_cover_handler,
  1074. (unsigned long)slot);
  1075. }
  1076. r = mmc_add_host(mmc);
  1077. if (r < 0)
  1078. goto err_remove_host;
  1079. if (slot->pdata->name != NULL) {
  1080. r = device_create_file(&mmc->class_dev,
  1081. &dev_attr_slot_name);
  1082. if (r < 0)
  1083. goto err_remove_host;
  1084. }
  1085. if (slot->pdata->get_cover_state != NULL) {
  1086. r = device_create_file(&mmc->class_dev,
  1087. &dev_attr_cover_switch);
  1088. if (r < 0)
  1089. goto err_remove_slot_name;
  1090. tasklet_schedule(&slot->cover_tasklet);
  1091. }
  1092. return 0;
  1093. err_remove_slot_name:
  1094. if (slot->pdata->name != NULL)
  1095. device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
  1096. err_remove_host:
  1097. mmc_remove_host(mmc);
  1098. mmc_free_host(mmc);
  1099. return r;
  1100. }
  1101. static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
  1102. {
  1103. struct mmc_host *mmc = slot->mmc;
  1104. if (slot->pdata->name != NULL)
  1105. device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
  1106. if (slot->pdata->get_cover_state != NULL)
  1107. device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
  1108. tasklet_kill(&slot->cover_tasklet);
  1109. del_timer_sync(&slot->cover_timer);
  1110. flush_workqueue(slot->host->mmc_omap_wq);
  1111. mmc_remove_host(mmc);
  1112. mmc_free_host(mmc);
  1113. }
  1114. static int mmc_omap_probe(struct platform_device *pdev)
  1115. {
  1116. struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
  1117. struct mmc_omap_host *host = NULL;
  1118. struct resource *res;
  1119. int i, ret = 0;
  1120. int irq;
  1121. if (pdata == NULL) {
  1122. dev_err(&pdev->dev, "platform data missing\n");
  1123. return -ENXIO;
  1124. }
  1125. if (pdata->nr_slots == 0) {
  1126. dev_err(&pdev->dev, "no slots\n");
  1127. return -EPROBE_DEFER;
  1128. }
  1129. host = devm_kzalloc(&pdev->dev, sizeof(struct mmc_omap_host),
  1130. GFP_KERNEL);
  1131. if (host == NULL)
  1132. return -ENOMEM;
  1133. irq = platform_get_irq(pdev, 0);
  1134. if (irq < 0)
  1135. return -ENXIO;
  1136. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1137. host->virt_base = devm_ioremap_resource(&pdev->dev, res);
  1138. if (IS_ERR(host->virt_base))
  1139. return PTR_ERR(host->virt_base);
  1140. INIT_WORK(&host->slot_release_work, mmc_omap_slot_release_work);
  1141. INIT_WORK(&host->send_stop_work, mmc_omap_send_stop_work);
  1142. INIT_WORK(&host->cmd_abort_work, mmc_omap_abort_command);
  1143. timer_setup(&host->cmd_abort_timer, mmc_omap_cmd_timer, 0);
  1144. spin_lock_init(&host->clk_lock);
  1145. timer_setup(&host->clk_timer, mmc_omap_clk_timer, 0);
  1146. spin_lock_init(&host->dma_lock);
  1147. spin_lock_init(&host->slot_lock);
  1148. init_waitqueue_head(&host->slot_wq);
  1149. host->pdata = pdata;
  1150. host->features = host->pdata->slots[0].features;
  1151. host->dev = &pdev->dev;
  1152. platform_set_drvdata(pdev, host);
  1153. host->id = pdev->id;
  1154. host->irq = irq;
  1155. host->phys_base = res->start;
  1156. host->iclk = clk_get(&pdev->dev, "ick");
  1157. if (IS_ERR(host->iclk))
  1158. return PTR_ERR(host->iclk);
  1159. clk_enable(host->iclk);
  1160. host->fclk = clk_get(&pdev->dev, "fck");
  1161. if (IS_ERR(host->fclk)) {
  1162. ret = PTR_ERR(host->fclk);
  1163. goto err_free_iclk;
  1164. }
  1165. host->dma_tx_burst = -1;
  1166. host->dma_rx_burst = -1;
  1167. host->dma_tx = dma_request_chan(&pdev->dev, "tx");
  1168. if (IS_ERR(host->dma_tx)) {
  1169. ret = PTR_ERR(host->dma_tx);
  1170. if (ret == -EPROBE_DEFER) {
  1171. clk_put(host->fclk);
  1172. goto err_free_iclk;
  1173. }
  1174. host->dma_tx = NULL;
  1175. dev_warn(host->dev, "TX DMA channel request failed\n");
  1176. }
  1177. host->dma_rx = dma_request_chan(&pdev->dev, "rx");
  1178. if (IS_ERR(host->dma_rx)) {
  1179. ret = PTR_ERR(host->dma_rx);
  1180. if (ret == -EPROBE_DEFER) {
  1181. if (host->dma_tx)
  1182. dma_release_channel(host->dma_tx);
  1183. clk_put(host->fclk);
  1184. goto err_free_iclk;
  1185. }
  1186. host->dma_rx = NULL;
  1187. dev_warn(host->dev, "RX DMA channel request failed\n");
  1188. }
  1189. ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
  1190. if (ret)
  1191. goto err_free_dma;
  1192. if (pdata->init != NULL) {
  1193. ret = pdata->init(&pdev->dev);
  1194. if (ret < 0)
  1195. goto err_free_irq;
  1196. }
  1197. host->nr_slots = pdata->nr_slots;
  1198. host->reg_shift = (mmc_omap7xx() ? 1 : 2);
  1199. host->mmc_omap_wq = alloc_workqueue("mmc_omap", 0, 0);
  1200. if (!host->mmc_omap_wq) {
  1201. ret = -ENOMEM;
  1202. goto err_plat_cleanup;
  1203. }
  1204. for (i = 0; i < pdata->nr_slots; i++) {
  1205. ret = mmc_omap_new_slot(host, i);
  1206. if (ret < 0) {
  1207. while (--i >= 0)
  1208. mmc_omap_remove_slot(host->slots[i]);
  1209. goto err_destroy_wq;
  1210. }
  1211. }
  1212. return 0;
  1213. err_destroy_wq:
  1214. destroy_workqueue(host->mmc_omap_wq);
  1215. err_plat_cleanup:
  1216. if (pdata->cleanup)
  1217. pdata->cleanup(&pdev->dev);
  1218. err_free_irq:
  1219. free_irq(host->irq, host);
  1220. err_free_dma:
  1221. if (host->dma_tx)
  1222. dma_release_channel(host->dma_tx);
  1223. if (host->dma_rx)
  1224. dma_release_channel(host->dma_rx);
  1225. clk_put(host->fclk);
  1226. err_free_iclk:
  1227. clk_disable(host->iclk);
  1228. clk_put(host->iclk);
  1229. return ret;
  1230. }
  1231. static int mmc_omap_remove(struct platform_device *pdev)
  1232. {
  1233. struct mmc_omap_host *host = platform_get_drvdata(pdev);
  1234. int i;
  1235. BUG_ON(host == NULL);
  1236. for (i = 0; i < host->nr_slots; i++)
  1237. mmc_omap_remove_slot(host->slots[i]);
  1238. if (host->pdata->cleanup)
  1239. host->pdata->cleanup(&pdev->dev);
  1240. mmc_omap_fclk_enable(host, 0);
  1241. free_irq(host->irq, host);
  1242. clk_put(host->fclk);
  1243. clk_disable(host->iclk);
  1244. clk_put(host->iclk);
  1245. if (host->dma_tx)
  1246. dma_release_channel(host->dma_tx);
  1247. if (host->dma_rx)
  1248. dma_release_channel(host->dma_rx);
  1249. destroy_workqueue(host->mmc_omap_wq);
  1250. return 0;
  1251. }
  1252. #if IS_BUILTIN(CONFIG_OF)
  1253. static const struct of_device_id mmc_omap_match[] = {
  1254. { .compatible = "ti,omap2420-mmc", },
  1255. { },
  1256. };
  1257. MODULE_DEVICE_TABLE(of, mmc_omap_match);
  1258. #endif
  1259. static struct platform_driver mmc_omap_driver = {
  1260. .probe = mmc_omap_probe,
  1261. .remove = mmc_omap_remove,
  1262. .driver = {
  1263. .name = DRIVER_NAME,
  1264. .of_match_table = of_match_ptr(mmc_omap_match),
  1265. },
  1266. };
  1267. module_platform_driver(mmc_omap_driver);
  1268. MODULE_DESCRIPTION("OMAP Multimedia Card driver");
  1269. MODULE_LICENSE("GPL");
  1270. MODULE_ALIAS("platform:" DRIVER_NAME);
  1271. MODULE_AUTHOR("Juha Yrjölä");