omap_hsmmc.c 58 KB

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  1. /*
  2. * drivers/mmc/host/omap_hsmmc.c
  3. *
  4. * Driver for OMAP2430/3430 MMC controller.
  5. *
  6. * Copyright (C) 2007 Texas Instruments.
  7. *
  8. * Authors:
  9. * Syed Mohammed Khasim <x0khasim@ti.com>
  10. * Madhusudhan <madhu.cr@ti.com>
  11. * Mohit Jalori <mjalori@ti.com>
  12. *
  13. * This file is licensed under the terms of the GNU General Public License
  14. * version 2. This program is licensed "as is" without any warranty of any
  15. * kind, whether express or implied.
  16. */
  17. #include <linux/module.h>
  18. #include <linux/init.h>
  19. #include <linux/kernel.h>
  20. #include <linux/debugfs.h>
  21. #include <linux/dmaengine.h>
  22. #include <linux/seq_file.h>
  23. #include <linux/sizes.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/delay.h>
  26. #include <linux/dma-mapping.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/timer.h>
  29. #include <linux/clk.h>
  30. #include <linux/of.h>
  31. #include <linux/of_irq.h>
  32. #include <linux/of_gpio.h>
  33. #include <linux/of_device.h>
  34. #include <linux/mmc/host.h>
  35. #include <linux/mmc/core.h>
  36. #include <linux/mmc/mmc.h>
  37. #include <linux/mmc/slot-gpio.h>
  38. #include <linux/io.h>
  39. #include <linux/irq.h>
  40. #include <linux/gpio.h>
  41. #include <linux/regulator/consumer.h>
  42. #include <linux/pinctrl/consumer.h>
  43. #include <linux/pm_runtime.h>
  44. #include <linux/pm_wakeirq.h>
  45. #include <linux/platform_data/hsmmc-omap.h>
  46. /* OMAP HSMMC Host Controller Registers */
  47. #define OMAP_HSMMC_SYSSTATUS 0x0014
  48. #define OMAP_HSMMC_CON 0x002C
  49. #define OMAP_HSMMC_SDMASA 0x0100
  50. #define OMAP_HSMMC_BLK 0x0104
  51. #define OMAP_HSMMC_ARG 0x0108
  52. #define OMAP_HSMMC_CMD 0x010C
  53. #define OMAP_HSMMC_RSP10 0x0110
  54. #define OMAP_HSMMC_RSP32 0x0114
  55. #define OMAP_HSMMC_RSP54 0x0118
  56. #define OMAP_HSMMC_RSP76 0x011C
  57. #define OMAP_HSMMC_DATA 0x0120
  58. #define OMAP_HSMMC_PSTATE 0x0124
  59. #define OMAP_HSMMC_HCTL 0x0128
  60. #define OMAP_HSMMC_SYSCTL 0x012C
  61. #define OMAP_HSMMC_STAT 0x0130
  62. #define OMAP_HSMMC_IE 0x0134
  63. #define OMAP_HSMMC_ISE 0x0138
  64. #define OMAP_HSMMC_AC12 0x013C
  65. #define OMAP_HSMMC_CAPA 0x0140
  66. #define VS18 (1 << 26)
  67. #define VS30 (1 << 25)
  68. #define HSS (1 << 21)
  69. #define SDVS18 (0x5 << 9)
  70. #define SDVS30 (0x6 << 9)
  71. #define SDVS33 (0x7 << 9)
  72. #define SDVS_MASK 0x00000E00
  73. #define SDVSCLR 0xFFFFF1FF
  74. #define SDVSDET 0x00000400
  75. #define AUTOIDLE 0x1
  76. #define SDBP (1 << 8)
  77. #define DTO 0xe
  78. #define ICE 0x1
  79. #define ICS 0x2
  80. #define CEN (1 << 2)
  81. #define CLKD_MAX 0x3FF /* max clock divisor: 1023 */
  82. #define CLKD_MASK 0x0000FFC0
  83. #define CLKD_SHIFT 6
  84. #define DTO_MASK 0x000F0000
  85. #define DTO_SHIFT 16
  86. #define INIT_STREAM (1 << 1)
  87. #define ACEN_ACMD23 (2 << 2)
  88. #define DP_SELECT (1 << 21)
  89. #define DDIR (1 << 4)
  90. #define DMAE 0x1
  91. #define MSBS (1 << 5)
  92. #define BCE (1 << 1)
  93. #define FOUR_BIT (1 << 1)
  94. #define HSPE (1 << 2)
  95. #define IWE (1 << 24)
  96. #define DDR (1 << 19)
  97. #define CLKEXTFREE (1 << 16)
  98. #define CTPL (1 << 11)
  99. #define DW8 (1 << 5)
  100. #define OD 0x1
  101. #define STAT_CLEAR 0xFFFFFFFF
  102. #define INIT_STREAM_CMD 0x00000000
  103. #define DUAL_VOLT_OCR_BIT 7
  104. #define SRC (1 << 25)
  105. #define SRD (1 << 26)
  106. #define SOFTRESET (1 << 1)
  107. /* PSTATE */
  108. #define DLEV_DAT(x) (1 << (20 + (x)))
  109. /* Interrupt masks for IE and ISE register */
  110. #define CC_EN (1 << 0)
  111. #define TC_EN (1 << 1)
  112. #define BWR_EN (1 << 4)
  113. #define BRR_EN (1 << 5)
  114. #define CIRQ_EN (1 << 8)
  115. #define ERR_EN (1 << 15)
  116. #define CTO_EN (1 << 16)
  117. #define CCRC_EN (1 << 17)
  118. #define CEB_EN (1 << 18)
  119. #define CIE_EN (1 << 19)
  120. #define DTO_EN (1 << 20)
  121. #define DCRC_EN (1 << 21)
  122. #define DEB_EN (1 << 22)
  123. #define ACE_EN (1 << 24)
  124. #define CERR_EN (1 << 28)
  125. #define BADA_EN (1 << 29)
  126. #define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\
  127. DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \
  128. BRR_EN | BWR_EN | TC_EN | CC_EN)
  129. #define CNI (1 << 7)
  130. #define ACIE (1 << 4)
  131. #define ACEB (1 << 3)
  132. #define ACCE (1 << 2)
  133. #define ACTO (1 << 1)
  134. #define ACNE (1 << 0)
  135. #define MMC_AUTOSUSPEND_DELAY 100
  136. #define MMC_TIMEOUT_MS 20 /* 20 mSec */
  137. #define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */
  138. #define OMAP_MMC_MIN_CLOCK 400000
  139. #define OMAP_MMC_MAX_CLOCK 52000000
  140. #define DRIVER_NAME "omap_hsmmc"
  141. /*
  142. * One controller can have multiple slots, like on some omap boards using
  143. * omap.c controller driver. Luckily this is not currently done on any known
  144. * omap_hsmmc.c device.
  145. */
  146. #define mmc_pdata(host) host->pdata
  147. /*
  148. * MMC Host controller read/write API's
  149. */
  150. #define OMAP_HSMMC_READ(base, reg) \
  151. __raw_readl((base) + OMAP_HSMMC_##reg)
  152. #define OMAP_HSMMC_WRITE(base, reg, val) \
  153. __raw_writel((val), (base) + OMAP_HSMMC_##reg)
  154. struct omap_hsmmc_next {
  155. unsigned int dma_len;
  156. s32 cookie;
  157. };
  158. struct omap_hsmmc_host {
  159. struct device *dev;
  160. struct mmc_host *mmc;
  161. struct mmc_request *mrq;
  162. struct mmc_command *cmd;
  163. struct mmc_data *data;
  164. struct clk *fclk;
  165. struct clk *dbclk;
  166. struct regulator *pbias;
  167. bool pbias_enabled;
  168. void __iomem *base;
  169. int vqmmc_enabled;
  170. resource_size_t mapbase;
  171. spinlock_t irq_lock; /* Prevent races with irq handler */
  172. unsigned int dma_len;
  173. unsigned int dma_sg_idx;
  174. unsigned char bus_mode;
  175. unsigned char power_mode;
  176. int suspended;
  177. u32 con;
  178. u32 hctl;
  179. u32 sysctl;
  180. u32 capa;
  181. int irq;
  182. int wake_irq;
  183. int use_dma, dma_ch;
  184. struct dma_chan *tx_chan;
  185. struct dma_chan *rx_chan;
  186. int response_busy;
  187. int context_loss;
  188. int protect_card;
  189. int reqs_blocked;
  190. int req_in_progress;
  191. unsigned long clk_rate;
  192. unsigned int flags;
  193. #define AUTO_CMD23 (1 << 0) /* Auto CMD23 support */
  194. #define HSMMC_SDIO_IRQ_ENABLED (1 << 1) /* SDIO irq enabled */
  195. struct omap_hsmmc_next next_data;
  196. struct omap_hsmmc_platform_data *pdata;
  197. /* return MMC cover switch state, can be NULL if not supported.
  198. *
  199. * possible return values:
  200. * 0 - closed
  201. * 1 - open
  202. */
  203. int (*get_cover_state)(struct device *dev);
  204. int (*card_detect)(struct device *dev);
  205. };
  206. struct omap_mmc_of_data {
  207. u32 reg_offset;
  208. u8 controller_flags;
  209. };
  210. static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host);
  211. static int omap_hsmmc_card_detect(struct device *dev)
  212. {
  213. struct omap_hsmmc_host *host = dev_get_drvdata(dev);
  214. return mmc_gpio_get_cd(host->mmc);
  215. }
  216. static int omap_hsmmc_get_cover_state(struct device *dev)
  217. {
  218. struct omap_hsmmc_host *host = dev_get_drvdata(dev);
  219. return mmc_gpio_get_cd(host->mmc);
  220. }
  221. static int omap_hsmmc_enable_supply(struct mmc_host *mmc)
  222. {
  223. int ret;
  224. struct omap_hsmmc_host *host = mmc_priv(mmc);
  225. struct mmc_ios *ios = &mmc->ios;
  226. if (!IS_ERR(mmc->supply.vmmc)) {
  227. ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
  228. if (ret)
  229. return ret;
  230. }
  231. /* Enable interface voltage rail, if needed */
  232. if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
  233. ret = regulator_enable(mmc->supply.vqmmc);
  234. if (ret) {
  235. dev_err(mmc_dev(mmc), "vmmc_aux reg enable failed\n");
  236. goto err_vqmmc;
  237. }
  238. host->vqmmc_enabled = 1;
  239. }
  240. return 0;
  241. err_vqmmc:
  242. if (!IS_ERR(mmc->supply.vmmc))
  243. mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
  244. return ret;
  245. }
  246. static int omap_hsmmc_disable_supply(struct mmc_host *mmc)
  247. {
  248. int ret;
  249. int status;
  250. struct omap_hsmmc_host *host = mmc_priv(mmc);
  251. if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
  252. ret = regulator_disable(mmc->supply.vqmmc);
  253. if (ret) {
  254. dev_err(mmc_dev(mmc), "vmmc_aux reg disable failed\n");
  255. return ret;
  256. }
  257. host->vqmmc_enabled = 0;
  258. }
  259. if (!IS_ERR(mmc->supply.vmmc)) {
  260. ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
  261. if (ret)
  262. goto err_set_ocr;
  263. }
  264. return 0;
  265. err_set_ocr:
  266. if (!IS_ERR(mmc->supply.vqmmc)) {
  267. status = regulator_enable(mmc->supply.vqmmc);
  268. if (status)
  269. dev_err(mmc_dev(mmc), "vmmc_aux re-enable failed\n");
  270. }
  271. return ret;
  272. }
  273. static int omap_hsmmc_set_pbias(struct omap_hsmmc_host *host, bool power_on)
  274. {
  275. int ret;
  276. if (IS_ERR(host->pbias))
  277. return 0;
  278. if (power_on) {
  279. if (host->pbias_enabled == 0) {
  280. ret = regulator_enable(host->pbias);
  281. if (ret) {
  282. dev_err(host->dev, "pbias reg enable fail\n");
  283. return ret;
  284. }
  285. host->pbias_enabled = 1;
  286. }
  287. } else {
  288. if (host->pbias_enabled == 1) {
  289. ret = regulator_disable(host->pbias);
  290. if (ret) {
  291. dev_err(host->dev, "pbias reg disable fail\n");
  292. return ret;
  293. }
  294. host->pbias_enabled = 0;
  295. }
  296. }
  297. return 0;
  298. }
  299. static int omap_hsmmc_set_power(struct omap_hsmmc_host *host, int power_on)
  300. {
  301. struct mmc_host *mmc = host->mmc;
  302. int ret = 0;
  303. /*
  304. * If we don't see a Vcc regulator, assume it's a fixed
  305. * voltage always-on regulator.
  306. */
  307. if (IS_ERR(mmc->supply.vmmc))
  308. return 0;
  309. ret = omap_hsmmc_set_pbias(host, false);
  310. if (ret)
  311. return ret;
  312. /*
  313. * Assume Vcc regulator is used only to power the card ... OMAP
  314. * VDDS is used to power the pins, optionally with a transceiver to
  315. * support cards using voltages other than VDDS (1.8V nominal). When a
  316. * transceiver is used, DAT3..7 are muxed as transceiver control pins.
  317. *
  318. * In some cases this regulator won't support enable/disable;
  319. * e.g. it's a fixed rail for a WLAN chip.
  320. *
  321. * In other cases vcc_aux switches interface power. Example, for
  322. * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
  323. * chips/cards need an interface voltage rail too.
  324. */
  325. if (power_on) {
  326. ret = omap_hsmmc_enable_supply(mmc);
  327. if (ret)
  328. return ret;
  329. ret = omap_hsmmc_set_pbias(host, true);
  330. if (ret)
  331. goto err_set_voltage;
  332. } else {
  333. ret = omap_hsmmc_disable_supply(mmc);
  334. if (ret)
  335. return ret;
  336. }
  337. return 0;
  338. err_set_voltage:
  339. omap_hsmmc_disable_supply(mmc);
  340. return ret;
  341. }
  342. static int omap_hsmmc_disable_boot_regulator(struct regulator *reg)
  343. {
  344. int ret;
  345. if (IS_ERR(reg))
  346. return 0;
  347. if (regulator_is_enabled(reg)) {
  348. ret = regulator_enable(reg);
  349. if (ret)
  350. return ret;
  351. ret = regulator_disable(reg);
  352. if (ret)
  353. return ret;
  354. }
  355. return 0;
  356. }
  357. static int omap_hsmmc_disable_boot_regulators(struct omap_hsmmc_host *host)
  358. {
  359. struct mmc_host *mmc = host->mmc;
  360. int ret;
  361. /*
  362. * disable regulators enabled during boot and get the usecount
  363. * right so that regulators can be enabled/disabled by checking
  364. * the return value of regulator_is_enabled
  365. */
  366. ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vmmc);
  367. if (ret) {
  368. dev_err(host->dev, "fail to disable boot enabled vmmc reg\n");
  369. return ret;
  370. }
  371. ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vqmmc);
  372. if (ret) {
  373. dev_err(host->dev,
  374. "fail to disable boot enabled vmmc_aux reg\n");
  375. return ret;
  376. }
  377. ret = omap_hsmmc_disable_boot_regulator(host->pbias);
  378. if (ret) {
  379. dev_err(host->dev,
  380. "failed to disable boot enabled pbias reg\n");
  381. return ret;
  382. }
  383. return 0;
  384. }
  385. static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
  386. {
  387. int ret;
  388. struct mmc_host *mmc = host->mmc;
  389. ret = mmc_regulator_get_supply(mmc);
  390. if (ret)
  391. return ret;
  392. /* Allow an aux regulator */
  393. if (IS_ERR(mmc->supply.vqmmc)) {
  394. mmc->supply.vqmmc = devm_regulator_get_optional(host->dev,
  395. "vmmc_aux");
  396. if (IS_ERR(mmc->supply.vqmmc)) {
  397. ret = PTR_ERR(mmc->supply.vqmmc);
  398. if ((ret != -ENODEV) && host->dev->of_node)
  399. return ret;
  400. dev_dbg(host->dev, "unable to get vmmc_aux regulator %ld\n",
  401. PTR_ERR(mmc->supply.vqmmc));
  402. }
  403. }
  404. host->pbias = devm_regulator_get_optional(host->dev, "pbias");
  405. if (IS_ERR(host->pbias)) {
  406. ret = PTR_ERR(host->pbias);
  407. if ((ret != -ENODEV) && host->dev->of_node) {
  408. dev_err(host->dev,
  409. "SD card detect fail? enable CONFIG_REGULATOR_PBIAS\n");
  410. return ret;
  411. }
  412. dev_dbg(host->dev, "unable to get pbias regulator %ld\n",
  413. PTR_ERR(host->pbias));
  414. }
  415. /* For eMMC do not power off when not in sleep state */
  416. if (mmc_pdata(host)->no_regulator_off_init)
  417. return 0;
  418. ret = omap_hsmmc_disable_boot_regulators(host);
  419. if (ret)
  420. return ret;
  421. return 0;
  422. }
  423. static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id);
  424. static int omap_hsmmc_gpio_init(struct mmc_host *mmc,
  425. struct omap_hsmmc_host *host,
  426. struct omap_hsmmc_platform_data *pdata)
  427. {
  428. int ret;
  429. if (gpio_is_valid(pdata->gpio_cod)) {
  430. ret = mmc_gpio_request_cd(mmc, pdata->gpio_cod, 0);
  431. if (ret)
  432. return ret;
  433. host->get_cover_state = omap_hsmmc_get_cover_state;
  434. mmc_gpio_set_cd_isr(mmc, omap_hsmmc_cover_irq);
  435. } else if (gpio_is_valid(pdata->gpio_cd)) {
  436. ret = mmc_gpio_request_cd(mmc, pdata->gpio_cd, 0);
  437. if (ret)
  438. return ret;
  439. host->card_detect = omap_hsmmc_card_detect;
  440. }
  441. if (gpio_is_valid(pdata->gpio_wp)) {
  442. ret = mmc_gpio_request_ro(mmc, pdata->gpio_wp);
  443. if (ret)
  444. return ret;
  445. }
  446. return 0;
  447. }
  448. /*
  449. * Start clock to the card
  450. */
  451. static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
  452. {
  453. OMAP_HSMMC_WRITE(host->base, SYSCTL,
  454. OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
  455. }
  456. /*
  457. * Stop clock to the card
  458. */
  459. static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
  460. {
  461. OMAP_HSMMC_WRITE(host->base, SYSCTL,
  462. OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
  463. if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
  464. dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
  465. }
  466. static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
  467. struct mmc_command *cmd)
  468. {
  469. u32 irq_mask = INT_EN_MASK;
  470. unsigned long flags;
  471. if (host->use_dma)
  472. irq_mask &= ~(BRR_EN | BWR_EN);
  473. /* Disable timeout for erases */
  474. if (cmd->opcode == MMC_ERASE)
  475. irq_mask &= ~DTO_EN;
  476. spin_lock_irqsave(&host->irq_lock, flags);
  477. OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
  478. OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
  479. /* latch pending CIRQ, but don't signal MMC core */
  480. if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
  481. irq_mask |= CIRQ_EN;
  482. OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
  483. spin_unlock_irqrestore(&host->irq_lock, flags);
  484. }
  485. static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
  486. {
  487. u32 irq_mask = 0;
  488. unsigned long flags;
  489. spin_lock_irqsave(&host->irq_lock, flags);
  490. /* no transfer running but need to keep cirq if enabled */
  491. if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
  492. irq_mask |= CIRQ_EN;
  493. OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
  494. OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
  495. OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
  496. spin_unlock_irqrestore(&host->irq_lock, flags);
  497. }
  498. /* Calculate divisor for the given clock frequency */
  499. static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
  500. {
  501. u16 dsor = 0;
  502. if (ios->clock) {
  503. dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
  504. if (dsor > CLKD_MAX)
  505. dsor = CLKD_MAX;
  506. }
  507. return dsor;
  508. }
  509. static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
  510. {
  511. struct mmc_ios *ios = &host->mmc->ios;
  512. unsigned long regval;
  513. unsigned long timeout;
  514. unsigned long clkdiv;
  515. dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
  516. omap_hsmmc_stop_clock(host);
  517. regval = OMAP_HSMMC_READ(host->base, SYSCTL);
  518. regval = regval & ~(CLKD_MASK | DTO_MASK);
  519. clkdiv = calc_divisor(host, ios);
  520. regval = regval | (clkdiv << 6) | (DTO << 16);
  521. OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
  522. OMAP_HSMMC_WRITE(host->base, SYSCTL,
  523. OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
  524. /* Wait till the ICS bit is set */
  525. timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
  526. while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
  527. && time_before(jiffies, timeout))
  528. cpu_relax();
  529. /*
  530. * Enable High-Speed Support
  531. * Pre-Requisites
  532. * - Controller should support High-Speed-Enable Bit
  533. * - Controller should not be using DDR Mode
  534. * - Controller should advertise that it supports High Speed
  535. * in capabilities register
  536. * - MMC/SD clock coming out of controller > 25MHz
  537. */
  538. if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) &&
  539. (ios->timing != MMC_TIMING_MMC_DDR52) &&
  540. (ios->timing != MMC_TIMING_UHS_DDR50) &&
  541. ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
  542. regval = OMAP_HSMMC_READ(host->base, HCTL);
  543. if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
  544. regval |= HSPE;
  545. else
  546. regval &= ~HSPE;
  547. OMAP_HSMMC_WRITE(host->base, HCTL, regval);
  548. }
  549. omap_hsmmc_start_clock(host);
  550. }
  551. static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
  552. {
  553. struct mmc_ios *ios = &host->mmc->ios;
  554. u32 con;
  555. con = OMAP_HSMMC_READ(host->base, CON);
  556. if (ios->timing == MMC_TIMING_MMC_DDR52 ||
  557. ios->timing == MMC_TIMING_UHS_DDR50)
  558. con |= DDR; /* configure in DDR mode */
  559. else
  560. con &= ~DDR;
  561. switch (ios->bus_width) {
  562. case MMC_BUS_WIDTH_8:
  563. OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
  564. break;
  565. case MMC_BUS_WIDTH_4:
  566. OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
  567. OMAP_HSMMC_WRITE(host->base, HCTL,
  568. OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
  569. break;
  570. case MMC_BUS_WIDTH_1:
  571. OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
  572. OMAP_HSMMC_WRITE(host->base, HCTL,
  573. OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
  574. break;
  575. }
  576. }
  577. static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
  578. {
  579. struct mmc_ios *ios = &host->mmc->ios;
  580. u32 con;
  581. con = OMAP_HSMMC_READ(host->base, CON);
  582. if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
  583. OMAP_HSMMC_WRITE(host->base, CON, con | OD);
  584. else
  585. OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
  586. }
  587. #ifdef CONFIG_PM
  588. /*
  589. * Restore the MMC host context, if it was lost as result of a
  590. * power state change.
  591. */
  592. static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
  593. {
  594. struct mmc_ios *ios = &host->mmc->ios;
  595. u32 hctl, capa;
  596. unsigned long timeout;
  597. if (host->con == OMAP_HSMMC_READ(host->base, CON) &&
  598. host->hctl == OMAP_HSMMC_READ(host->base, HCTL) &&
  599. host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) &&
  600. host->capa == OMAP_HSMMC_READ(host->base, CAPA))
  601. return 0;
  602. host->context_loss++;
  603. if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
  604. if (host->power_mode != MMC_POWER_OFF &&
  605. (1 << ios->vdd) <= MMC_VDD_23_24)
  606. hctl = SDVS18;
  607. else
  608. hctl = SDVS30;
  609. capa = VS30 | VS18;
  610. } else {
  611. hctl = SDVS18;
  612. capa = VS18;
  613. }
  614. if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
  615. hctl |= IWE;
  616. OMAP_HSMMC_WRITE(host->base, HCTL,
  617. OMAP_HSMMC_READ(host->base, HCTL) | hctl);
  618. OMAP_HSMMC_WRITE(host->base, CAPA,
  619. OMAP_HSMMC_READ(host->base, CAPA) | capa);
  620. OMAP_HSMMC_WRITE(host->base, HCTL,
  621. OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
  622. timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
  623. while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
  624. && time_before(jiffies, timeout))
  625. ;
  626. OMAP_HSMMC_WRITE(host->base, ISE, 0);
  627. OMAP_HSMMC_WRITE(host->base, IE, 0);
  628. OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
  629. /* Do not initialize card-specific things if the power is off */
  630. if (host->power_mode == MMC_POWER_OFF)
  631. goto out;
  632. omap_hsmmc_set_bus_width(host);
  633. omap_hsmmc_set_clock(host);
  634. omap_hsmmc_set_bus_mode(host);
  635. out:
  636. dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n",
  637. host->context_loss);
  638. return 0;
  639. }
  640. /*
  641. * Save the MMC host context (store the number of power state changes so far).
  642. */
  643. static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
  644. {
  645. host->con = OMAP_HSMMC_READ(host->base, CON);
  646. host->hctl = OMAP_HSMMC_READ(host->base, HCTL);
  647. host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL);
  648. host->capa = OMAP_HSMMC_READ(host->base, CAPA);
  649. }
  650. #else
  651. static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
  652. {
  653. return 0;
  654. }
  655. static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
  656. {
  657. }
  658. #endif
  659. /*
  660. * Send init stream sequence to card
  661. * before sending IDLE command
  662. */
  663. static void send_init_stream(struct omap_hsmmc_host *host)
  664. {
  665. int reg = 0;
  666. unsigned long timeout;
  667. if (host->protect_card)
  668. return;
  669. disable_irq(host->irq);
  670. OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
  671. OMAP_HSMMC_WRITE(host->base, CON,
  672. OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
  673. OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
  674. timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
  675. while ((reg != CC_EN) && time_before(jiffies, timeout))
  676. reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN;
  677. OMAP_HSMMC_WRITE(host->base, CON,
  678. OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
  679. OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
  680. OMAP_HSMMC_READ(host->base, STAT);
  681. enable_irq(host->irq);
  682. }
  683. static inline
  684. int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
  685. {
  686. int r = 1;
  687. if (host->get_cover_state)
  688. r = host->get_cover_state(host->dev);
  689. return r;
  690. }
  691. static ssize_t
  692. omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
  693. char *buf)
  694. {
  695. struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
  696. struct omap_hsmmc_host *host = mmc_priv(mmc);
  697. return sprintf(buf, "%s\n",
  698. omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
  699. }
  700. static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
  701. static ssize_t
  702. omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
  703. char *buf)
  704. {
  705. struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
  706. struct omap_hsmmc_host *host = mmc_priv(mmc);
  707. return sprintf(buf, "%s\n", mmc_pdata(host)->name);
  708. }
  709. static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
  710. /*
  711. * Configure the response type and send the cmd.
  712. */
  713. static void
  714. omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
  715. struct mmc_data *data)
  716. {
  717. int cmdreg = 0, resptype = 0, cmdtype = 0;
  718. dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
  719. mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
  720. host->cmd = cmd;
  721. omap_hsmmc_enable_irq(host, cmd);
  722. host->response_busy = 0;
  723. if (cmd->flags & MMC_RSP_PRESENT) {
  724. if (cmd->flags & MMC_RSP_136)
  725. resptype = 1;
  726. else if (cmd->flags & MMC_RSP_BUSY) {
  727. resptype = 3;
  728. host->response_busy = 1;
  729. } else
  730. resptype = 2;
  731. }
  732. /*
  733. * Unlike OMAP1 controller, the cmdtype does not seem to be based on
  734. * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
  735. * a val of 0x3, rest 0x0.
  736. */
  737. if (cmd == host->mrq->stop)
  738. cmdtype = 0x3;
  739. cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
  740. if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) &&
  741. host->mrq->sbc) {
  742. cmdreg |= ACEN_ACMD23;
  743. OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg);
  744. }
  745. if (data) {
  746. cmdreg |= DP_SELECT | MSBS | BCE;
  747. if (data->flags & MMC_DATA_READ)
  748. cmdreg |= DDIR;
  749. else
  750. cmdreg &= ~(DDIR);
  751. }
  752. if (host->use_dma)
  753. cmdreg |= DMAE;
  754. host->req_in_progress = 1;
  755. OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
  756. OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
  757. }
  758. static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
  759. struct mmc_data *data)
  760. {
  761. return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
  762. }
  763. static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
  764. {
  765. int dma_ch;
  766. unsigned long flags;
  767. spin_lock_irqsave(&host->irq_lock, flags);
  768. host->req_in_progress = 0;
  769. dma_ch = host->dma_ch;
  770. spin_unlock_irqrestore(&host->irq_lock, flags);
  771. omap_hsmmc_disable_irq(host);
  772. /* Do not complete the request if DMA is still in progress */
  773. if (mrq->data && host->use_dma && dma_ch != -1)
  774. return;
  775. host->mrq = NULL;
  776. mmc_request_done(host->mmc, mrq);
  777. }
  778. /*
  779. * Notify the transfer complete to MMC core
  780. */
  781. static void
  782. omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
  783. {
  784. if (!data) {
  785. struct mmc_request *mrq = host->mrq;
  786. /* TC before CC from CMD6 - don't know why, but it happens */
  787. if (host->cmd && host->cmd->opcode == 6 &&
  788. host->response_busy) {
  789. host->response_busy = 0;
  790. return;
  791. }
  792. omap_hsmmc_request_done(host, mrq);
  793. return;
  794. }
  795. host->data = NULL;
  796. if (!data->error)
  797. data->bytes_xfered += data->blocks * (data->blksz);
  798. else
  799. data->bytes_xfered = 0;
  800. if (data->stop && (data->error || !host->mrq->sbc))
  801. omap_hsmmc_start_command(host, data->stop, NULL);
  802. else
  803. omap_hsmmc_request_done(host, data->mrq);
  804. }
  805. /*
  806. * Notify the core about command completion
  807. */
  808. static void
  809. omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
  810. {
  811. if (host->mrq->sbc && (host->cmd == host->mrq->sbc) &&
  812. !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) {
  813. host->cmd = NULL;
  814. omap_hsmmc_start_dma_transfer(host);
  815. omap_hsmmc_start_command(host, host->mrq->cmd,
  816. host->mrq->data);
  817. return;
  818. }
  819. host->cmd = NULL;
  820. if (cmd->flags & MMC_RSP_PRESENT) {
  821. if (cmd->flags & MMC_RSP_136) {
  822. /* response type 2 */
  823. cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
  824. cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
  825. cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
  826. cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
  827. } else {
  828. /* response types 1, 1b, 3, 4, 5, 6 */
  829. cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
  830. }
  831. }
  832. if ((host->data == NULL && !host->response_busy) || cmd->error)
  833. omap_hsmmc_request_done(host, host->mrq);
  834. }
  835. /*
  836. * DMA clean up for command errors
  837. */
  838. static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
  839. {
  840. int dma_ch;
  841. unsigned long flags;
  842. host->data->error = errno;
  843. spin_lock_irqsave(&host->irq_lock, flags);
  844. dma_ch = host->dma_ch;
  845. host->dma_ch = -1;
  846. spin_unlock_irqrestore(&host->irq_lock, flags);
  847. if (host->use_dma && dma_ch != -1) {
  848. struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
  849. dmaengine_terminate_all(chan);
  850. dma_unmap_sg(chan->device->dev,
  851. host->data->sg, host->data->sg_len,
  852. mmc_get_dma_dir(host->data));
  853. host->data->host_cookie = 0;
  854. }
  855. host->data = NULL;
  856. }
  857. /*
  858. * Readable error output
  859. */
  860. #ifdef CONFIG_MMC_DEBUG
  861. static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
  862. {
  863. /* --- means reserved bit without definition at documentation */
  864. static const char *omap_hsmmc_status_bits[] = {
  865. "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
  866. "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
  867. "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
  868. "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
  869. };
  870. char res[256];
  871. char *buf = res;
  872. int len, i;
  873. len = sprintf(buf, "MMC IRQ 0x%x :", status);
  874. buf += len;
  875. for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
  876. if (status & (1 << i)) {
  877. len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
  878. buf += len;
  879. }
  880. dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
  881. }
  882. #else
  883. static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
  884. u32 status)
  885. {
  886. }
  887. #endif /* CONFIG_MMC_DEBUG */
  888. /*
  889. * MMC controller internal state machines reset
  890. *
  891. * Used to reset command or data internal state machines, using respectively
  892. * SRC or SRD bit of SYSCTL register
  893. * Can be called from interrupt context
  894. */
  895. static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
  896. unsigned long bit)
  897. {
  898. unsigned long i = 0;
  899. unsigned long limit = MMC_TIMEOUT_US;
  900. OMAP_HSMMC_WRITE(host->base, SYSCTL,
  901. OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
  902. /*
  903. * OMAP4 ES2 and greater has an updated reset logic.
  904. * Monitor a 0->1 transition first
  905. */
  906. if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) {
  907. while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
  908. && (i++ < limit))
  909. udelay(1);
  910. }
  911. i = 0;
  912. while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
  913. (i++ < limit))
  914. udelay(1);
  915. if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
  916. dev_err(mmc_dev(host->mmc),
  917. "Timeout waiting on controller reset in %s\n",
  918. __func__);
  919. }
  920. static void hsmmc_command_incomplete(struct omap_hsmmc_host *host,
  921. int err, int end_cmd)
  922. {
  923. if (end_cmd) {
  924. omap_hsmmc_reset_controller_fsm(host, SRC);
  925. if (host->cmd)
  926. host->cmd->error = err;
  927. }
  928. if (host->data) {
  929. omap_hsmmc_reset_controller_fsm(host, SRD);
  930. omap_hsmmc_dma_cleanup(host, err);
  931. } else if (host->mrq && host->mrq->cmd)
  932. host->mrq->cmd->error = err;
  933. }
  934. static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
  935. {
  936. struct mmc_data *data;
  937. int end_cmd = 0, end_trans = 0;
  938. int error = 0;
  939. data = host->data;
  940. dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
  941. if (status & ERR_EN) {
  942. omap_hsmmc_dbg_report_irq(host, status);
  943. if (status & (CTO_EN | CCRC_EN | CEB_EN))
  944. end_cmd = 1;
  945. if (host->data || host->response_busy) {
  946. end_trans = !end_cmd;
  947. host->response_busy = 0;
  948. }
  949. if (status & (CTO_EN | DTO_EN))
  950. hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd);
  951. else if (status & (CCRC_EN | DCRC_EN | DEB_EN | CEB_EN |
  952. BADA_EN))
  953. hsmmc_command_incomplete(host, -EILSEQ, end_cmd);
  954. if (status & ACE_EN) {
  955. u32 ac12;
  956. ac12 = OMAP_HSMMC_READ(host->base, AC12);
  957. if (!(ac12 & ACNE) && host->mrq->sbc) {
  958. end_cmd = 1;
  959. if (ac12 & ACTO)
  960. error = -ETIMEDOUT;
  961. else if (ac12 & (ACCE | ACEB | ACIE))
  962. error = -EILSEQ;
  963. host->mrq->sbc->error = error;
  964. hsmmc_command_incomplete(host, error, end_cmd);
  965. }
  966. dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12);
  967. }
  968. }
  969. OMAP_HSMMC_WRITE(host->base, STAT, status);
  970. if (end_cmd || ((status & CC_EN) && host->cmd))
  971. omap_hsmmc_cmd_done(host, host->cmd);
  972. if ((end_trans || (status & TC_EN)) && host->mrq)
  973. omap_hsmmc_xfer_done(host, data);
  974. }
  975. /*
  976. * MMC controller IRQ handler
  977. */
  978. static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
  979. {
  980. struct omap_hsmmc_host *host = dev_id;
  981. int status;
  982. status = OMAP_HSMMC_READ(host->base, STAT);
  983. while (status & (INT_EN_MASK | CIRQ_EN)) {
  984. if (host->req_in_progress)
  985. omap_hsmmc_do_irq(host, status);
  986. if (status & CIRQ_EN)
  987. mmc_signal_sdio_irq(host->mmc);
  988. /* Flush posted write */
  989. status = OMAP_HSMMC_READ(host->base, STAT);
  990. }
  991. return IRQ_HANDLED;
  992. }
  993. static void set_sd_bus_power(struct omap_hsmmc_host *host)
  994. {
  995. unsigned long i;
  996. OMAP_HSMMC_WRITE(host->base, HCTL,
  997. OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
  998. for (i = 0; i < loops_per_jiffy; i++) {
  999. if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
  1000. break;
  1001. cpu_relax();
  1002. }
  1003. }
  1004. /*
  1005. * Switch MMC interface voltage ... only relevant for MMC1.
  1006. *
  1007. * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
  1008. * The MMC2 transceiver controls are used instead of DAT4..DAT7.
  1009. * Some chips, like eMMC ones, use internal transceivers.
  1010. */
  1011. static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
  1012. {
  1013. u32 reg_val = 0;
  1014. int ret;
  1015. /* Disable the clocks */
  1016. if (host->dbclk)
  1017. clk_disable_unprepare(host->dbclk);
  1018. /* Turn the power off */
  1019. ret = omap_hsmmc_set_power(host, 0);
  1020. /* Turn the power ON with given VDD 1.8 or 3.0v */
  1021. if (!ret)
  1022. ret = omap_hsmmc_set_power(host, 1);
  1023. if (host->dbclk)
  1024. clk_prepare_enable(host->dbclk);
  1025. if (ret != 0)
  1026. goto err;
  1027. OMAP_HSMMC_WRITE(host->base, HCTL,
  1028. OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
  1029. reg_val = OMAP_HSMMC_READ(host->base, HCTL);
  1030. /*
  1031. * If a MMC dual voltage card is detected, the set_ios fn calls
  1032. * this fn with VDD bit set for 1.8V. Upon card removal from the
  1033. * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
  1034. *
  1035. * Cope with a bit of slop in the range ... per data sheets:
  1036. * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
  1037. * but recommended values are 1.71V to 1.89V
  1038. * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
  1039. * but recommended values are 2.7V to 3.3V
  1040. *
  1041. * Board setup code shouldn't permit anything very out-of-range.
  1042. * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
  1043. * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
  1044. */
  1045. if ((1 << vdd) <= MMC_VDD_23_24)
  1046. reg_val |= SDVS18;
  1047. else
  1048. reg_val |= SDVS30;
  1049. OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
  1050. set_sd_bus_power(host);
  1051. return 0;
  1052. err:
  1053. dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
  1054. return ret;
  1055. }
  1056. /* Protect the card while the cover is open */
  1057. static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
  1058. {
  1059. if (!host->get_cover_state)
  1060. return;
  1061. host->reqs_blocked = 0;
  1062. if (host->get_cover_state(host->dev)) {
  1063. if (host->protect_card) {
  1064. dev_info(host->dev, "%s: cover is closed, "
  1065. "card is now accessible\n",
  1066. mmc_hostname(host->mmc));
  1067. host->protect_card = 0;
  1068. }
  1069. } else {
  1070. if (!host->protect_card) {
  1071. dev_info(host->dev, "%s: cover is open, "
  1072. "card is now inaccessible\n",
  1073. mmc_hostname(host->mmc));
  1074. host->protect_card = 1;
  1075. }
  1076. }
  1077. }
  1078. /*
  1079. * irq handler when (cell-phone) cover is mounted/removed
  1080. */
  1081. static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id)
  1082. {
  1083. struct omap_hsmmc_host *host = dev_id;
  1084. sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
  1085. omap_hsmmc_protect_card(host);
  1086. mmc_detect_change(host->mmc, (HZ * 200) / 1000);
  1087. return IRQ_HANDLED;
  1088. }
  1089. static void omap_hsmmc_dma_callback(void *param)
  1090. {
  1091. struct omap_hsmmc_host *host = param;
  1092. struct dma_chan *chan;
  1093. struct mmc_data *data;
  1094. int req_in_progress;
  1095. spin_lock_irq(&host->irq_lock);
  1096. if (host->dma_ch < 0) {
  1097. spin_unlock_irq(&host->irq_lock);
  1098. return;
  1099. }
  1100. data = host->mrq->data;
  1101. chan = omap_hsmmc_get_dma_chan(host, data);
  1102. if (!data->host_cookie)
  1103. dma_unmap_sg(chan->device->dev,
  1104. data->sg, data->sg_len,
  1105. mmc_get_dma_dir(data));
  1106. req_in_progress = host->req_in_progress;
  1107. host->dma_ch = -1;
  1108. spin_unlock_irq(&host->irq_lock);
  1109. /* If DMA has finished after TC, complete the request */
  1110. if (!req_in_progress) {
  1111. struct mmc_request *mrq = host->mrq;
  1112. host->mrq = NULL;
  1113. mmc_request_done(host->mmc, mrq);
  1114. }
  1115. }
  1116. static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
  1117. struct mmc_data *data,
  1118. struct omap_hsmmc_next *next,
  1119. struct dma_chan *chan)
  1120. {
  1121. int dma_len;
  1122. if (!next && data->host_cookie &&
  1123. data->host_cookie != host->next_data.cookie) {
  1124. dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
  1125. " host->next_data.cookie %d\n",
  1126. __func__, data->host_cookie, host->next_data.cookie);
  1127. data->host_cookie = 0;
  1128. }
  1129. /* Check if next job is already prepared */
  1130. if (next || data->host_cookie != host->next_data.cookie) {
  1131. dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
  1132. mmc_get_dma_dir(data));
  1133. } else {
  1134. dma_len = host->next_data.dma_len;
  1135. host->next_data.dma_len = 0;
  1136. }
  1137. if (dma_len == 0)
  1138. return -EINVAL;
  1139. if (next) {
  1140. next->dma_len = dma_len;
  1141. data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
  1142. } else
  1143. host->dma_len = dma_len;
  1144. return 0;
  1145. }
  1146. /*
  1147. * Routine to configure and start DMA for the MMC card
  1148. */
  1149. static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host,
  1150. struct mmc_request *req)
  1151. {
  1152. struct dma_async_tx_descriptor *tx;
  1153. int ret = 0, i;
  1154. struct mmc_data *data = req->data;
  1155. struct dma_chan *chan;
  1156. struct dma_slave_config cfg = {
  1157. .src_addr = host->mapbase + OMAP_HSMMC_DATA,
  1158. .dst_addr = host->mapbase + OMAP_HSMMC_DATA,
  1159. .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
  1160. .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
  1161. .src_maxburst = data->blksz / 4,
  1162. .dst_maxburst = data->blksz / 4,
  1163. };
  1164. /* Sanity check: all the SG entries must be aligned by block size. */
  1165. for (i = 0; i < data->sg_len; i++) {
  1166. struct scatterlist *sgl;
  1167. sgl = data->sg + i;
  1168. if (sgl->length % data->blksz)
  1169. return -EINVAL;
  1170. }
  1171. if ((data->blksz % 4) != 0)
  1172. /* REVISIT: The MMC buffer increments only when MSB is written.
  1173. * Return error for blksz which is non multiple of four.
  1174. */
  1175. return -EINVAL;
  1176. BUG_ON(host->dma_ch != -1);
  1177. chan = omap_hsmmc_get_dma_chan(host, data);
  1178. ret = dmaengine_slave_config(chan, &cfg);
  1179. if (ret)
  1180. return ret;
  1181. ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
  1182. if (ret)
  1183. return ret;
  1184. tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
  1185. data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
  1186. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  1187. if (!tx) {
  1188. dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
  1189. /* FIXME: cleanup */
  1190. return -1;
  1191. }
  1192. tx->callback = omap_hsmmc_dma_callback;
  1193. tx->callback_param = host;
  1194. /* Does not fail */
  1195. dmaengine_submit(tx);
  1196. host->dma_ch = 1;
  1197. return 0;
  1198. }
  1199. static void set_data_timeout(struct omap_hsmmc_host *host,
  1200. unsigned long long timeout_ns,
  1201. unsigned int timeout_clks)
  1202. {
  1203. unsigned long long timeout = timeout_ns;
  1204. unsigned int cycle_ns;
  1205. uint32_t reg, clkd, dto = 0;
  1206. reg = OMAP_HSMMC_READ(host->base, SYSCTL);
  1207. clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
  1208. if (clkd == 0)
  1209. clkd = 1;
  1210. cycle_ns = 1000000000 / (host->clk_rate / clkd);
  1211. do_div(timeout, cycle_ns);
  1212. timeout += timeout_clks;
  1213. if (timeout) {
  1214. while ((timeout & 0x80000000) == 0) {
  1215. dto += 1;
  1216. timeout <<= 1;
  1217. }
  1218. dto = 31 - dto;
  1219. timeout <<= 1;
  1220. if (timeout && dto)
  1221. dto += 1;
  1222. if (dto >= 13)
  1223. dto -= 13;
  1224. else
  1225. dto = 0;
  1226. if (dto > 14)
  1227. dto = 14;
  1228. }
  1229. reg &= ~DTO_MASK;
  1230. reg |= dto << DTO_SHIFT;
  1231. OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
  1232. }
  1233. static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host)
  1234. {
  1235. struct mmc_request *req = host->mrq;
  1236. struct dma_chan *chan;
  1237. if (!req->data)
  1238. return;
  1239. OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
  1240. | (req->data->blocks << 16));
  1241. set_data_timeout(host, req->data->timeout_ns,
  1242. req->data->timeout_clks);
  1243. chan = omap_hsmmc_get_dma_chan(host, req->data);
  1244. dma_async_issue_pending(chan);
  1245. }
  1246. /*
  1247. * Configure block length for MMC/SD cards and initiate the transfer.
  1248. */
  1249. static int
  1250. omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
  1251. {
  1252. int ret;
  1253. unsigned long long timeout;
  1254. host->data = req->data;
  1255. if (req->data == NULL) {
  1256. OMAP_HSMMC_WRITE(host->base, BLK, 0);
  1257. if (req->cmd->flags & MMC_RSP_BUSY) {
  1258. timeout = req->cmd->busy_timeout * NSEC_PER_MSEC;
  1259. /*
  1260. * Set an arbitrary 100ms data timeout for commands with
  1261. * busy signal and no indication of busy_timeout.
  1262. */
  1263. if (!timeout)
  1264. timeout = 100000000U;
  1265. set_data_timeout(host, timeout, 0);
  1266. }
  1267. return 0;
  1268. }
  1269. if (host->use_dma) {
  1270. ret = omap_hsmmc_setup_dma_transfer(host, req);
  1271. if (ret != 0) {
  1272. dev_err(mmc_dev(host->mmc), "MMC start dma failure\n");
  1273. return ret;
  1274. }
  1275. }
  1276. return 0;
  1277. }
  1278. static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
  1279. int err)
  1280. {
  1281. struct omap_hsmmc_host *host = mmc_priv(mmc);
  1282. struct mmc_data *data = mrq->data;
  1283. if (host->use_dma && data->host_cookie) {
  1284. struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
  1285. dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
  1286. mmc_get_dma_dir(data));
  1287. data->host_cookie = 0;
  1288. }
  1289. }
  1290. static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
  1291. {
  1292. struct omap_hsmmc_host *host = mmc_priv(mmc);
  1293. if (mrq->data->host_cookie) {
  1294. mrq->data->host_cookie = 0;
  1295. return ;
  1296. }
  1297. if (host->use_dma) {
  1298. struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
  1299. if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
  1300. &host->next_data, c))
  1301. mrq->data->host_cookie = 0;
  1302. }
  1303. }
  1304. /*
  1305. * Request function. for read/write operation
  1306. */
  1307. static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
  1308. {
  1309. struct omap_hsmmc_host *host = mmc_priv(mmc);
  1310. int err;
  1311. BUG_ON(host->req_in_progress);
  1312. BUG_ON(host->dma_ch != -1);
  1313. if (host->protect_card) {
  1314. if (host->reqs_blocked < 3) {
  1315. /*
  1316. * Ensure the controller is left in a consistent
  1317. * state by resetting the command and data state
  1318. * machines.
  1319. */
  1320. omap_hsmmc_reset_controller_fsm(host, SRD);
  1321. omap_hsmmc_reset_controller_fsm(host, SRC);
  1322. host->reqs_blocked += 1;
  1323. }
  1324. req->cmd->error = -EBADF;
  1325. if (req->data)
  1326. req->data->error = -EBADF;
  1327. req->cmd->retries = 0;
  1328. mmc_request_done(mmc, req);
  1329. return;
  1330. } else if (host->reqs_blocked)
  1331. host->reqs_blocked = 0;
  1332. WARN_ON(host->mrq != NULL);
  1333. host->mrq = req;
  1334. host->clk_rate = clk_get_rate(host->fclk);
  1335. err = omap_hsmmc_prepare_data(host, req);
  1336. if (err) {
  1337. req->cmd->error = err;
  1338. if (req->data)
  1339. req->data->error = err;
  1340. host->mrq = NULL;
  1341. mmc_request_done(mmc, req);
  1342. return;
  1343. }
  1344. if (req->sbc && !(host->flags & AUTO_CMD23)) {
  1345. omap_hsmmc_start_command(host, req->sbc, NULL);
  1346. return;
  1347. }
  1348. omap_hsmmc_start_dma_transfer(host);
  1349. omap_hsmmc_start_command(host, req->cmd, req->data);
  1350. }
  1351. /* Routine to configure clock values. Exposed API to core */
  1352. static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  1353. {
  1354. struct omap_hsmmc_host *host = mmc_priv(mmc);
  1355. int do_send_init_stream = 0;
  1356. if (ios->power_mode != host->power_mode) {
  1357. switch (ios->power_mode) {
  1358. case MMC_POWER_OFF:
  1359. omap_hsmmc_set_power(host, 0);
  1360. break;
  1361. case MMC_POWER_UP:
  1362. omap_hsmmc_set_power(host, 1);
  1363. break;
  1364. case MMC_POWER_ON:
  1365. do_send_init_stream = 1;
  1366. break;
  1367. }
  1368. host->power_mode = ios->power_mode;
  1369. }
  1370. /* FIXME: set registers based only on changes to ios */
  1371. omap_hsmmc_set_bus_width(host);
  1372. if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
  1373. /* Only MMC1 can interface at 3V without some flavor
  1374. * of external transceiver; but they all handle 1.8V.
  1375. */
  1376. if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
  1377. (ios->vdd == DUAL_VOLT_OCR_BIT)) {
  1378. /*
  1379. * The mmc_select_voltage fn of the core does
  1380. * not seem to set the power_mode to
  1381. * MMC_POWER_UP upon recalculating the voltage.
  1382. * vdd 1.8v.
  1383. */
  1384. if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
  1385. dev_dbg(mmc_dev(host->mmc),
  1386. "Switch operation failed\n");
  1387. }
  1388. }
  1389. omap_hsmmc_set_clock(host);
  1390. if (do_send_init_stream)
  1391. send_init_stream(host);
  1392. omap_hsmmc_set_bus_mode(host);
  1393. }
  1394. static int omap_hsmmc_get_cd(struct mmc_host *mmc)
  1395. {
  1396. struct omap_hsmmc_host *host = mmc_priv(mmc);
  1397. if (!host->card_detect)
  1398. return -ENOSYS;
  1399. return host->card_detect(host->dev);
  1400. }
  1401. static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
  1402. {
  1403. struct omap_hsmmc_host *host = mmc_priv(mmc);
  1404. if (mmc_pdata(host)->init_card)
  1405. mmc_pdata(host)->init_card(card);
  1406. else if (card->type == MMC_TYPE_SDIO ||
  1407. card->type == MMC_TYPE_SD_COMBO) {
  1408. struct device_node *np = mmc_dev(mmc)->of_node;
  1409. /*
  1410. * REVISIT: should be moved to sdio core and made more
  1411. * general e.g. by expanding the DT bindings of child nodes
  1412. * to provide a mechanism to provide this information:
  1413. * Documentation/devicetree/bindings/mmc/mmc-card.txt
  1414. */
  1415. np = of_get_compatible_child(np, "ti,wl1251");
  1416. if (np) {
  1417. /*
  1418. * We have TI wl1251 attached to MMC3. Pass this
  1419. * information to the SDIO core because it can't be
  1420. * probed by normal methods.
  1421. */
  1422. dev_info(host->dev, "found wl1251\n");
  1423. card->quirks |= MMC_QUIRK_NONSTD_SDIO;
  1424. card->cccr.wide_bus = 1;
  1425. card->cis.vendor = 0x104c;
  1426. card->cis.device = 0x9066;
  1427. card->cis.blksize = 512;
  1428. card->cis.max_dtr = 24000000;
  1429. card->ocr = 0x80;
  1430. of_node_put(np);
  1431. }
  1432. }
  1433. }
  1434. static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
  1435. {
  1436. struct omap_hsmmc_host *host = mmc_priv(mmc);
  1437. u32 irq_mask, con;
  1438. unsigned long flags;
  1439. spin_lock_irqsave(&host->irq_lock, flags);
  1440. con = OMAP_HSMMC_READ(host->base, CON);
  1441. irq_mask = OMAP_HSMMC_READ(host->base, ISE);
  1442. if (enable) {
  1443. host->flags |= HSMMC_SDIO_IRQ_ENABLED;
  1444. irq_mask |= CIRQ_EN;
  1445. con |= CTPL | CLKEXTFREE;
  1446. } else {
  1447. host->flags &= ~HSMMC_SDIO_IRQ_ENABLED;
  1448. irq_mask &= ~CIRQ_EN;
  1449. con &= ~(CTPL | CLKEXTFREE);
  1450. }
  1451. OMAP_HSMMC_WRITE(host->base, CON, con);
  1452. OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
  1453. /*
  1454. * if enable, piggy back detection on current request
  1455. * but always disable immediately
  1456. */
  1457. if (!host->req_in_progress || !enable)
  1458. OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
  1459. /* flush posted write */
  1460. OMAP_HSMMC_READ(host->base, IE);
  1461. spin_unlock_irqrestore(&host->irq_lock, flags);
  1462. }
  1463. static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host)
  1464. {
  1465. int ret;
  1466. /*
  1467. * For omaps with wake-up path, wakeirq will be irq from pinctrl and
  1468. * for other omaps, wakeirq will be from GPIO (dat line remuxed to
  1469. * gpio). wakeirq is needed to detect sdio irq in runtime suspend state
  1470. * with functional clock disabled.
  1471. */
  1472. if (!host->dev->of_node || !host->wake_irq)
  1473. return -ENODEV;
  1474. ret = dev_pm_set_dedicated_wake_irq(host->dev, host->wake_irq);
  1475. if (ret) {
  1476. dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n");
  1477. goto err;
  1478. }
  1479. /*
  1480. * Some omaps don't have wake-up path from deeper idle states
  1481. * and need to remux SDIO DAT1 to GPIO for wake-up from idle.
  1482. */
  1483. if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) {
  1484. struct pinctrl *p = devm_pinctrl_get(host->dev);
  1485. if (IS_ERR(p)) {
  1486. ret = PTR_ERR(p);
  1487. goto err_free_irq;
  1488. }
  1489. if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_DEFAULT))) {
  1490. dev_info(host->dev, "missing default pinctrl state\n");
  1491. devm_pinctrl_put(p);
  1492. ret = -EINVAL;
  1493. goto err_free_irq;
  1494. }
  1495. if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) {
  1496. dev_info(host->dev, "missing idle pinctrl state\n");
  1497. devm_pinctrl_put(p);
  1498. ret = -EINVAL;
  1499. goto err_free_irq;
  1500. }
  1501. devm_pinctrl_put(p);
  1502. }
  1503. OMAP_HSMMC_WRITE(host->base, HCTL,
  1504. OMAP_HSMMC_READ(host->base, HCTL) | IWE);
  1505. return 0;
  1506. err_free_irq:
  1507. dev_pm_clear_wake_irq(host->dev);
  1508. err:
  1509. dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n");
  1510. host->wake_irq = 0;
  1511. return ret;
  1512. }
  1513. static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
  1514. {
  1515. u32 hctl, capa, value;
  1516. /* Only MMC1 supports 3.0V */
  1517. if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
  1518. hctl = SDVS30;
  1519. capa = VS30 | VS18;
  1520. } else {
  1521. hctl = SDVS18;
  1522. capa = VS18;
  1523. }
  1524. value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
  1525. OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
  1526. value = OMAP_HSMMC_READ(host->base, CAPA);
  1527. OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
  1528. /* Set SD bus power bit */
  1529. set_sd_bus_power(host);
  1530. }
  1531. static int omap_hsmmc_multi_io_quirk(struct mmc_card *card,
  1532. unsigned int direction, int blk_size)
  1533. {
  1534. /* This controller can't do multiblock reads due to hw bugs */
  1535. if (direction == MMC_DATA_READ)
  1536. return 1;
  1537. return blk_size;
  1538. }
  1539. static struct mmc_host_ops omap_hsmmc_ops = {
  1540. .post_req = omap_hsmmc_post_req,
  1541. .pre_req = omap_hsmmc_pre_req,
  1542. .request = omap_hsmmc_request,
  1543. .set_ios = omap_hsmmc_set_ios,
  1544. .get_cd = omap_hsmmc_get_cd,
  1545. .get_ro = mmc_gpio_get_ro,
  1546. .init_card = omap_hsmmc_init_card,
  1547. .enable_sdio_irq = omap_hsmmc_enable_sdio_irq,
  1548. };
  1549. #ifdef CONFIG_DEBUG_FS
  1550. static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
  1551. {
  1552. struct mmc_host *mmc = s->private;
  1553. struct omap_hsmmc_host *host = mmc_priv(mmc);
  1554. seq_printf(s, "mmc%d:\n", mmc->index);
  1555. seq_printf(s, "sdio irq mode\t%s\n",
  1556. (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling");
  1557. if (mmc->caps & MMC_CAP_SDIO_IRQ) {
  1558. seq_printf(s, "sdio irq \t%s\n",
  1559. (host->flags & HSMMC_SDIO_IRQ_ENABLED) ? "enabled"
  1560. : "disabled");
  1561. }
  1562. seq_printf(s, "ctx_loss:\t%d\n", host->context_loss);
  1563. pm_runtime_get_sync(host->dev);
  1564. seq_puts(s, "\nregs:\n");
  1565. seq_printf(s, "CON:\t\t0x%08x\n",
  1566. OMAP_HSMMC_READ(host->base, CON));
  1567. seq_printf(s, "PSTATE:\t\t0x%08x\n",
  1568. OMAP_HSMMC_READ(host->base, PSTATE));
  1569. seq_printf(s, "HCTL:\t\t0x%08x\n",
  1570. OMAP_HSMMC_READ(host->base, HCTL));
  1571. seq_printf(s, "SYSCTL:\t\t0x%08x\n",
  1572. OMAP_HSMMC_READ(host->base, SYSCTL));
  1573. seq_printf(s, "IE:\t\t0x%08x\n",
  1574. OMAP_HSMMC_READ(host->base, IE));
  1575. seq_printf(s, "ISE:\t\t0x%08x\n",
  1576. OMAP_HSMMC_READ(host->base, ISE));
  1577. seq_printf(s, "CAPA:\t\t0x%08x\n",
  1578. OMAP_HSMMC_READ(host->base, CAPA));
  1579. pm_runtime_mark_last_busy(host->dev);
  1580. pm_runtime_put_autosuspend(host->dev);
  1581. return 0;
  1582. }
  1583. static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
  1584. {
  1585. return single_open(file, omap_hsmmc_regs_show, inode->i_private);
  1586. }
  1587. static const struct file_operations mmc_regs_fops = {
  1588. .open = omap_hsmmc_regs_open,
  1589. .read = seq_read,
  1590. .llseek = seq_lseek,
  1591. .release = single_release,
  1592. };
  1593. static void omap_hsmmc_debugfs(struct mmc_host *mmc)
  1594. {
  1595. if (mmc->debugfs_root)
  1596. debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
  1597. mmc, &mmc_regs_fops);
  1598. }
  1599. #else
  1600. static void omap_hsmmc_debugfs(struct mmc_host *mmc)
  1601. {
  1602. }
  1603. #endif
  1604. #ifdef CONFIG_OF
  1605. static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = {
  1606. /* See 35xx errata 2.1.1.128 in SPRZ278F */
  1607. .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
  1608. };
  1609. static const struct omap_mmc_of_data omap4_mmc_of_data = {
  1610. .reg_offset = 0x100,
  1611. };
  1612. static const struct omap_mmc_of_data am33xx_mmc_of_data = {
  1613. .reg_offset = 0x100,
  1614. .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING,
  1615. };
  1616. static const struct of_device_id omap_mmc_of_match[] = {
  1617. {
  1618. .compatible = "ti,omap2-hsmmc",
  1619. },
  1620. {
  1621. .compatible = "ti,omap3-pre-es3-hsmmc",
  1622. .data = &omap3_pre_es3_mmc_of_data,
  1623. },
  1624. {
  1625. .compatible = "ti,omap3-hsmmc",
  1626. },
  1627. {
  1628. .compatible = "ti,omap4-hsmmc",
  1629. .data = &omap4_mmc_of_data,
  1630. },
  1631. {
  1632. .compatible = "ti,am33xx-hsmmc",
  1633. .data = &am33xx_mmc_of_data,
  1634. },
  1635. {},
  1636. };
  1637. MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
  1638. static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
  1639. {
  1640. struct omap_hsmmc_platform_data *pdata, *legacy;
  1641. struct device_node *np = dev->of_node;
  1642. pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
  1643. if (!pdata)
  1644. return ERR_PTR(-ENOMEM); /* out of memory */
  1645. legacy = dev_get_platdata(dev);
  1646. if (legacy && legacy->name)
  1647. pdata->name = legacy->name;
  1648. if (of_find_property(np, "ti,dual-volt", NULL))
  1649. pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
  1650. pdata->gpio_cd = -EINVAL;
  1651. pdata->gpio_cod = -EINVAL;
  1652. pdata->gpio_wp = -EINVAL;
  1653. if (of_find_property(np, "ti,non-removable", NULL)) {
  1654. pdata->nonremovable = true;
  1655. pdata->no_regulator_off_init = true;
  1656. }
  1657. if (of_find_property(np, "ti,needs-special-reset", NULL))
  1658. pdata->features |= HSMMC_HAS_UPDATED_RESET;
  1659. if (of_find_property(np, "ti,needs-special-hs-handling", NULL))
  1660. pdata->features |= HSMMC_HAS_HSPE_SUPPORT;
  1661. return pdata;
  1662. }
  1663. #else
  1664. static inline struct omap_hsmmc_platform_data
  1665. *of_get_hsmmc_pdata(struct device *dev)
  1666. {
  1667. return ERR_PTR(-EINVAL);
  1668. }
  1669. #endif
  1670. static int omap_hsmmc_probe(struct platform_device *pdev)
  1671. {
  1672. struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data;
  1673. struct mmc_host *mmc;
  1674. struct omap_hsmmc_host *host = NULL;
  1675. struct resource *res;
  1676. int ret, irq;
  1677. const struct of_device_id *match;
  1678. const struct omap_mmc_of_data *data;
  1679. void __iomem *base;
  1680. match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
  1681. if (match) {
  1682. pdata = of_get_hsmmc_pdata(&pdev->dev);
  1683. if (IS_ERR(pdata))
  1684. return PTR_ERR(pdata);
  1685. if (match->data) {
  1686. data = match->data;
  1687. pdata->reg_offset = data->reg_offset;
  1688. pdata->controller_flags |= data->controller_flags;
  1689. }
  1690. }
  1691. if (pdata == NULL) {
  1692. dev_err(&pdev->dev, "Platform Data is missing\n");
  1693. return -ENXIO;
  1694. }
  1695. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1696. irq = platform_get_irq(pdev, 0);
  1697. if (res == NULL || irq < 0)
  1698. return -ENXIO;
  1699. base = devm_ioremap_resource(&pdev->dev, res);
  1700. if (IS_ERR(base))
  1701. return PTR_ERR(base);
  1702. mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
  1703. if (!mmc) {
  1704. ret = -ENOMEM;
  1705. goto err;
  1706. }
  1707. ret = mmc_of_parse(mmc);
  1708. if (ret)
  1709. goto err1;
  1710. host = mmc_priv(mmc);
  1711. host->mmc = mmc;
  1712. host->pdata = pdata;
  1713. host->dev = &pdev->dev;
  1714. host->use_dma = 1;
  1715. host->dma_ch = -1;
  1716. host->irq = irq;
  1717. host->mapbase = res->start + pdata->reg_offset;
  1718. host->base = base + pdata->reg_offset;
  1719. host->power_mode = MMC_POWER_OFF;
  1720. host->next_data.cookie = 1;
  1721. host->pbias_enabled = 0;
  1722. host->vqmmc_enabled = 0;
  1723. ret = omap_hsmmc_gpio_init(mmc, host, pdata);
  1724. if (ret)
  1725. goto err_gpio;
  1726. platform_set_drvdata(pdev, host);
  1727. if (pdev->dev.of_node)
  1728. host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1);
  1729. mmc->ops = &omap_hsmmc_ops;
  1730. mmc->f_min = OMAP_MMC_MIN_CLOCK;
  1731. if (pdata->max_freq > 0)
  1732. mmc->f_max = pdata->max_freq;
  1733. else if (mmc->f_max == 0)
  1734. mmc->f_max = OMAP_MMC_MAX_CLOCK;
  1735. spin_lock_init(&host->irq_lock);
  1736. host->fclk = devm_clk_get(&pdev->dev, "fck");
  1737. if (IS_ERR(host->fclk)) {
  1738. ret = PTR_ERR(host->fclk);
  1739. host->fclk = NULL;
  1740. goto err1;
  1741. }
  1742. if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
  1743. dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
  1744. omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk;
  1745. }
  1746. device_init_wakeup(&pdev->dev, true);
  1747. pm_runtime_enable(host->dev);
  1748. pm_runtime_get_sync(host->dev);
  1749. pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
  1750. pm_runtime_use_autosuspend(host->dev);
  1751. omap_hsmmc_context_save(host);
  1752. host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck");
  1753. /*
  1754. * MMC can still work without debounce clock.
  1755. */
  1756. if (IS_ERR(host->dbclk)) {
  1757. host->dbclk = NULL;
  1758. } else if (clk_prepare_enable(host->dbclk) != 0) {
  1759. dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
  1760. host->dbclk = NULL;
  1761. }
  1762. /* Set this to a value that allows allocating an entire descriptor
  1763. * list within a page (zero order allocation). */
  1764. mmc->max_segs = 64;
  1765. mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
  1766. mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
  1767. mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
  1768. mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
  1769. MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE | MMC_CAP_CMD23;
  1770. mmc->caps |= mmc_pdata(host)->caps;
  1771. if (mmc->caps & MMC_CAP_8_BIT_DATA)
  1772. mmc->caps |= MMC_CAP_4_BIT_DATA;
  1773. if (mmc_pdata(host)->nonremovable)
  1774. mmc->caps |= MMC_CAP_NONREMOVABLE;
  1775. mmc->pm_caps |= mmc_pdata(host)->pm_caps;
  1776. omap_hsmmc_conf_bus_power(host);
  1777. host->rx_chan = dma_request_chan(&pdev->dev, "rx");
  1778. if (IS_ERR(host->rx_chan)) {
  1779. dev_err(mmc_dev(host->mmc), "RX DMA channel request failed\n");
  1780. ret = PTR_ERR(host->rx_chan);
  1781. goto err_irq;
  1782. }
  1783. host->tx_chan = dma_request_chan(&pdev->dev, "tx");
  1784. if (IS_ERR(host->tx_chan)) {
  1785. dev_err(mmc_dev(host->mmc), "TX DMA channel request failed\n");
  1786. ret = PTR_ERR(host->tx_chan);
  1787. goto err_irq;
  1788. }
  1789. /*
  1790. * Limit the maximum segment size to the lower of the request size
  1791. * and the DMA engine device segment size limits. In reality, with
  1792. * 32-bit transfers, the DMA engine can do longer segments than this
  1793. * but there is no way to represent that in the DMA model - if we
  1794. * increase this figure here, we get warnings from the DMA API debug.
  1795. */
  1796. mmc->max_seg_size = min3(mmc->max_req_size,
  1797. dma_get_max_seg_size(host->rx_chan->device->dev),
  1798. dma_get_max_seg_size(host->tx_chan->device->dev));
  1799. /* Request IRQ for MMC operations */
  1800. ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0,
  1801. mmc_hostname(mmc), host);
  1802. if (ret) {
  1803. dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
  1804. goto err_irq;
  1805. }
  1806. ret = omap_hsmmc_reg_get(host);
  1807. if (ret)
  1808. goto err_irq;
  1809. if (!mmc->ocr_avail)
  1810. mmc->ocr_avail = mmc_pdata(host)->ocr_mask;
  1811. omap_hsmmc_disable_irq(host);
  1812. /*
  1813. * For now, only support SDIO interrupt if we have a separate
  1814. * wake-up interrupt configured from device tree. This is because
  1815. * the wake-up interrupt is needed for idle state and some
  1816. * platforms need special quirks. And we don't want to add new
  1817. * legacy mux platform init code callbacks any longer as we
  1818. * are moving to DT based booting anyways.
  1819. */
  1820. ret = omap_hsmmc_configure_wake_irq(host);
  1821. if (!ret)
  1822. mmc->caps |= MMC_CAP_SDIO_IRQ;
  1823. omap_hsmmc_protect_card(host);
  1824. mmc_add_host(mmc);
  1825. if (mmc_pdata(host)->name != NULL) {
  1826. ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
  1827. if (ret < 0)
  1828. goto err_slot_name;
  1829. }
  1830. if (host->get_cover_state) {
  1831. ret = device_create_file(&mmc->class_dev,
  1832. &dev_attr_cover_switch);
  1833. if (ret < 0)
  1834. goto err_slot_name;
  1835. }
  1836. omap_hsmmc_debugfs(mmc);
  1837. pm_runtime_mark_last_busy(host->dev);
  1838. pm_runtime_put_autosuspend(host->dev);
  1839. return 0;
  1840. err_slot_name:
  1841. mmc_remove_host(mmc);
  1842. err_irq:
  1843. device_init_wakeup(&pdev->dev, false);
  1844. if (!IS_ERR_OR_NULL(host->tx_chan))
  1845. dma_release_channel(host->tx_chan);
  1846. if (!IS_ERR_OR_NULL(host->rx_chan))
  1847. dma_release_channel(host->rx_chan);
  1848. pm_runtime_dont_use_autosuspend(host->dev);
  1849. pm_runtime_put_sync(host->dev);
  1850. pm_runtime_disable(host->dev);
  1851. if (host->dbclk)
  1852. clk_disable_unprepare(host->dbclk);
  1853. err1:
  1854. err_gpio:
  1855. mmc_free_host(mmc);
  1856. err:
  1857. return ret;
  1858. }
  1859. static int omap_hsmmc_remove(struct platform_device *pdev)
  1860. {
  1861. struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
  1862. pm_runtime_get_sync(host->dev);
  1863. mmc_remove_host(host->mmc);
  1864. dma_release_channel(host->tx_chan);
  1865. dma_release_channel(host->rx_chan);
  1866. dev_pm_clear_wake_irq(host->dev);
  1867. pm_runtime_dont_use_autosuspend(host->dev);
  1868. pm_runtime_put_sync(host->dev);
  1869. pm_runtime_disable(host->dev);
  1870. device_init_wakeup(&pdev->dev, false);
  1871. if (host->dbclk)
  1872. clk_disable_unprepare(host->dbclk);
  1873. mmc_free_host(host->mmc);
  1874. return 0;
  1875. }
  1876. #ifdef CONFIG_PM_SLEEP
  1877. static int omap_hsmmc_suspend(struct device *dev)
  1878. {
  1879. struct omap_hsmmc_host *host = dev_get_drvdata(dev);
  1880. if (!host)
  1881. return 0;
  1882. pm_runtime_get_sync(host->dev);
  1883. if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
  1884. OMAP_HSMMC_WRITE(host->base, ISE, 0);
  1885. OMAP_HSMMC_WRITE(host->base, IE, 0);
  1886. OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
  1887. OMAP_HSMMC_WRITE(host->base, HCTL,
  1888. OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
  1889. }
  1890. if (host->dbclk)
  1891. clk_disable_unprepare(host->dbclk);
  1892. pm_runtime_put_sync(host->dev);
  1893. return 0;
  1894. }
  1895. /* Routine to resume the MMC device */
  1896. static int omap_hsmmc_resume(struct device *dev)
  1897. {
  1898. struct omap_hsmmc_host *host = dev_get_drvdata(dev);
  1899. if (!host)
  1900. return 0;
  1901. pm_runtime_get_sync(host->dev);
  1902. if (host->dbclk)
  1903. clk_prepare_enable(host->dbclk);
  1904. if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
  1905. omap_hsmmc_conf_bus_power(host);
  1906. omap_hsmmc_protect_card(host);
  1907. pm_runtime_mark_last_busy(host->dev);
  1908. pm_runtime_put_autosuspend(host->dev);
  1909. return 0;
  1910. }
  1911. #endif
  1912. static int omap_hsmmc_runtime_suspend(struct device *dev)
  1913. {
  1914. struct omap_hsmmc_host *host;
  1915. unsigned long flags;
  1916. int ret = 0;
  1917. host = platform_get_drvdata(to_platform_device(dev));
  1918. omap_hsmmc_context_save(host);
  1919. dev_dbg(dev, "disabled\n");
  1920. spin_lock_irqsave(&host->irq_lock, flags);
  1921. if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
  1922. (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
  1923. /* disable sdio irq handling to prevent race */
  1924. OMAP_HSMMC_WRITE(host->base, ISE, 0);
  1925. OMAP_HSMMC_WRITE(host->base, IE, 0);
  1926. if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) {
  1927. /*
  1928. * dat1 line low, pending sdio irq
  1929. * race condition: possible irq handler running on
  1930. * multi-core, abort
  1931. */
  1932. dev_dbg(dev, "pending sdio irq, abort suspend\n");
  1933. OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
  1934. OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
  1935. OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
  1936. pm_runtime_mark_last_busy(dev);
  1937. ret = -EBUSY;
  1938. goto abort;
  1939. }
  1940. pinctrl_pm_select_idle_state(dev);
  1941. } else {
  1942. pinctrl_pm_select_idle_state(dev);
  1943. }
  1944. abort:
  1945. spin_unlock_irqrestore(&host->irq_lock, flags);
  1946. return ret;
  1947. }
  1948. static int omap_hsmmc_runtime_resume(struct device *dev)
  1949. {
  1950. struct omap_hsmmc_host *host;
  1951. unsigned long flags;
  1952. host = platform_get_drvdata(to_platform_device(dev));
  1953. omap_hsmmc_context_restore(host);
  1954. dev_dbg(dev, "enabled\n");
  1955. spin_lock_irqsave(&host->irq_lock, flags);
  1956. if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
  1957. (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
  1958. pinctrl_pm_select_default_state(host->dev);
  1959. /* irq lost, if pinmux incorrect */
  1960. OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
  1961. OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
  1962. OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
  1963. } else {
  1964. pinctrl_pm_select_default_state(host->dev);
  1965. }
  1966. spin_unlock_irqrestore(&host->irq_lock, flags);
  1967. return 0;
  1968. }
  1969. static const struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
  1970. SET_SYSTEM_SLEEP_PM_OPS(omap_hsmmc_suspend, omap_hsmmc_resume)
  1971. .runtime_suspend = omap_hsmmc_runtime_suspend,
  1972. .runtime_resume = omap_hsmmc_runtime_resume,
  1973. };
  1974. static struct platform_driver omap_hsmmc_driver = {
  1975. .probe = omap_hsmmc_probe,
  1976. .remove = omap_hsmmc_remove,
  1977. .driver = {
  1978. .name = DRIVER_NAME,
  1979. .pm = &omap_hsmmc_dev_pm_ops,
  1980. .of_match_table = of_match_ptr(omap_mmc_of_match),
  1981. },
  1982. };
  1983. module_platform_driver(omap_hsmmc_driver);
  1984. MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
  1985. MODULE_LICENSE("GPL");
  1986. MODULE_ALIAS("platform:" DRIVER_NAME);
  1987. MODULE_AUTHOR("Texas Instruments Inc");