pxamci.c 19 KB

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  1. /*
  2. * linux/drivers/mmc/host/pxa.c - PXA MMCI driver
  3. *
  4. * Copyright (C) 2003 Russell King, All Rights Reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * This hardware is really sick:
  11. * - No way to clear interrupts.
  12. * - Have to turn off the clock whenever we touch the device.
  13. * - Doesn't tell you how many data blocks were transferred.
  14. * Yuck!
  15. *
  16. * 1 and 3 byte data transfers not supported
  17. * max block length up to 1023
  18. */
  19. #include <linux/module.h>
  20. #include <linux/init.h>
  21. #include <linux/ioport.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/delay.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/dmaengine.h>
  26. #include <linux/dma-mapping.h>
  27. #include <linux/clk.h>
  28. #include <linux/err.h>
  29. #include <linux/mmc/host.h>
  30. #include <linux/mmc/slot-gpio.h>
  31. #include <linux/io.h>
  32. #include <linux/regulator/consumer.h>
  33. #include <linux/gpio.h>
  34. #include <linux/gfp.h>
  35. #include <linux/of.h>
  36. #include <linux/of_gpio.h>
  37. #include <linux/of_device.h>
  38. #include <asm/sizes.h>
  39. #include <mach/hardware.h>
  40. #include <linux/platform_data/mmc-pxamci.h>
  41. #include "pxamci.h"
  42. #define DRIVER_NAME "pxa2xx-mci"
  43. #define NR_SG 1
  44. #define CLKRT_OFF (~0)
  45. #define mmc_has_26MHz() (cpu_is_pxa300() || cpu_is_pxa310() \
  46. || cpu_is_pxa935())
  47. struct pxamci_host {
  48. struct mmc_host *mmc;
  49. spinlock_t lock;
  50. struct resource *res;
  51. void __iomem *base;
  52. struct clk *clk;
  53. unsigned long clkrate;
  54. unsigned int clkrt;
  55. unsigned int cmdat;
  56. unsigned int imask;
  57. unsigned int power_mode;
  58. unsigned long detect_delay_ms;
  59. struct pxamci_platform_data *pdata;
  60. struct mmc_request *mrq;
  61. struct mmc_command *cmd;
  62. struct mmc_data *data;
  63. struct dma_chan *dma_chan_rx;
  64. struct dma_chan *dma_chan_tx;
  65. dma_cookie_t dma_cookie;
  66. unsigned int dma_len;
  67. unsigned int dma_dir;
  68. };
  69. static int pxamci_init_ocr(struct pxamci_host *host)
  70. {
  71. struct mmc_host *mmc = host->mmc;
  72. int ret;
  73. ret = mmc_regulator_get_supply(mmc);
  74. if (ret < 0)
  75. return ret;
  76. if (IS_ERR(mmc->supply.vmmc)) {
  77. /* fall-back to platform data */
  78. mmc->ocr_avail = host->pdata ?
  79. host->pdata->ocr_mask :
  80. MMC_VDD_32_33 | MMC_VDD_33_34;
  81. }
  82. return 0;
  83. }
  84. static inline int pxamci_set_power(struct pxamci_host *host,
  85. unsigned char power_mode,
  86. unsigned int vdd)
  87. {
  88. struct mmc_host *mmc = host->mmc;
  89. struct regulator *supply = mmc->supply.vmmc;
  90. int on;
  91. if (!IS_ERR(supply))
  92. return mmc_regulator_set_ocr(mmc, supply, vdd);
  93. if (host->pdata &&
  94. gpio_is_valid(host->pdata->gpio_power)) {
  95. on = ((1 << vdd) & host->pdata->ocr_mask);
  96. gpio_set_value(host->pdata->gpio_power,
  97. !!on ^ host->pdata->gpio_power_invert);
  98. }
  99. if (host->pdata && host->pdata->setpower)
  100. return host->pdata->setpower(mmc_dev(host->mmc), vdd);
  101. return 0;
  102. }
  103. static void pxamci_stop_clock(struct pxamci_host *host)
  104. {
  105. if (readl(host->base + MMC_STAT) & STAT_CLK_EN) {
  106. unsigned long timeout = 10000;
  107. unsigned int v;
  108. writel(STOP_CLOCK, host->base + MMC_STRPCL);
  109. do {
  110. v = readl(host->base + MMC_STAT);
  111. if (!(v & STAT_CLK_EN))
  112. break;
  113. udelay(1);
  114. } while (timeout--);
  115. if (v & STAT_CLK_EN)
  116. dev_err(mmc_dev(host->mmc), "unable to stop clock\n");
  117. }
  118. }
  119. static void pxamci_enable_irq(struct pxamci_host *host, unsigned int mask)
  120. {
  121. unsigned long flags;
  122. spin_lock_irqsave(&host->lock, flags);
  123. host->imask &= ~mask;
  124. writel(host->imask, host->base + MMC_I_MASK);
  125. spin_unlock_irqrestore(&host->lock, flags);
  126. }
  127. static void pxamci_disable_irq(struct pxamci_host *host, unsigned int mask)
  128. {
  129. unsigned long flags;
  130. spin_lock_irqsave(&host->lock, flags);
  131. host->imask |= mask;
  132. writel(host->imask, host->base + MMC_I_MASK);
  133. spin_unlock_irqrestore(&host->lock, flags);
  134. }
  135. static void pxamci_dma_irq(void *param);
  136. static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data)
  137. {
  138. struct dma_async_tx_descriptor *tx;
  139. enum dma_transfer_direction direction;
  140. struct dma_slave_config config;
  141. struct dma_chan *chan;
  142. unsigned int nob = data->blocks;
  143. unsigned long long clks;
  144. unsigned int timeout;
  145. int ret;
  146. host->data = data;
  147. writel(nob, host->base + MMC_NOB);
  148. writel(data->blksz, host->base + MMC_BLKLEN);
  149. clks = (unsigned long long)data->timeout_ns * host->clkrate;
  150. do_div(clks, 1000000000UL);
  151. timeout = (unsigned int)clks + (data->timeout_clks << host->clkrt);
  152. writel((timeout + 255) / 256, host->base + MMC_RDTO);
  153. memset(&config, 0, sizeof(config));
  154. config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
  155. config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
  156. config.src_addr = host->res->start + MMC_RXFIFO;
  157. config.dst_addr = host->res->start + MMC_TXFIFO;
  158. config.src_maxburst = 32;
  159. config.dst_maxburst = 32;
  160. if (data->flags & MMC_DATA_READ) {
  161. host->dma_dir = DMA_FROM_DEVICE;
  162. direction = DMA_DEV_TO_MEM;
  163. chan = host->dma_chan_rx;
  164. } else {
  165. host->dma_dir = DMA_TO_DEVICE;
  166. direction = DMA_MEM_TO_DEV;
  167. chan = host->dma_chan_tx;
  168. }
  169. config.direction = direction;
  170. ret = dmaengine_slave_config(chan, &config);
  171. if (ret < 0) {
  172. dev_err(mmc_dev(host->mmc), "dma slave config failed\n");
  173. return;
  174. }
  175. host->dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
  176. host->dma_dir);
  177. tx = dmaengine_prep_slave_sg(chan, data->sg, host->dma_len, direction,
  178. DMA_PREP_INTERRUPT);
  179. if (!tx) {
  180. dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
  181. return;
  182. }
  183. if (!(data->flags & MMC_DATA_READ)) {
  184. tx->callback = pxamci_dma_irq;
  185. tx->callback_param = host;
  186. }
  187. host->dma_cookie = dmaengine_submit(tx);
  188. /*
  189. * workaround for erratum #91:
  190. * only start DMA now if we are doing a read,
  191. * otherwise we wait until CMD/RESP has finished
  192. * before starting DMA.
  193. */
  194. if (!cpu_is_pxa27x() || data->flags & MMC_DATA_READ)
  195. dma_async_issue_pending(chan);
  196. }
  197. static void pxamci_start_cmd(struct pxamci_host *host, struct mmc_command *cmd, unsigned int cmdat)
  198. {
  199. WARN_ON(host->cmd != NULL);
  200. host->cmd = cmd;
  201. if (cmd->flags & MMC_RSP_BUSY)
  202. cmdat |= CMDAT_BUSY;
  203. #define RSP_TYPE(x) ((x) & ~(MMC_RSP_BUSY|MMC_RSP_OPCODE))
  204. switch (RSP_TYPE(mmc_resp_type(cmd))) {
  205. case RSP_TYPE(MMC_RSP_R1): /* r1, r1b, r6, r7 */
  206. cmdat |= CMDAT_RESP_SHORT;
  207. break;
  208. case RSP_TYPE(MMC_RSP_R3):
  209. cmdat |= CMDAT_RESP_R3;
  210. break;
  211. case RSP_TYPE(MMC_RSP_R2):
  212. cmdat |= CMDAT_RESP_R2;
  213. break;
  214. default:
  215. break;
  216. }
  217. writel(cmd->opcode, host->base + MMC_CMD);
  218. writel(cmd->arg >> 16, host->base + MMC_ARGH);
  219. writel(cmd->arg & 0xffff, host->base + MMC_ARGL);
  220. writel(cmdat, host->base + MMC_CMDAT);
  221. writel(host->clkrt, host->base + MMC_CLKRT);
  222. writel(START_CLOCK, host->base + MMC_STRPCL);
  223. pxamci_enable_irq(host, END_CMD_RES);
  224. }
  225. static void pxamci_finish_request(struct pxamci_host *host, struct mmc_request *mrq)
  226. {
  227. host->mrq = NULL;
  228. host->cmd = NULL;
  229. host->data = NULL;
  230. mmc_request_done(host->mmc, mrq);
  231. }
  232. static int pxamci_cmd_done(struct pxamci_host *host, unsigned int stat)
  233. {
  234. struct mmc_command *cmd = host->cmd;
  235. int i;
  236. u32 v;
  237. if (!cmd)
  238. return 0;
  239. host->cmd = NULL;
  240. /*
  241. * Did I mention this is Sick. We always need to
  242. * discard the upper 8 bits of the first 16-bit word.
  243. */
  244. v = readl(host->base + MMC_RES) & 0xffff;
  245. for (i = 0; i < 4; i++) {
  246. u32 w1 = readl(host->base + MMC_RES) & 0xffff;
  247. u32 w2 = readl(host->base + MMC_RES) & 0xffff;
  248. cmd->resp[i] = v << 24 | w1 << 8 | w2 >> 8;
  249. v = w2;
  250. }
  251. if (stat & STAT_TIME_OUT_RESPONSE) {
  252. cmd->error = -ETIMEDOUT;
  253. } else if (stat & STAT_RES_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
  254. /*
  255. * workaround for erratum #42:
  256. * Intel PXA27x Family Processor Specification Update Rev 001
  257. * A bogus CRC error can appear if the msb of a 136 bit
  258. * response is a one.
  259. */
  260. if (cpu_is_pxa27x() &&
  261. (cmd->flags & MMC_RSP_136 && cmd->resp[0] & 0x80000000))
  262. pr_debug("ignoring CRC from command %d - *risky*\n", cmd->opcode);
  263. else
  264. cmd->error = -EILSEQ;
  265. }
  266. pxamci_disable_irq(host, END_CMD_RES);
  267. if (host->data && !cmd->error) {
  268. pxamci_enable_irq(host, DATA_TRAN_DONE);
  269. /*
  270. * workaround for erratum #91, if doing write
  271. * enable DMA late
  272. */
  273. if (cpu_is_pxa27x() && host->data->flags & MMC_DATA_WRITE)
  274. dma_async_issue_pending(host->dma_chan_tx);
  275. } else {
  276. pxamci_finish_request(host, host->mrq);
  277. }
  278. return 1;
  279. }
  280. static int pxamci_data_done(struct pxamci_host *host, unsigned int stat)
  281. {
  282. struct mmc_data *data = host->data;
  283. struct dma_chan *chan;
  284. if (!data)
  285. return 0;
  286. if (data->flags & MMC_DATA_READ)
  287. chan = host->dma_chan_rx;
  288. else
  289. chan = host->dma_chan_tx;
  290. dma_unmap_sg(chan->device->dev,
  291. data->sg, data->sg_len, host->dma_dir);
  292. if (stat & STAT_READ_TIME_OUT)
  293. data->error = -ETIMEDOUT;
  294. else if (stat & (STAT_CRC_READ_ERROR|STAT_CRC_WRITE_ERROR))
  295. data->error = -EILSEQ;
  296. /*
  297. * There appears to be a hardware design bug here. There seems to
  298. * be no way to find out how much data was transferred to the card.
  299. * This means that if there was an error on any block, we mark all
  300. * data blocks as being in error.
  301. */
  302. if (!data->error)
  303. data->bytes_xfered = data->blocks * data->blksz;
  304. else
  305. data->bytes_xfered = 0;
  306. pxamci_disable_irq(host, DATA_TRAN_DONE);
  307. host->data = NULL;
  308. if (host->mrq->stop) {
  309. pxamci_stop_clock(host);
  310. pxamci_start_cmd(host, host->mrq->stop, host->cmdat);
  311. } else {
  312. pxamci_finish_request(host, host->mrq);
  313. }
  314. return 1;
  315. }
  316. static irqreturn_t pxamci_irq(int irq, void *devid)
  317. {
  318. struct pxamci_host *host = devid;
  319. unsigned int ireg;
  320. int handled = 0;
  321. ireg = readl(host->base + MMC_I_REG) & ~readl(host->base + MMC_I_MASK);
  322. if (ireg) {
  323. unsigned stat = readl(host->base + MMC_STAT);
  324. pr_debug("PXAMCI: irq %08x stat %08x\n", ireg, stat);
  325. if (ireg & END_CMD_RES)
  326. handled |= pxamci_cmd_done(host, stat);
  327. if (ireg & DATA_TRAN_DONE)
  328. handled |= pxamci_data_done(host, stat);
  329. if (ireg & SDIO_INT) {
  330. mmc_signal_sdio_irq(host->mmc);
  331. handled = 1;
  332. }
  333. }
  334. return IRQ_RETVAL(handled);
  335. }
  336. static void pxamci_request(struct mmc_host *mmc, struct mmc_request *mrq)
  337. {
  338. struct pxamci_host *host = mmc_priv(mmc);
  339. unsigned int cmdat;
  340. WARN_ON(host->mrq != NULL);
  341. host->mrq = mrq;
  342. pxamci_stop_clock(host);
  343. cmdat = host->cmdat;
  344. host->cmdat &= ~CMDAT_INIT;
  345. if (mrq->data) {
  346. pxamci_setup_data(host, mrq->data);
  347. cmdat &= ~CMDAT_BUSY;
  348. cmdat |= CMDAT_DATAEN | CMDAT_DMAEN;
  349. if (mrq->data->flags & MMC_DATA_WRITE)
  350. cmdat |= CMDAT_WRITE;
  351. }
  352. pxamci_start_cmd(host, mrq->cmd, cmdat);
  353. }
  354. static int pxamci_get_ro(struct mmc_host *mmc)
  355. {
  356. struct pxamci_host *host = mmc_priv(mmc);
  357. if (host->pdata && gpio_is_valid(host->pdata->gpio_card_ro))
  358. return mmc_gpio_get_ro(mmc);
  359. if (host->pdata && host->pdata->get_ro)
  360. return !!host->pdata->get_ro(mmc_dev(mmc));
  361. /*
  362. * Board doesn't support read only detection; let the mmc core
  363. * decide what to do.
  364. */
  365. return -ENOSYS;
  366. }
  367. static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  368. {
  369. struct pxamci_host *host = mmc_priv(mmc);
  370. if (ios->clock) {
  371. unsigned long rate = host->clkrate;
  372. unsigned int clk = rate / ios->clock;
  373. if (host->clkrt == CLKRT_OFF)
  374. clk_prepare_enable(host->clk);
  375. if (ios->clock == 26000000) {
  376. /* to support 26MHz */
  377. host->clkrt = 7;
  378. } else {
  379. /* to handle (19.5MHz, 26MHz) */
  380. if (!clk)
  381. clk = 1;
  382. /*
  383. * clk might result in a lower divisor than we
  384. * desire. check for that condition and adjust
  385. * as appropriate.
  386. */
  387. if (rate / clk > ios->clock)
  388. clk <<= 1;
  389. host->clkrt = fls(clk) - 1;
  390. }
  391. /*
  392. * we write clkrt on the next command
  393. */
  394. } else {
  395. pxamci_stop_clock(host);
  396. if (host->clkrt != CLKRT_OFF) {
  397. host->clkrt = CLKRT_OFF;
  398. clk_disable_unprepare(host->clk);
  399. }
  400. }
  401. if (host->power_mode != ios->power_mode) {
  402. int ret;
  403. host->power_mode = ios->power_mode;
  404. ret = pxamci_set_power(host, ios->power_mode, ios->vdd);
  405. if (ret) {
  406. dev_err(mmc_dev(mmc), "unable to set power\n");
  407. /*
  408. * The .set_ios() function in the mmc_host_ops
  409. * struct return void, and failing to set the
  410. * power should be rare so we print an error and
  411. * return here.
  412. */
  413. return;
  414. }
  415. if (ios->power_mode == MMC_POWER_ON)
  416. host->cmdat |= CMDAT_INIT;
  417. }
  418. if (ios->bus_width == MMC_BUS_WIDTH_4)
  419. host->cmdat |= CMDAT_SD_4DAT;
  420. else
  421. host->cmdat &= ~CMDAT_SD_4DAT;
  422. dev_dbg(mmc_dev(mmc), "PXAMCI: clkrt = %x cmdat = %x\n",
  423. host->clkrt, host->cmdat);
  424. }
  425. static void pxamci_enable_sdio_irq(struct mmc_host *host, int enable)
  426. {
  427. struct pxamci_host *pxa_host = mmc_priv(host);
  428. if (enable)
  429. pxamci_enable_irq(pxa_host, SDIO_INT);
  430. else
  431. pxamci_disable_irq(pxa_host, SDIO_INT);
  432. }
  433. static const struct mmc_host_ops pxamci_ops = {
  434. .request = pxamci_request,
  435. .get_cd = mmc_gpio_get_cd,
  436. .get_ro = pxamci_get_ro,
  437. .set_ios = pxamci_set_ios,
  438. .enable_sdio_irq = pxamci_enable_sdio_irq,
  439. };
  440. static void pxamci_dma_irq(void *param)
  441. {
  442. struct pxamci_host *host = param;
  443. struct dma_tx_state state;
  444. enum dma_status status;
  445. struct dma_chan *chan;
  446. unsigned long flags;
  447. spin_lock_irqsave(&host->lock, flags);
  448. if (!host->data)
  449. goto out_unlock;
  450. if (host->data->flags & MMC_DATA_READ)
  451. chan = host->dma_chan_rx;
  452. else
  453. chan = host->dma_chan_tx;
  454. status = dmaengine_tx_status(chan, host->dma_cookie, &state);
  455. if (likely(status == DMA_COMPLETE)) {
  456. writel(BUF_PART_FULL, host->base + MMC_PRTBUF);
  457. } else {
  458. pr_err("%s: DMA error on %s channel\n", mmc_hostname(host->mmc),
  459. host->data->flags & MMC_DATA_READ ? "rx" : "tx");
  460. host->data->error = -EIO;
  461. pxamci_data_done(host, 0);
  462. }
  463. out_unlock:
  464. spin_unlock_irqrestore(&host->lock, flags);
  465. }
  466. static irqreturn_t pxamci_detect_irq(int irq, void *devid)
  467. {
  468. struct pxamci_host *host = mmc_priv(devid);
  469. mmc_detect_change(devid, msecs_to_jiffies(host->detect_delay_ms));
  470. return IRQ_HANDLED;
  471. }
  472. #ifdef CONFIG_OF
  473. static const struct of_device_id pxa_mmc_dt_ids[] = {
  474. { .compatible = "marvell,pxa-mmc" },
  475. { }
  476. };
  477. MODULE_DEVICE_TABLE(of, pxa_mmc_dt_ids);
  478. static int pxamci_of_init(struct platform_device *pdev,
  479. struct mmc_host *mmc)
  480. {
  481. struct device_node *np = pdev->dev.of_node;
  482. struct pxamci_host *host = mmc_priv(mmc);
  483. u32 tmp;
  484. int ret;
  485. if (!np)
  486. return 0;
  487. /* pxa-mmc specific */
  488. if (of_property_read_u32(np, "pxa-mmc,detect-delay-ms", &tmp) == 0)
  489. host->detect_delay_ms = tmp;
  490. ret = mmc_of_parse(mmc);
  491. if (ret < 0)
  492. return ret;
  493. return 0;
  494. }
  495. #else
  496. static int pxamci_of_init(struct platform_device *pdev,
  497. struct mmc_host *mmc)
  498. {
  499. return 0;
  500. }
  501. #endif
  502. static int pxamci_probe(struct platform_device *pdev)
  503. {
  504. struct mmc_host *mmc;
  505. struct pxamci_host *host = NULL;
  506. struct device *dev = &pdev->dev;
  507. struct resource *r;
  508. int ret, irq;
  509. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  510. irq = platform_get_irq(pdev, 0);
  511. if (irq < 0)
  512. return irq;
  513. mmc = mmc_alloc_host(sizeof(struct pxamci_host), dev);
  514. if (!mmc) {
  515. ret = -ENOMEM;
  516. goto out;
  517. }
  518. mmc->ops = &pxamci_ops;
  519. /*
  520. * We can do SG-DMA, but we don't because we never know how much
  521. * data we successfully wrote to the card.
  522. */
  523. mmc->max_segs = NR_SG;
  524. /*
  525. * Our hardware DMA can handle a maximum of one page per SG entry.
  526. */
  527. mmc->max_seg_size = PAGE_SIZE;
  528. /*
  529. * Block length register is only 10 bits before PXA27x.
  530. */
  531. mmc->max_blk_size = cpu_is_pxa25x() ? 1023 : 2048;
  532. /*
  533. * Block count register is 16 bits.
  534. */
  535. mmc->max_blk_count = 65535;
  536. ret = pxamci_of_init(pdev, mmc);
  537. if (ret)
  538. return ret;
  539. host = mmc_priv(mmc);
  540. host->mmc = mmc;
  541. host->pdata = pdev->dev.platform_data;
  542. host->clkrt = CLKRT_OFF;
  543. host->clk = devm_clk_get(dev, NULL);
  544. if (IS_ERR(host->clk)) {
  545. ret = PTR_ERR(host->clk);
  546. host->clk = NULL;
  547. goto out;
  548. }
  549. host->clkrate = clk_get_rate(host->clk);
  550. /*
  551. * Calculate minimum clock rate, rounding up.
  552. */
  553. mmc->f_min = (host->clkrate + 63) / 64;
  554. mmc->f_max = (mmc_has_26MHz()) ? 26000000 : host->clkrate;
  555. ret = pxamci_init_ocr(host);
  556. if (ret < 0)
  557. return ret;
  558. mmc->caps = 0;
  559. host->cmdat = 0;
  560. if (!cpu_is_pxa25x()) {
  561. mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
  562. host->cmdat |= CMDAT_SDIO_INT_EN;
  563. if (mmc_has_26MHz())
  564. mmc->caps |= MMC_CAP_MMC_HIGHSPEED |
  565. MMC_CAP_SD_HIGHSPEED;
  566. }
  567. spin_lock_init(&host->lock);
  568. host->res = r;
  569. host->imask = MMC_I_MASK_ALL;
  570. host->base = devm_ioremap_resource(dev, r);
  571. if (IS_ERR(host->base)) {
  572. ret = PTR_ERR(host->base);
  573. goto out;
  574. }
  575. /*
  576. * Ensure that the host controller is shut down, and setup
  577. * with our defaults.
  578. */
  579. pxamci_stop_clock(host);
  580. writel(0, host->base + MMC_SPI);
  581. writel(64, host->base + MMC_RESTO);
  582. writel(host->imask, host->base + MMC_I_MASK);
  583. ret = devm_request_irq(dev, irq, pxamci_irq, 0,
  584. DRIVER_NAME, host);
  585. if (ret)
  586. goto out;
  587. platform_set_drvdata(pdev, mmc);
  588. host->dma_chan_rx = dma_request_slave_channel(dev, "rx");
  589. if (host->dma_chan_rx == NULL) {
  590. dev_err(dev, "unable to request rx dma channel\n");
  591. ret = -ENODEV;
  592. goto out;
  593. }
  594. host->dma_chan_tx = dma_request_slave_channel(dev, "tx");
  595. if (host->dma_chan_tx == NULL) {
  596. dev_err(dev, "unable to request tx dma channel\n");
  597. ret = -ENODEV;
  598. goto out;
  599. }
  600. if (host->pdata) {
  601. int gpio_cd = host->pdata->gpio_card_detect;
  602. int gpio_ro = host->pdata->gpio_card_ro;
  603. int gpio_power = host->pdata->gpio_power;
  604. host->detect_delay_ms = host->pdata->detect_delay_ms;
  605. if (gpio_is_valid(gpio_power)) {
  606. ret = devm_gpio_request(dev, gpio_power,
  607. "mmc card power");
  608. if (ret) {
  609. dev_err(dev,
  610. "Failed requesting gpio_power %d\n",
  611. gpio_power);
  612. goto out;
  613. }
  614. gpio_direction_output(gpio_power,
  615. host->pdata->gpio_power_invert);
  616. }
  617. if (gpio_is_valid(gpio_ro)) {
  618. ret = mmc_gpio_request_ro(mmc, gpio_ro);
  619. if (ret) {
  620. dev_err(dev,
  621. "Failed requesting gpio_ro %d\n",
  622. gpio_ro);
  623. goto out;
  624. } else {
  625. mmc->caps2 |= host->pdata->gpio_card_ro_invert ?
  626. 0 : MMC_CAP2_RO_ACTIVE_HIGH;
  627. }
  628. }
  629. if (gpio_is_valid(gpio_cd))
  630. ret = mmc_gpio_request_cd(mmc, gpio_cd, 0);
  631. if (ret) {
  632. dev_err(dev, "Failed requesting gpio_cd %d\n",
  633. gpio_cd);
  634. goto out;
  635. }
  636. if (host->pdata->init)
  637. host->pdata->init(dev, pxamci_detect_irq, mmc);
  638. if (gpio_is_valid(gpio_power) && host->pdata->setpower)
  639. dev_warn(dev, "gpio_power and setpower() both defined\n");
  640. if (gpio_is_valid(gpio_ro) && host->pdata->get_ro)
  641. dev_warn(dev, "gpio_ro and get_ro() both defined\n");
  642. }
  643. mmc_add_host(mmc);
  644. return 0;
  645. out:
  646. if (host) {
  647. if (host->dma_chan_rx)
  648. dma_release_channel(host->dma_chan_rx);
  649. if (host->dma_chan_tx)
  650. dma_release_channel(host->dma_chan_tx);
  651. }
  652. if (mmc)
  653. mmc_free_host(mmc);
  654. return ret;
  655. }
  656. static int pxamci_remove(struct platform_device *pdev)
  657. {
  658. struct mmc_host *mmc = platform_get_drvdata(pdev);
  659. if (mmc) {
  660. struct pxamci_host *host = mmc_priv(mmc);
  661. mmc_remove_host(mmc);
  662. if (host->pdata && host->pdata->exit)
  663. host->pdata->exit(&pdev->dev, mmc);
  664. pxamci_stop_clock(host);
  665. writel(TXFIFO_WR_REQ|RXFIFO_RD_REQ|CLK_IS_OFF|STOP_CMD|
  666. END_CMD_RES|PRG_DONE|DATA_TRAN_DONE,
  667. host->base + MMC_I_MASK);
  668. dmaengine_terminate_all(host->dma_chan_rx);
  669. dmaengine_terminate_all(host->dma_chan_tx);
  670. dma_release_channel(host->dma_chan_rx);
  671. dma_release_channel(host->dma_chan_tx);
  672. mmc_free_host(mmc);
  673. }
  674. return 0;
  675. }
  676. static struct platform_driver pxamci_driver = {
  677. .probe = pxamci_probe,
  678. .remove = pxamci_remove,
  679. .driver = {
  680. .name = DRIVER_NAME,
  681. .of_match_table = of_match_ptr(pxa_mmc_dt_ids),
  682. },
  683. };
  684. module_platform_driver(pxamci_driver);
  685. MODULE_DESCRIPTION("PXA Multimedia Card Interface Driver");
  686. MODULE_LICENSE("GPL");
  687. MODULE_ALIAS("platform:pxa2xx-mci");