sdhci-acpi.c 23 KB

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  1. /*
  2. * Secure Digital Host Controller Interface ACPI driver.
  3. *
  4. * Copyright (c) 2012, Intel Corporation.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms and conditions of the GNU General Public License,
  8. * version 2, as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program; if not, write to the Free Software Foundation, Inc.,
  17. * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18. *
  19. */
  20. #include <linux/init.h>
  21. #include <linux/export.h>
  22. #include <linux/module.h>
  23. #include <linux/device.h>
  24. #include <linux/platform_device.h>
  25. #include <linux/ioport.h>
  26. #include <linux/io.h>
  27. #include <linux/dma-mapping.h>
  28. #include <linux/compiler.h>
  29. #include <linux/stddef.h>
  30. #include <linux/bitops.h>
  31. #include <linux/types.h>
  32. #include <linux/err.h>
  33. #include <linux/interrupt.h>
  34. #include <linux/acpi.h>
  35. #include <linux/pm.h>
  36. #include <linux/pm_runtime.h>
  37. #include <linux/delay.h>
  38. #include <linux/mmc/host.h>
  39. #include <linux/mmc/pm.h>
  40. #include <linux/mmc/slot-gpio.h>
  41. #ifdef CONFIG_X86
  42. #include <asm/cpu_device_id.h>
  43. #include <asm/intel-family.h>
  44. #include <asm/iosf_mbi.h>
  45. #include <linux/pci.h>
  46. #endif
  47. #include "sdhci.h"
  48. enum {
  49. SDHCI_ACPI_SD_CD = BIT(0),
  50. SDHCI_ACPI_RUNTIME_PM = BIT(1),
  51. SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL = BIT(2),
  52. };
  53. struct sdhci_acpi_chip {
  54. const struct sdhci_ops *ops;
  55. unsigned int quirks;
  56. unsigned int quirks2;
  57. unsigned long caps;
  58. unsigned int caps2;
  59. mmc_pm_flag_t pm_caps;
  60. };
  61. struct sdhci_acpi_slot {
  62. const struct sdhci_acpi_chip *chip;
  63. unsigned int quirks;
  64. unsigned int quirks2;
  65. unsigned long caps;
  66. unsigned int caps2;
  67. mmc_pm_flag_t pm_caps;
  68. unsigned int flags;
  69. size_t priv_size;
  70. int (*probe_slot)(struct platform_device *, const char *, const char *);
  71. int (*remove_slot)(struct platform_device *);
  72. int (*free_slot)(struct platform_device *pdev);
  73. int (*setup_host)(struct platform_device *pdev);
  74. };
  75. struct sdhci_acpi_host {
  76. struct sdhci_host *host;
  77. const struct sdhci_acpi_slot *slot;
  78. struct platform_device *pdev;
  79. bool use_runtime_pm;
  80. unsigned long private[0] ____cacheline_aligned;
  81. };
  82. static inline void *sdhci_acpi_priv(struct sdhci_acpi_host *c)
  83. {
  84. return (void *)c->private;
  85. }
  86. static inline bool sdhci_acpi_flag(struct sdhci_acpi_host *c, unsigned int flag)
  87. {
  88. return c->slot && (c->slot->flags & flag);
  89. }
  90. #define INTEL_DSM_HS_CAPS_SDR25 BIT(0)
  91. #define INTEL_DSM_HS_CAPS_DDR50 BIT(1)
  92. #define INTEL_DSM_HS_CAPS_SDR50 BIT(2)
  93. #define INTEL_DSM_HS_CAPS_SDR104 BIT(3)
  94. enum {
  95. INTEL_DSM_FNS = 0,
  96. INTEL_DSM_V18_SWITCH = 3,
  97. INTEL_DSM_V33_SWITCH = 4,
  98. INTEL_DSM_HS_CAPS = 8,
  99. };
  100. struct intel_host {
  101. u32 dsm_fns;
  102. u32 hs_caps;
  103. };
  104. static const guid_t intel_dsm_guid =
  105. GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F,
  106. 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61);
  107. static int __intel_dsm(struct intel_host *intel_host, struct device *dev,
  108. unsigned int fn, u32 *result)
  109. {
  110. union acpi_object *obj;
  111. int err = 0;
  112. obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL);
  113. if (!obj)
  114. return -EOPNOTSUPP;
  115. if (obj->type == ACPI_TYPE_INTEGER) {
  116. *result = obj->integer.value;
  117. } else if (obj->type == ACPI_TYPE_BUFFER && obj->buffer.length > 0) {
  118. size_t len = min_t(size_t, obj->buffer.length, 4);
  119. *result = 0;
  120. memcpy(result, obj->buffer.pointer, len);
  121. } else {
  122. dev_err(dev, "%s DSM fn %u obj->type %d obj->buffer.length %d\n",
  123. __func__, fn, obj->type, obj->buffer.length);
  124. err = -EINVAL;
  125. }
  126. ACPI_FREE(obj);
  127. return err;
  128. }
  129. static int intel_dsm(struct intel_host *intel_host, struct device *dev,
  130. unsigned int fn, u32 *result)
  131. {
  132. if (fn > 31 || !(intel_host->dsm_fns & (1 << fn)))
  133. return -EOPNOTSUPP;
  134. return __intel_dsm(intel_host, dev, fn, result);
  135. }
  136. static void intel_dsm_init(struct intel_host *intel_host, struct device *dev,
  137. struct mmc_host *mmc)
  138. {
  139. int err;
  140. intel_host->hs_caps = ~0;
  141. err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns);
  142. if (err) {
  143. pr_debug("%s: DSM not supported, error %d\n",
  144. mmc_hostname(mmc), err);
  145. return;
  146. }
  147. pr_debug("%s: DSM function mask %#x\n",
  148. mmc_hostname(mmc), intel_host->dsm_fns);
  149. intel_dsm(intel_host, dev, INTEL_DSM_HS_CAPS, &intel_host->hs_caps);
  150. }
  151. static int intel_start_signal_voltage_switch(struct mmc_host *mmc,
  152. struct mmc_ios *ios)
  153. {
  154. struct device *dev = mmc_dev(mmc);
  155. struct sdhci_acpi_host *c = dev_get_drvdata(dev);
  156. struct intel_host *intel_host = sdhci_acpi_priv(c);
  157. unsigned int fn;
  158. u32 result = 0;
  159. int err;
  160. err = sdhci_start_signal_voltage_switch(mmc, ios);
  161. if (err)
  162. return err;
  163. switch (ios->signal_voltage) {
  164. case MMC_SIGNAL_VOLTAGE_330:
  165. fn = INTEL_DSM_V33_SWITCH;
  166. break;
  167. case MMC_SIGNAL_VOLTAGE_180:
  168. fn = INTEL_DSM_V18_SWITCH;
  169. break;
  170. default:
  171. return 0;
  172. }
  173. err = intel_dsm(intel_host, dev, fn, &result);
  174. pr_debug("%s: %s DSM fn %u error %d result %u\n",
  175. mmc_hostname(mmc), __func__, fn, err, result);
  176. return 0;
  177. }
  178. static void sdhci_acpi_int_hw_reset(struct sdhci_host *host)
  179. {
  180. u8 reg;
  181. reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
  182. reg |= 0x10;
  183. sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
  184. /* For eMMC, minimum is 1us but give it 9us for good measure */
  185. udelay(9);
  186. reg &= ~0x10;
  187. sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
  188. /* For eMMC, minimum is 200us but give it 300us for good measure */
  189. usleep_range(300, 1000);
  190. }
  191. static const struct sdhci_ops sdhci_acpi_ops_dflt = {
  192. .set_clock = sdhci_set_clock,
  193. .set_bus_width = sdhci_set_bus_width,
  194. .reset = sdhci_reset,
  195. .set_uhs_signaling = sdhci_set_uhs_signaling,
  196. };
  197. static const struct sdhci_ops sdhci_acpi_ops_int = {
  198. .set_clock = sdhci_set_clock,
  199. .set_bus_width = sdhci_set_bus_width,
  200. .reset = sdhci_reset,
  201. .set_uhs_signaling = sdhci_set_uhs_signaling,
  202. .hw_reset = sdhci_acpi_int_hw_reset,
  203. };
  204. static const struct sdhci_acpi_chip sdhci_acpi_chip_int = {
  205. .ops = &sdhci_acpi_ops_int,
  206. };
  207. #ifdef CONFIG_X86
  208. static bool sdhci_acpi_byt(void)
  209. {
  210. static const struct x86_cpu_id byt[] = {
  211. { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT },
  212. {}
  213. };
  214. return x86_match_cpu(byt);
  215. }
  216. static bool sdhci_acpi_cht(void)
  217. {
  218. static const struct x86_cpu_id cht[] = {
  219. { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_AIRMONT },
  220. {}
  221. };
  222. return x86_match_cpu(cht);
  223. }
  224. #define BYT_IOSF_SCCEP 0x63
  225. #define BYT_IOSF_OCP_NETCTRL0 0x1078
  226. #define BYT_IOSF_OCP_TIMEOUT_BASE GENMASK(10, 8)
  227. static void sdhci_acpi_byt_setting(struct device *dev)
  228. {
  229. u32 val = 0;
  230. if (!sdhci_acpi_byt())
  231. return;
  232. if (iosf_mbi_read(BYT_IOSF_SCCEP, MBI_CR_READ, BYT_IOSF_OCP_NETCTRL0,
  233. &val)) {
  234. dev_err(dev, "%s read error\n", __func__);
  235. return;
  236. }
  237. if (!(val & BYT_IOSF_OCP_TIMEOUT_BASE))
  238. return;
  239. val &= ~BYT_IOSF_OCP_TIMEOUT_BASE;
  240. if (iosf_mbi_write(BYT_IOSF_SCCEP, MBI_CR_WRITE, BYT_IOSF_OCP_NETCTRL0,
  241. val)) {
  242. dev_err(dev, "%s write error\n", __func__);
  243. return;
  244. }
  245. dev_dbg(dev, "%s completed\n", __func__);
  246. }
  247. static bool sdhci_acpi_byt_defer(struct device *dev)
  248. {
  249. if (!sdhci_acpi_byt())
  250. return false;
  251. if (!iosf_mbi_available())
  252. return true;
  253. sdhci_acpi_byt_setting(dev);
  254. return false;
  255. }
  256. static bool sdhci_acpi_cht_pci_wifi(unsigned int vendor, unsigned int device,
  257. unsigned int slot, unsigned int parent_slot)
  258. {
  259. struct pci_dev *dev, *parent, *from = NULL;
  260. while (1) {
  261. dev = pci_get_device(vendor, device, from);
  262. pci_dev_put(from);
  263. if (!dev)
  264. break;
  265. parent = pci_upstream_bridge(dev);
  266. if (ACPI_COMPANION(&dev->dev) && PCI_SLOT(dev->devfn) == slot &&
  267. parent && PCI_SLOT(parent->devfn) == parent_slot &&
  268. !pci_upstream_bridge(parent)) {
  269. pci_dev_put(dev);
  270. return true;
  271. }
  272. from = dev;
  273. }
  274. return false;
  275. }
  276. /*
  277. * GPDwin uses PCI wifi which conflicts with SDIO's use of
  278. * acpi_device_fix_up_power() on child device nodes. Identifying GPDwin is
  279. * problematic, but since SDIO is only used for wifi, the presence of the PCI
  280. * wifi card in the expected slot with an ACPI companion node, is used to
  281. * indicate that acpi_device_fix_up_power() should be avoided.
  282. */
  283. static inline bool sdhci_acpi_no_fixup_child_power(const char *hid,
  284. const char *uid)
  285. {
  286. return sdhci_acpi_cht() &&
  287. !strcmp(hid, "80860F14") &&
  288. !strcmp(uid, "2") &&
  289. sdhci_acpi_cht_pci_wifi(0x14e4, 0x43ec, 0, 28);
  290. }
  291. #else
  292. static inline void sdhci_acpi_byt_setting(struct device *dev)
  293. {
  294. }
  295. static inline bool sdhci_acpi_byt_defer(struct device *dev)
  296. {
  297. return false;
  298. }
  299. static inline bool sdhci_acpi_no_fixup_child_power(const char *hid,
  300. const char *uid)
  301. {
  302. return false;
  303. }
  304. #endif
  305. static int bxt_get_cd(struct mmc_host *mmc)
  306. {
  307. int gpio_cd = mmc_gpio_get_cd(mmc);
  308. struct sdhci_host *host = mmc_priv(mmc);
  309. unsigned long flags;
  310. int ret = 0;
  311. if (!gpio_cd)
  312. return 0;
  313. spin_lock_irqsave(&host->lock, flags);
  314. if (host->flags & SDHCI_DEVICE_DEAD)
  315. goto out;
  316. ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
  317. out:
  318. spin_unlock_irqrestore(&host->lock, flags);
  319. return ret;
  320. }
  321. static int intel_probe_slot(struct platform_device *pdev, const char *hid,
  322. const char *uid)
  323. {
  324. struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
  325. struct intel_host *intel_host = sdhci_acpi_priv(c);
  326. struct sdhci_host *host = c->host;
  327. if (hid && uid && !strcmp(hid, "80860F14") && !strcmp(uid, "1") &&
  328. sdhci_readl(host, SDHCI_CAPABILITIES) == 0x446cc8b2 &&
  329. sdhci_readl(host, SDHCI_CAPABILITIES_1) == 0x00000807)
  330. host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
  331. if (hid && !strcmp(hid, "80865ACA"))
  332. host->mmc_host_ops.get_cd = bxt_get_cd;
  333. intel_dsm_init(intel_host, &pdev->dev, host->mmc);
  334. host->mmc_host_ops.start_signal_voltage_switch =
  335. intel_start_signal_voltage_switch;
  336. return 0;
  337. }
  338. static int intel_setup_host(struct platform_device *pdev)
  339. {
  340. struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
  341. struct intel_host *intel_host = sdhci_acpi_priv(c);
  342. if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_SDR25))
  343. c->host->mmc->caps &= ~MMC_CAP_UHS_SDR25;
  344. if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_SDR50))
  345. c->host->mmc->caps &= ~MMC_CAP_UHS_SDR50;
  346. if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_DDR50))
  347. c->host->mmc->caps &= ~MMC_CAP_UHS_DDR50;
  348. if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_SDR104))
  349. c->host->mmc->caps &= ~MMC_CAP_UHS_SDR104;
  350. return 0;
  351. }
  352. static const struct sdhci_acpi_slot sdhci_acpi_slot_int_emmc = {
  353. .chip = &sdhci_acpi_chip_int,
  354. .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
  355. MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
  356. MMC_CAP_CMD_DURING_TFR | MMC_CAP_WAIT_WHILE_BUSY,
  357. .flags = SDHCI_ACPI_RUNTIME_PM,
  358. .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
  359. .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
  360. SDHCI_QUIRK2_STOP_WITH_TC |
  361. SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400,
  362. .probe_slot = intel_probe_slot,
  363. .setup_host = intel_setup_host,
  364. .priv_size = sizeof(struct intel_host),
  365. };
  366. static const struct sdhci_acpi_slot sdhci_acpi_slot_int_sdio = {
  367. .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
  368. SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
  369. .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
  370. .caps = MMC_CAP_NONREMOVABLE | MMC_CAP_POWER_OFF_CARD |
  371. MMC_CAP_WAIT_WHILE_BUSY,
  372. .flags = SDHCI_ACPI_RUNTIME_PM,
  373. .pm_caps = MMC_PM_KEEP_POWER,
  374. .probe_slot = intel_probe_slot,
  375. .setup_host = intel_setup_host,
  376. .priv_size = sizeof(struct intel_host),
  377. };
  378. static const struct sdhci_acpi_slot sdhci_acpi_slot_int_sd = {
  379. .flags = SDHCI_ACPI_SD_CD | SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL |
  380. SDHCI_ACPI_RUNTIME_PM,
  381. .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
  382. .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
  383. SDHCI_QUIRK2_STOP_WITH_TC,
  384. .caps = MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_AGGRESSIVE_PM,
  385. .probe_slot = intel_probe_slot,
  386. .setup_host = intel_setup_host,
  387. .priv_size = sizeof(struct intel_host),
  388. };
  389. static const struct sdhci_acpi_slot sdhci_acpi_slot_qcom_sd_3v = {
  390. .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION,
  391. .quirks2 = SDHCI_QUIRK2_NO_1_8_V,
  392. .caps = MMC_CAP_NONREMOVABLE,
  393. };
  394. static const struct sdhci_acpi_slot sdhci_acpi_slot_qcom_sd = {
  395. .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION,
  396. .caps = MMC_CAP_NONREMOVABLE,
  397. };
  398. /* AMD sdhci reset dll register. */
  399. #define SDHCI_AMD_RESET_DLL_REGISTER 0x908
  400. static int amd_select_drive_strength(struct mmc_card *card,
  401. unsigned int max_dtr, int host_drv,
  402. int card_drv, int *drv_type)
  403. {
  404. return MMC_SET_DRIVER_TYPE_A;
  405. }
  406. static void sdhci_acpi_amd_hs400_dll(struct sdhci_host *host)
  407. {
  408. /* AMD Platform requires dll setting */
  409. sdhci_writel(host, 0x40003210, SDHCI_AMD_RESET_DLL_REGISTER);
  410. usleep_range(10, 20);
  411. sdhci_writel(host, 0x40033210, SDHCI_AMD_RESET_DLL_REGISTER);
  412. }
  413. /*
  414. * For AMD Platform it is required to disable the tuning
  415. * bit first controller to bring to HS Mode from HS200
  416. * mode, later enable to tune to HS400 mode.
  417. */
  418. static void amd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  419. {
  420. struct sdhci_host *host = mmc_priv(mmc);
  421. unsigned int old_timing = host->timing;
  422. sdhci_set_ios(mmc, ios);
  423. if (old_timing == MMC_TIMING_MMC_HS200 &&
  424. ios->timing == MMC_TIMING_MMC_HS)
  425. sdhci_writew(host, 0x9, SDHCI_HOST_CONTROL2);
  426. if (old_timing != MMC_TIMING_MMC_HS400 &&
  427. ios->timing == MMC_TIMING_MMC_HS400) {
  428. sdhci_writew(host, 0x80, SDHCI_HOST_CONTROL2);
  429. sdhci_acpi_amd_hs400_dll(host);
  430. }
  431. }
  432. static const struct sdhci_ops sdhci_acpi_ops_amd = {
  433. .set_clock = sdhci_set_clock,
  434. .set_bus_width = sdhci_set_bus_width,
  435. .reset = sdhci_reset,
  436. .set_uhs_signaling = sdhci_set_uhs_signaling,
  437. };
  438. static const struct sdhci_acpi_chip sdhci_acpi_chip_amd = {
  439. .ops = &sdhci_acpi_ops_amd,
  440. };
  441. static int sdhci_acpi_emmc_amd_probe_slot(struct platform_device *pdev,
  442. const char *hid, const char *uid)
  443. {
  444. struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
  445. struct sdhci_host *host = c->host;
  446. sdhci_read_caps(host);
  447. if (host->caps1 & SDHCI_SUPPORT_DDR50)
  448. host->mmc->caps = MMC_CAP_1_8V_DDR;
  449. if ((host->caps1 & SDHCI_SUPPORT_SDR104) &&
  450. (host->mmc->caps & MMC_CAP_1_8V_DDR))
  451. host->mmc->caps2 = MMC_CAP2_HS400_1_8V;
  452. /*
  453. * There are two types of presets out in the wild:
  454. * 1) Default/broken presets.
  455. * These presets have two sets of problems:
  456. * a) The clock divisor for SDR12, SDR25, and SDR50 is too small.
  457. * This results in clock frequencies that are 2x higher than
  458. * acceptable. i.e., SDR12 = 25 MHz, SDR25 = 50 MHz, SDR50 =
  459. * 100 MHz.x
  460. * b) The HS200 and HS400 driver strengths don't match.
  461. * By default, the SDR104 preset register has a driver strength of
  462. * A, but the (internal) HS400 preset register has a driver
  463. * strength of B. As part of initializing HS400, HS200 tuning
  464. * needs to be performed. Having different driver strengths
  465. * between tuning and operation is wrong. It results in different
  466. * rise/fall times that lead to incorrect sampling.
  467. * 2) Firmware with properly initialized presets.
  468. * These presets have proper clock divisors. i.e., SDR12 => 12MHz,
  469. * SDR25 => 25 MHz, SDR50 => 50 MHz. Additionally the HS200 and
  470. * HS400 preset driver strengths match.
  471. *
  472. * Enabling presets for HS400 doesn't work for the following reasons:
  473. * 1) sdhci_set_ios has a hard coded list of timings that are used
  474. * to determine if presets should be enabled.
  475. * 2) sdhci_get_preset_value is using a non-standard register to
  476. * read out HS400 presets. The AMD controller doesn't support this
  477. * non-standard register. In fact, it doesn't expose the HS400
  478. * preset register anywhere in the SDHCI memory map. This results
  479. * in reading a garbage value and using the wrong presets.
  480. *
  481. * Since HS400 and HS200 presets must be identical, we could
  482. * instead use the the SDR104 preset register.
  483. *
  484. * If the above issues are resolved we could remove this quirk for
  485. * firmware that that has valid presets (i.e., SDR12 <= 12 MHz).
  486. */
  487. host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
  488. host->mmc_host_ops.select_drive_strength = amd_select_drive_strength;
  489. host->mmc_host_ops.set_ios = amd_set_ios;
  490. return 0;
  491. }
  492. static const struct sdhci_acpi_slot sdhci_acpi_slot_amd_emmc = {
  493. .chip = &sdhci_acpi_chip_amd,
  494. .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
  495. .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
  496. SDHCI_QUIRK_32BIT_DMA_SIZE |
  497. SDHCI_QUIRK_32BIT_ADMA_SIZE,
  498. .quirks2 = SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
  499. .probe_slot = sdhci_acpi_emmc_amd_probe_slot,
  500. };
  501. struct sdhci_acpi_uid_slot {
  502. const char *hid;
  503. const char *uid;
  504. const struct sdhci_acpi_slot *slot;
  505. };
  506. static const struct sdhci_acpi_uid_slot sdhci_acpi_uids[] = {
  507. { "80865ACA", NULL, &sdhci_acpi_slot_int_sd },
  508. { "80865ACC", NULL, &sdhci_acpi_slot_int_emmc },
  509. { "80865AD0", NULL, &sdhci_acpi_slot_int_sdio },
  510. { "80860F14" , "1" , &sdhci_acpi_slot_int_emmc },
  511. { "80860F14" , "2" , &sdhci_acpi_slot_int_sdio },
  512. { "80860F14" , "3" , &sdhci_acpi_slot_int_sd },
  513. { "80860F16" , NULL, &sdhci_acpi_slot_int_sd },
  514. { "INT33BB" , "2" , &sdhci_acpi_slot_int_sdio },
  515. { "INT33BB" , "3" , &sdhci_acpi_slot_int_sd },
  516. { "INT33C6" , NULL, &sdhci_acpi_slot_int_sdio },
  517. { "INT3436" , NULL, &sdhci_acpi_slot_int_sdio },
  518. { "INT344D" , NULL, &sdhci_acpi_slot_int_sdio },
  519. { "PNP0FFF" , "3" , &sdhci_acpi_slot_int_sd },
  520. { "PNP0D40" },
  521. { "QCOM8051", NULL, &sdhci_acpi_slot_qcom_sd_3v },
  522. { "QCOM8052", NULL, &sdhci_acpi_slot_qcom_sd },
  523. { "AMDI0040", NULL, &sdhci_acpi_slot_amd_emmc },
  524. { },
  525. };
  526. static const struct acpi_device_id sdhci_acpi_ids[] = {
  527. { "80865ACA" },
  528. { "80865ACC" },
  529. { "80865AD0" },
  530. { "80860F14" },
  531. { "80860F16" },
  532. { "INT33BB" },
  533. { "INT33C6" },
  534. { "INT3436" },
  535. { "INT344D" },
  536. { "PNP0D40" },
  537. { "QCOM8051" },
  538. { "QCOM8052" },
  539. { "AMDI0040" },
  540. { },
  541. };
  542. MODULE_DEVICE_TABLE(acpi, sdhci_acpi_ids);
  543. static const struct sdhci_acpi_slot *sdhci_acpi_get_slot(const char *hid,
  544. const char *uid)
  545. {
  546. const struct sdhci_acpi_uid_slot *u;
  547. for (u = sdhci_acpi_uids; u->hid; u++) {
  548. if (strcmp(u->hid, hid))
  549. continue;
  550. if (!u->uid)
  551. return u->slot;
  552. if (uid && !strcmp(u->uid, uid))
  553. return u->slot;
  554. }
  555. return NULL;
  556. }
  557. static int sdhci_acpi_probe(struct platform_device *pdev)
  558. {
  559. struct device *dev = &pdev->dev;
  560. const struct sdhci_acpi_slot *slot;
  561. struct acpi_device *device, *child;
  562. struct sdhci_acpi_host *c;
  563. struct sdhci_host *host;
  564. struct resource *iomem;
  565. resource_size_t len;
  566. size_t priv_size;
  567. const char *hid;
  568. const char *uid;
  569. int err;
  570. device = ACPI_COMPANION(dev);
  571. if (!device)
  572. return -ENODEV;
  573. hid = acpi_device_hid(device);
  574. uid = acpi_device_uid(device);
  575. slot = sdhci_acpi_get_slot(hid, uid);
  576. /* Power on the SDHCI controller and its children */
  577. acpi_device_fix_up_power(device);
  578. if (!sdhci_acpi_no_fixup_child_power(hid, uid)) {
  579. list_for_each_entry(child, &device->children, node)
  580. if (child->status.present && child->status.enabled)
  581. acpi_device_fix_up_power(child);
  582. }
  583. if (sdhci_acpi_byt_defer(dev))
  584. return -EPROBE_DEFER;
  585. iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  586. if (!iomem)
  587. return -ENOMEM;
  588. len = resource_size(iomem);
  589. if (len < 0x100)
  590. dev_err(dev, "Invalid iomem size!\n");
  591. if (!devm_request_mem_region(dev, iomem->start, len, dev_name(dev)))
  592. return -ENOMEM;
  593. priv_size = slot ? slot->priv_size : 0;
  594. host = sdhci_alloc_host(dev, sizeof(struct sdhci_acpi_host) + priv_size);
  595. if (IS_ERR(host))
  596. return PTR_ERR(host);
  597. c = sdhci_priv(host);
  598. c->host = host;
  599. c->slot = slot;
  600. c->pdev = pdev;
  601. c->use_runtime_pm = sdhci_acpi_flag(c, SDHCI_ACPI_RUNTIME_PM);
  602. platform_set_drvdata(pdev, c);
  603. host->hw_name = "ACPI";
  604. host->ops = &sdhci_acpi_ops_dflt;
  605. host->irq = platform_get_irq(pdev, 0);
  606. if (host->irq < 0) {
  607. err = -EINVAL;
  608. goto err_free;
  609. }
  610. host->ioaddr = devm_ioremap_nocache(dev, iomem->start,
  611. resource_size(iomem));
  612. if (host->ioaddr == NULL) {
  613. err = -ENOMEM;
  614. goto err_free;
  615. }
  616. if (c->slot) {
  617. if (c->slot->probe_slot) {
  618. err = c->slot->probe_slot(pdev, hid, uid);
  619. if (err)
  620. goto err_free;
  621. }
  622. if (c->slot->chip) {
  623. host->ops = c->slot->chip->ops;
  624. host->quirks |= c->slot->chip->quirks;
  625. host->quirks2 |= c->slot->chip->quirks2;
  626. host->mmc->caps |= c->slot->chip->caps;
  627. host->mmc->caps2 |= c->slot->chip->caps2;
  628. host->mmc->pm_caps |= c->slot->chip->pm_caps;
  629. }
  630. host->quirks |= c->slot->quirks;
  631. host->quirks2 |= c->slot->quirks2;
  632. host->mmc->caps |= c->slot->caps;
  633. host->mmc->caps2 |= c->slot->caps2;
  634. host->mmc->pm_caps |= c->slot->pm_caps;
  635. }
  636. host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
  637. if (sdhci_acpi_flag(c, SDHCI_ACPI_SD_CD)) {
  638. bool v = sdhci_acpi_flag(c, SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL);
  639. err = mmc_gpiod_request_cd(host->mmc, NULL, 0, v, 0, NULL);
  640. if (err) {
  641. if (err == -EPROBE_DEFER)
  642. goto err_free;
  643. dev_warn(dev, "failed to setup card detect gpio\n");
  644. c->use_runtime_pm = false;
  645. }
  646. }
  647. err = sdhci_setup_host(host);
  648. if (err)
  649. goto err_free;
  650. if (c->slot && c->slot->setup_host) {
  651. err = c->slot->setup_host(pdev);
  652. if (err)
  653. goto err_cleanup;
  654. }
  655. err = __sdhci_add_host(host);
  656. if (err)
  657. goto err_cleanup;
  658. if (c->use_runtime_pm) {
  659. pm_runtime_set_active(dev);
  660. pm_suspend_ignore_children(dev, 1);
  661. pm_runtime_set_autosuspend_delay(dev, 50);
  662. pm_runtime_use_autosuspend(dev);
  663. pm_runtime_enable(dev);
  664. }
  665. device_enable_async_suspend(dev);
  666. return 0;
  667. err_cleanup:
  668. sdhci_cleanup_host(c->host);
  669. err_free:
  670. if (c->slot && c->slot->free_slot)
  671. c->slot->free_slot(pdev);
  672. sdhci_free_host(c->host);
  673. return err;
  674. }
  675. static int sdhci_acpi_remove(struct platform_device *pdev)
  676. {
  677. struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
  678. struct device *dev = &pdev->dev;
  679. int dead;
  680. if (c->use_runtime_pm) {
  681. pm_runtime_get_sync(dev);
  682. pm_runtime_disable(dev);
  683. pm_runtime_put_noidle(dev);
  684. }
  685. if (c->slot && c->slot->remove_slot)
  686. c->slot->remove_slot(pdev);
  687. dead = (sdhci_readl(c->host, SDHCI_INT_STATUS) == ~0);
  688. sdhci_remove_host(c->host, dead);
  689. if (c->slot && c->slot->free_slot)
  690. c->slot->free_slot(pdev);
  691. sdhci_free_host(c->host);
  692. return 0;
  693. }
  694. #ifdef CONFIG_PM_SLEEP
  695. static int sdhci_acpi_suspend(struct device *dev)
  696. {
  697. struct sdhci_acpi_host *c = dev_get_drvdata(dev);
  698. struct sdhci_host *host = c->host;
  699. if (host->tuning_mode != SDHCI_TUNING_MODE_3)
  700. mmc_retune_needed(host->mmc);
  701. return sdhci_suspend_host(host);
  702. }
  703. static int sdhci_acpi_resume(struct device *dev)
  704. {
  705. struct sdhci_acpi_host *c = dev_get_drvdata(dev);
  706. sdhci_acpi_byt_setting(&c->pdev->dev);
  707. return sdhci_resume_host(c->host);
  708. }
  709. #endif
  710. #ifdef CONFIG_PM
  711. static int sdhci_acpi_runtime_suspend(struct device *dev)
  712. {
  713. struct sdhci_acpi_host *c = dev_get_drvdata(dev);
  714. struct sdhci_host *host = c->host;
  715. if (host->tuning_mode != SDHCI_TUNING_MODE_3)
  716. mmc_retune_needed(host->mmc);
  717. return sdhci_runtime_suspend_host(host);
  718. }
  719. static int sdhci_acpi_runtime_resume(struct device *dev)
  720. {
  721. struct sdhci_acpi_host *c = dev_get_drvdata(dev);
  722. sdhci_acpi_byt_setting(&c->pdev->dev);
  723. return sdhci_runtime_resume_host(c->host);
  724. }
  725. #endif
  726. static const struct dev_pm_ops sdhci_acpi_pm_ops = {
  727. SET_SYSTEM_SLEEP_PM_OPS(sdhci_acpi_suspend, sdhci_acpi_resume)
  728. SET_RUNTIME_PM_OPS(sdhci_acpi_runtime_suspend,
  729. sdhci_acpi_runtime_resume, NULL)
  730. };
  731. static struct platform_driver sdhci_acpi_driver = {
  732. .driver = {
  733. .name = "sdhci-acpi",
  734. .acpi_match_table = sdhci_acpi_ids,
  735. .pm = &sdhci_acpi_pm_ops,
  736. },
  737. .probe = sdhci_acpi_probe,
  738. .remove = sdhci_acpi_remove,
  739. };
  740. module_platform_driver(sdhci_acpi_driver);
  741. MODULE_DESCRIPTION("Secure Digital Host Controller Interface ACPI driver");
  742. MODULE_AUTHOR("Adrian Hunter");
  743. MODULE_LICENSE("GPL v2");