sdhci-cadence.c 12 KB

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  1. /*
  2. * Copyright (C) 2016 Socionext Inc.
  3. * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation; either version 2 of the License, or
  8. * (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. */
  15. #include <linux/bitfield.h>
  16. #include <linux/bitops.h>
  17. #include <linux/iopoll.h>
  18. #include <linux/module.h>
  19. #include <linux/mmc/host.h>
  20. #include <linux/mmc/mmc.h>
  21. #include <linux/of.h>
  22. #include "sdhci-pltfm.h"
  23. /* HRS - Host Register Set (specific to Cadence) */
  24. #define SDHCI_CDNS_HRS04 0x10 /* PHY access port */
  25. #define SDHCI_CDNS_HRS04_ACK BIT(26)
  26. #define SDHCI_CDNS_HRS04_RD BIT(25)
  27. #define SDHCI_CDNS_HRS04_WR BIT(24)
  28. #define SDHCI_CDNS_HRS04_RDATA GENMASK(23, 16)
  29. #define SDHCI_CDNS_HRS04_WDATA GENMASK(15, 8)
  30. #define SDHCI_CDNS_HRS04_ADDR GENMASK(5, 0)
  31. #define SDHCI_CDNS_HRS06 0x18 /* eMMC control */
  32. #define SDHCI_CDNS_HRS06_TUNE_UP BIT(15)
  33. #define SDHCI_CDNS_HRS06_TUNE GENMASK(13, 8)
  34. #define SDHCI_CDNS_HRS06_MODE GENMASK(2, 0)
  35. #define SDHCI_CDNS_HRS06_MODE_SD 0x0
  36. #define SDHCI_CDNS_HRS06_MODE_MMC_SDR 0x2
  37. #define SDHCI_CDNS_HRS06_MODE_MMC_DDR 0x3
  38. #define SDHCI_CDNS_HRS06_MODE_MMC_HS200 0x4
  39. #define SDHCI_CDNS_HRS06_MODE_MMC_HS400 0x5
  40. #define SDHCI_CDNS_HRS06_MODE_MMC_HS400ES 0x6
  41. /* SRS - Slot Register Set (SDHCI-compatible) */
  42. #define SDHCI_CDNS_SRS_BASE 0x200
  43. /* PHY */
  44. #define SDHCI_CDNS_PHY_DLY_SD_HS 0x00
  45. #define SDHCI_CDNS_PHY_DLY_SD_DEFAULT 0x01
  46. #define SDHCI_CDNS_PHY_DLY_UHS_SDR12 0x02
  47. #define SDHCI_CDNS_PHY_DLY_UHS_SDR25 0x03
  48. #define SDHCI_CDNS_PHY_DLY_UHS_SDR50 0x04
  49. #define SDHCI_CDNS_PHY_DLY_UHS_DDR50 0x05
  50. #define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY 0x06
  51. #define SDHCI_CDNS_PHY_DLY_EMMC_SDR 0x07
  52. #define SDHCI_CDNS_PHY_DLY_EMMC_DDR 0x08
  53. #define SDHCI_CDNS_PHY_DLY_SDCLK 0x0b
  54. #define SDHCI_CDNS_PHY_DLY_HSMMC 0x0c
  55. #define SDHCI_CDNS_PHY_DLY_STROBE 0x0d
  56. /*
  57. * The tuned val register is 6 bit-wide, but not the whole of the range is
  58. * available. The range 0-42 seems to be available (then 43 wraps around to 0)
  59. * but I am not quite sure if it is official. Use only 0 to 39 for safety.
  60. */
  61. #define SDHCI_CDNS_MAX_TUNING_LOOP 40
  62. struct sdhci_cdns_phy_param {
  63. u8 addr;
  64. u8 data;
  65. };
  66. struct sdhci_cdns_priv {
  67. void __iomem *hrs_addr;
  68. bool enhanced_strobe;
  69. unsigned int nr_phy_params;
  70. struct sdhci_cdns_phy_param phy_params[0];
  71. };
  72. struct sdhci_cdns_phy_cfg {
  73. const char *property;
  74. u8 addr;
  75. };
  76. static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = {
  77. { "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, },
  78. { "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, },
  79. { "cdns,phy-input-delay-sd-uhs-sdr12", SDHCI_CDNS_PHY_DLY_UHS_SDR12, },
  80. { "cdns,phy-input-delay-sd-uhs-sdr25", SDHCI_CDNS_PHY_DLY_UHS_SDR25, },
  81. { "cdns,phy-input-delay-sd-uhs-sdr50", SDHCI_CDNS_PHY_DLY_UHS_SDR50, },
  82. { "cdns,phy-input-delay-sd-uhs-ddr50", SDHCI_CDNS_PHY_DLY_UHS_DDR50, },
  83. { "cdns,phy-input-delay-mmc-highspeed", SDHCI_CDNS_PHY_DLY_EMMC_SDR, },
  84. { "cdns,phy-input-delay-mmc-ddr", SDHCI_CDNS_PHY_DLY_EMMC_DDR, },
  85. { "cdns,phy-dll-delay-sdclk", SDHCI_CDNS_PHY_DLY_SDCLK, },
  86. { "cdns,phy-dll-delay-sdclk-hsmmc", SDHCI_CDNS_PHY_DLY_HSMMC, },
  87. { "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, },
  88. };
  89. static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv,
  90. u8 addr, u8 data)
  91. {
  92. void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS04;
  93. u32 tmp;
  94. int ret;
  95. tmp = FIELD_PREP(SDHCI_CDNS_HRS04_WDATA, data) |
  96. FIELD_PREP(SDHCI_CDNS_HRS04_ADDR, addr);
  97. writel(tmp, reg);
  98. tmp |= SDHCI_CDNS_HRS04_WR;
  99. writel(tmp, reg);
  100. ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 0, 10);
  101. if (ret)
  102. return ret;
  103. tmp &= ~SDHCI_CDNS_HRS04_WR;
  104. writel(tmp, reg);
  105. return 0;
  106. }
  107. static unsigned int sdhci_cdns_phy_param_count(struct device_node *np)
  108. {
  109. unsigned int count = 0;
  110. int i;
  111. for (i = 0; i < ARRAY_SIZE(sdhci_cdns_phy_cfgs); i++)
  112. if (of_property_read_bool(np, sdhci_cdns_phy_cfgs[i].property))
  113. count++;
  114. return count;
  115. }
  116. static void sdhci_cdns_phy_param_parse(struct device_node *np,
  117. struct sdhci_cdns_priv *priv)
  118. {
  119. struct sdhci_cdns_phy_param *p = priv->phy_params;
  120. u32 val;
  121. int ret, i;
  122. for (i = 0; i < ARRAY_SIZE(sdhci_cdns_phy_cfgs); i++) {
  123. ret = of_property_read_u32(np, sdhci_cdns_phy_cfgs[i].property,
  124. &val);
  125. if (ret)
  126. continue;
  127. p->addr = sdhci_cdns_phy_cfgs[i].addr;
  128. p->data = val;
  129. p++;
  130. }
  131. }
  132. static int sdhci_cdns_phy_init(struct sdhci_cdns_priv *priv)
  133. {
  134. int ret, i;
  135. for (i = 0; i < priv->nr_phy_params; i++) {
  136. ret = sdhci_cdns_write_phy_reg(priv, priv->phy_params[i].addr,
  137. priv->phy_params[i].data);
  138. if (ret)
  139. return ret;
  140. }
  141. return 0;
  142. }
  143. static inline void *sdhci_cdns_priv(struct sdhci_host *host)
  144. {
  145. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  146. return sdhci_pltfm_priv(pltfm_host);
  147. }
  148. static unsigned int sdhci_cdns_get_timeout_clock(struct sdhci_host *host)
  149. {
  150. /*
  151. * Cadence's spec says the Timeout Clock Frequency is the same as the
  152. * Base Clock Frequency.
  153. */
  154. return host->max_clk;
  155. }
  156. static void sdhci_cdns_set_emmc_mode(struct sdhci_cdns_priv *priv, u32 mode)
  157. {
  158. u32 tmp;
  159. /* The speed mode for eMMC is selected by HRS06 register */
  160. tmp = readl(priv->hrs_addr + SDHCI_CDNS_HRS06);
  161. tmp &= ~SDHCI_CDNS_HRS06_MODE;
  162. tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_MODE, mode);
  163. writel(tmp, priv->hrs_addr + SDHCI_CDNS_HRS06);
  164. }
  165. static u32 sdhci_cdns_get_emmc_mode(struct sdhci_cdns_priv *priv)
  166. {
  167. u32 tmp;
  168. tmp = readl(priv->hrs_addr + SDHCI_CDNS_HRS06);
  169. return FIELD_GET(SDHCI_CDNS_HRS06_MODE, tmp);
  170. }
  171. static void sdhci_cdns_set_uhs_signaling(struct sdhci_host *host,
  172. unsigned int timing)
  173. {
  174. struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
  175. u32 mode;
  176. switch (timing) {
  177. case MMC_TIMING_MMC_HS:
  178. mode = SDHCI_CDNS_HRS06_MODE_MMC_SDR;
  179. break;
  180. case MMC_TIMING_MMC_DDR52:
  181. mode = SDHCI_CDNS_HRS06_MODE_MMC_DDR;
  182. break;
  183. case MMC_TIMING_MMC_HS200:
  184. mode = SDHCI_CDNS_HRS06_MODE_MMC_HS200;
  185. break;
  186. case MMC_TIMING_MMC_HS400:
  187. if (priv->enhanced_strobe)
  188. mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400ES;
  189. else
  190. mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400;
  191. break;
  192. default:
  193. mode = SDHCI_CDNS_HRS06_MODE_SD;
  194. break;
  195. }
  196. sdhci_cdns_set_emmc_mode(priv, mode);
  197. /* For SD, fall back to the default handler */
  198. if (mode == SDHCI_CDNS_HRS06_MODE_SD)
  199. sdhci_set_uhs_signaling(host, timing);
  200. }
  201. static const struct sdhci_ops sdhci_cdns_ops = {
  202. .set_clock = sdhci_set_clock,
  203. .get_timeout_clock = sdhci_cdns_get_timeout_clock,
  204. .set_bus_width = sdhci_set_bus_width,
  205. .reset = sdhci_reset,
  206. .set_uhs_signaling = sdhci_cdns_set_uhs_signaling,
  207. };
  208. static const struct sdhci_pltfm_data sdhci_cdns_pltfm_data = {
  209. .ops = &sdhci_cdns_ops,
  210. };
  211. static int sdhci_cdns_set_tune_val(struct sdhci_host *host, unsigned int val)
  212. {
  213. struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
  214. void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS06;
  215. u32 tmp;
  216. int i, ret;
  217. if (WARN_ON(!FIELD_FIT(SDHCI_CDNS_HRS06_TUNE, val)))
  218. return -EINVAL;
  219. tmp = readl(reg);
  220. tmp &= ~SDHCI_CDNS_HRS06_TUNE;
  221. tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_TUNE, val);
  222. /*
  223. * Workaround for IP errata:
  224. * The IP6116 SD/eMMC PHY design has a timing issue on receive data
  225. * path. Send tune request twice.
  226. */
  227. for (i = 0; i < 2; i++) {
  228. tmp |= SDHCI_CDNS_HRS06_TUNE_UP;
  229. writel(tmp, reg);
  230. ret = readl_poll_timeout(reg, tmp,
  231. !(tmp & SDHCI_CDNS_HRS06_TUNE_UP),
  232. 0, 1);
  233. if (ret)
  234. return ret;
  235. }
  236. return 0;
  237. }
  238. static int sdhci_cdns_execute_tuning(struct mmc_host *mmc, u32 opcode)
  239. {
  240. struct sdhci_host *host = mmc_priv(mmc);
  241. int cur_streak = 0;
  242. int max_streak = 0;
  243. int end_of_streak = 0;
  244. int i;
  245. /*
  246. * This handler only implements the eMMC tuning that is specific to
  247. * this controller. Fall back to the standard method for SD timing.
  248. */
  249. if (host->timing != MMC_TIMING_MMC_HS200)
  250. return sdhci_execute_tuning(mmc, opcode);
  251. if (WARN_ON(opcode != MMC_SEND_TUNING_BLOCK_HS200))
  252. return -EINVAL;
  253. for (i = 0; i < SDHCI_CDNS_MAX_TUNING_LOOP; i++) {
  254. if (sdhci_cdns_set_tune_val(host, i) ||
  255. mmc_send_tuning(host->mmc, opcode, NULL)) { /* bad */
  256. cur_streak = 0;
  257. } else { /* good */
  258. cur_streak++;
  259. if (cur_streak > max_streak) {
  260. max_streak = cur_streak;
  261. end_of_streak = i;
  262. }
  263. }
  264. }
  265. if (!max_streak) {
  266. dev_err(mmc_dev(host->mmc), "no tuning point found\n");
  267. return -EIO;
  268. }
  269. return sdhci_cdns_set_tune_val(host, end_of_streak - max_streak / 2);
  270. }
  271. static void sdhci_cdns_hs400_enhanced_strobe(struct mmc_host *mmc,
  272. struct mmc_ios *ios)
  273. {
  274. struct sdhci_host *host = mmc_priv(mmc);
  275. struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
  276. u32 mode;
  277. priv->enhanced_strobe = ios->enhanced_strobe;
  278. mode = sdhci_cdns_get_emmc_mode(priv);
  279. if (mode == SDHCI_CDNS_HRS06_MODE_MMC_HS400 && ios->enhanced_strobe)
  280. sdhci_cdns_set_emmc_mode(priv,
  281. SDHCI_CDNS_HRS06_MODE_MMC_HS400ES);
  282. if (mode == SDHCI_CDNS_HRS06_MODE_MMC_HS400ES && !ios->enhanced_strobe)
  283. sdhci_cdns_set_emmc_mode(priv,
  284. SDHCI_CDNS_HRS06_MODE_MMC_HS400);
  285. }
  286. static int sdhci_cdns_probe(struct platform_device *pdev)
  287. {
  288. struct sdhci_host *host;
  289. struct sdhci_pltfm_host *pltfm_host;
  290. struct sdhci_cdns_priv *priv;
  291. struct clk *clk;
  292. size_t priv_size;
  293. unsigned int nr_phy_params;
  294. int ret;
  295. struct device *dev = &pdev->dev;
  296. clk = devm_clk_get(dev, NULL);
  297. if (IS_ERR(clk))
  298. return PTR_ERR(clk);
  299. ret = clk_prepare_enable(clk);
  300. if (ret)
  301. return ret;
  302. nr_phy_params = sdhci_cdns_phy_param_count(dev->of_node);
  303. priv_size = sizeof(*priv) + sizeof(priv->phy_params[0]) * nr_phy_params;
  304. host = sdhci_pltfm_init(pdev, &sdhci_cdns_pltfm_data, priv_size);
  305. if (IS_ERR(host)) {
  306. ret = PTR_ERR(host);
  307. goto disable_clk;
  308. }
  309. pltfm_host = sdhci_priv(host);
  310. pltfm_host->clk = clk;
  311. priv = sdhci_pltfm_priv(pltfm_host);
  312. priv->nr_phy_params = nr_phy_params;
  313. priv->hrs_addr = host->ioaddr;
  314. priv->enhanced_strobe = false;
  315. host->ioaddr += SDHCI_CDNS_SRS_BASE;
  316. host->mmc_host_ops.execute_tuning = sdhci_cdns_execute_tuning;
  317. host->mmc_host_ops.hs400_enhanced_strobe =
  318. sdhci_cdns_hs400_enhanced_strobe;
  319. sdhci_get_of_property(pdev);
  320. ret = mmc_of_parse(host->mmc);
  321. if (ret)
  322. goto free;
  323. sdhci_cdns_phy_param_parse(dev->of_node, priv);
  324. ret = sdhci_cdns_phy_init(priv);
  325. if (ret)
  326. goto free;
  327. ret = sdhci_add_host(host);
  328. if (ret)
  329. goto free;
  330. return 0;
  331. free:
  332. sdhci_pltfm_free(pdev);
  333. disable_clk:
  334. clk_disable_unprepare(clk);
  335. return ret;
  336. }
  337. #ifdef CONFIG_PM_SLEEP
  338. static int sdhci_cdns_resume(struct device *dev)
  339. {
  340. struct sdhci_host *host = dev_get_drvdata(dev);
  341. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  342. struct sdhci_cdns_priv *priv = sdhci_pltfm_priv(pltfm_host);
  343. int ret;
  344. ret = clk_prepare_enable(pltfm_host->clk);
  345. if (ret)
  346. return ret;
  347. ret = sdhci_cdns_phy_init(priv);
  348. if (ret)
  349. goto disable_clk;
  350. ret = sdhci_resume_host(host);
  351. if (ret)
  352. goto disable_clk;
  353. return 0;
  354. disable_clk:
  355. clk_disable_unprepare(pltfm_host->clk);
  356. return ret;
  357. }
  358. #endif
  359. static const struct dev_pm_ops sdhci_cdns_pm_ops = {
  360. SET_SYSTEM_SLEEP_PM_OPS(sdhci_pltfm_suspend, sdhci_cdns_resume)
  361. };
  362. static const struct of_device_id sdhci_cdns_match[] = {
  363. { .compatible = "socionext,uniphier-sd4hc" },
  364. { .compatible = "cdns,sd4hc" },
  365. { /* sentinel */ }
  366. };
  367. MODULE_DEVICE_TABLE(of, sdhci_cdns_match);
  368. static struct platform_driver sdhci_cdns_driver = {
  369. .driver = {
  370. .name = "sdhci-cdns",
  371. .pm = &sdhci_cdns_pm_ops,
  372. .of_match_table = sdhci_cdns_match,
  373. },
  374. .probe = sdhci_cdns_probe,
  375. .remove = sdhci_pltfm_unregister,
  376. };
  377. module_platform_driver(sdhci_cdns_driver);
  378. MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
  379. MODULE_DESCRIPTION("Cadence SD/SDIO/eMMC Host Controller Driver");
  380. MODULE_LICENSE("GPL");