sdhci-esdhc-imx.c 43 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Freescale eSDHC i.MX controller driver for the platform bus.
  4. *
  5. * derived from the OF-version.
  6. *
  7. * Copyright (c) 2010 Pengutronix e.K.
  8. * Author: Wolfram Sang <kernel@pengutronix.de>
  9. */
  10. #include <linux/io.h>
  11. #include <linux/delay.h>
  12. #include <linux/err.h>
  13. #include <linux/clk.h>
  14. #include <linux/gpio.h>
  15. #include <linux/module.h>
  16. #include <linux/slab.h>
  17. #include <linux/mmc/host.h>
  18. #include <linux/mmc/mmc.h>
  19. #include <linux/mmc/sdio.h>
  20. #include <linux/mmc/slot-gpio.h>
  21. #include <linux/of.h>
  22. #include <linux/of_device.h>
  23. #include <linux/of_gpio.h>
  24. #include <linux/pinctrl/consumer.h>
  25. #include <linux/platform_data/mmc-esdhc-imx.h>
  26. #include <linux/pm_runtime.h>
  27. #include "sdhci-pltfm.h"
  28. #include "sdhci-esdhc.h"
  29. #define ESDHC_SYS_CTRL_DTOCV_MASK 0x0f
  30. #define ESDHC_CTRL_D3CD 0x08
  31. #define ESDHC_BURST_LEN_EN_INCR (1 << 27)
  32. /* VENDOR SPEC register */
  33. #define ESDHC_VENDOR_SPEC 0xc0
  34. #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1)
  35. #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1)
  36. #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
  37. #define ESDHC_WTMK_LVL 0x44
  38. #define ESDHC_WTMK_DEFAULT_VAL 0x10401040
  39. #define ESDHC_WTMK_LVL_RD_WML_MASK 0x000000FF
  40. #define ESDHC_WTMK_LVL_RD_WML_SHIFT 0
  41. #define ESDHC_WTMK_LVL_WR_WML_MASK 0x00FF0000
  42. #define ESDHC_WTMK_LVL_WR_WML_SHIFT 16
  43. #define ESDHC_WTMK_LVL_WML_VAL_DEF 64
  44. #define ESDHC_WTMK_LVL_WML_VAL_MAX 128
  45. #define ESDHC_MIX_CTRL 0x48
  46. #define ESDHC_MIX_CTRL_DDREN (1 << 3)
  47. #define ESDHC_MIX_CTRL_AC23EN (1 << 7)
  48. #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22)
  49. #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23)
  50. #define ESDHC_MIX_CTRL_AUTO_TUNE_EN (1 << 24)
  51. #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25)
  52. #define ESDHC_MIX_CTRL_HS400_EN (1 << 26)
  53. /* Bits 3 and 6 are not SDHCI standard definitions */
  54. #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7
  55. /* Tuning bits */
  56. #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000
  57. /* dll control register */
  58. #define ESDHC_DLL_CTRL 0x60
  59. #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9
  60. #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8
  61. /* tune control register */
  62. #define ESDHC_TUNE_CTRL_STATUS 0x68
  63. #define ESDHC_TUNE_CTRL_STEP 1
  64. #define ESDHC_TUNE_CTRL_MIN 0
  65. #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1)
  66. /* strobe dll register */
  67. #define ESDHC_STROBE_DLL_CTRL 0x70
  68. #define ESDHC_STROBE_DLL_CTRL_ENABLE (1 << 0)
  69. #define ESDHC_STROBE_DLL_CTRL_RESET (1 << 1)
  70. #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3
  71. #define ESDHC_STROBE_DLL_STATUS 0x74
  72. #define ESDHC_STROBE_DLL_STS_REF_LOCK (1 << 1)
  73. #define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1
  74. #define ESDHC_TUNING_CTRL 0xcc
  75. #define ESDHC_STD_TUNING_EN (1 << 24)
  76. /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
  77. #define ESDHC_TUNING_START_TAP_DEFAULT 0x1
  78. #define ESDHC_TUNING_START_TAP_MASK 0x7f
  79. #define ESDHC_TUNING_STEP_MASK 0x00070000
  80. #define ESDHC_TUNING_STEP_SHIFT 16
  81. /* pinctrl state */
  82. #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz"
  83. #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz"
  84. /*
  85. * Our interpretation of the SDHCI_HOST_CONTROL register
  86. */
  87. #define ESDHC_CTRL_4BITBUS (0x1 << 1)
  88. #define ESDHC_CTRL_8BITBUS (0x2 << 1)
  89. #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
  90. /*
  91. * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC:
  92. * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
  93. * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
  94. * Define this macro DMA error INT for fsl eSDHC
  95. */
  96. #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28)
  97. /*
  98. * The CMDTYPE of the CMD register (offset 0xE) should be set to
  99. * "11" when the STOP CMD12 is issued on imx53 to abort one
  100. * open ended multi-blk IO. Otherwise the TC INT wouldn't
  101. * be generated.
  102. * In exact block transfer, the controller doesn't complete the
  103. * operations automatically as required at the end of the
  104. * transfer and remains on hold if the abort command is not sent.
  105. * As a result, the TC flag is not asserted and SW received timeout
  106. * exception. Bit1 of Vendor Spec register is used to fix it.
  107. */
  108. #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1)
  109. /*
  110. * The flag tells that the ESDHC controller is an USDHC block that is
  111. * integrated on the i.MX6 series.
  112. */
  113. #define ESDHC_FLAG_USDHC BIT(3)
  114. /* The IP supports manual tuning process */
  115. #define ESDHC_FLAG_MAN_TUNING BIT(4)
  116. /* The IP supports standard tuning process */
  117. #define ESDHC_FLAG_STD_TUNING BIT(5)
  118. /* The IP has SDHCI_CAPABILITIES_1 register */
  119. #define ESDHC_FLAG_HAVE_CAP1 BIT(6)
  120. /*
  121. * The IP has erratum ERR004536
  122. * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow,
  123. * when reading data from the card
  124. * This flag is also set for i.MX25 and i.MX35 in order to get
  125. * SDHCI_QUIRK_BROKEN_ADMA, but for different reasons (ADMA capability bits).
  126. */
  127. #define ESDHC_FLAG_ERR004536 BIT(7)
  128. /* The IP supports HS200 mode */
  129. #define ESDHC_FLAG_HS200 BIT(8)
  130. /* The IP supports HS400 mode */
  131. #define ESDHC_FLAG_HS400 BIT(9)
  132. /* A clock frequency higher than this rate requires strobe dll control */
  133. #define ESDHC_STROBE_DLL_CLK_FREQ 100000000
  134. struct esdhc_soc_data {
  135. u32 flags;
  136. };
  137. static struct esdhc_soc_data esdhc_imx25_data = {
  138. .flags = ESDHC_FLAG_ERR004536,
  139. };
  140. static struct esdhc_soc_data esdhc_imx35_data = {
  141. .flags = ESDHC_FLAG_ERR004536,
  142. };
  143. static struct esdhc_soc_data esdhc_imx51_data = {
  144. .flags = 0,
  145. };
  146. static struct esdhc_soc_data esdhc_imx53_data = {
  147. .flags = ESDHC_FLAG_MULTIBLK_NO_INT,
  148. };
  149. static struct esdhc_soc_data usdhc_imx6q_data = {
  150. .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING,
  151. };
  152. static struct esdhc_soc_data usdhc_imx6sl_data = {
  153. .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
  154. | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536
  155. | ESDHC_FLAG_HS200,
  156. };
  157. static struct esdhc_soc_data usdhc_imx6sx_data = {
  158. .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
  159. | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200,
  160. };
  161. static struct esdhc_soc_data usdhc_imx7d_data = {
  162. .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
  163. | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
  164. | ESDHC_FLAG_HS400,
  165. };
  166. struct pltfm_imx_data {
  167. u32 scratchpad;
  168. struct pinctrl *pinctrl;
  169. struct pinctrl_state *pins_default;
  170. struct pinctrl_state *pins_100mhz;
  171. struct pinctrl_state *pins_200mhz;
  172. const struct esdhc_soc_data *socdata;
  173. struct esdhc_platform_data boarddata;
  174. struct clk *clk_ipg;
  175. struct clk *clk_ahb;
  176. struct clk *clk_per;
  177. unsigned int actual_clock;
  178. enum {
  179. NO_CMD_PENDING, /* no multiblock command pending */
  180. MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
  181. WAIT_FOR_INT, /* sent CMD12, waiting for response INT */
  182. } multiblock_status;
  183. u32 is_ddr;
  184. };
  185. static const struct platform_device_id imx_esdhc_devtype[] = {
  186. {
  187. .name = "sdhci-esdhc-imx25",
  188. .driver_data = (kernel_ulong_t) &esdhc_imx25_data,
  189. }, {
  190. .name = "sdhci-esdhc-imx35",
  191. .driver_data = (kernel_ulong_t) &esdhc_imx35_data,
  192. }, {
  193. .name = "sdhci-esdhc-imx51",
  194. .driver_data = (kernel_ulong_t) &esdhc_imx51_data,
  195. }, {
  196. /* sentinel */
  197. }
  198. };
  199. MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype);
  200. static const struct of_device_id imx_esdhc_dt_ids[] = {
  201. { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
  202. { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
  203. { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
  204. { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
  205. { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
  206. { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
  207. { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
  208. { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
  209. { /* sentinel */ }
  210. };
  211. MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
  212. static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
  213. {
  214. return data->socdata == &esdhc_imx25_data;
  215. }
  216. static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
  217. {
  218. return data->socdata == &esdhc_imx53_data;
  219. }
  220. static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
  221. {
  222. return data->socdata == &usdhc_imx6q_data;
  223. }
  224. static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
  225. {
  226. return !!(data->socdata->flags & ESDHC_FLAG_USDHC);
  227. }
  228. static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
  229. {
  230. void __iomem *base = host->ioaddr + (reg & ~0x3);
  231. u32 shift = (reg & 0x3) * 8;
  232. writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
  233. }
  234. static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
  235. {
  236. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  237. struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
  238. u32 val = readl(host->ioaddr + reg);
  239. if (unlikely(reg == SDHCI_PRESENT_STATE)) {
  240. u32 fsl_prss = val;
  241. /* save the least 20 bits */
  242. val = fsl_prss & 0x000FFFFF;
  243. /* move dat[0-3] bits */
  244. val |= (fsl_prss & 0x0F000000) >> 4;
  245. /* move cmd line bit */
  246. val |= (fsl_prss & 0x00800000) << 1;
  247. }
  248. if (unlikely(reg == SDHCI_CAPABILITIES)) {
  249. /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */
  250. if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
  251. val &= 0xffff0000;
  252. /* In FSL esdhc IC module, only bit20 is used to indicate the
  253. * ADMA2 capability of esdhc, but this bit is messed up on
  254. * some SOCs (e.g. on MX25, MX35 this bit is set, but they
  255. * don't actually support ADMA2). So set the BROKEN_ADMA
  256. * quirk on MX25/35 platforms.
  257. */
  258. if (val & SDHCI_CAN_DO_ADMA1) {
  259. val &= ~SDHCI_CAN_DO_ADMA1;
  260. val |= SDHCI_CAN_DO_ADMA2;
  261. }
  262. }
  263. if (unlikely(reg == SDHCI_CAPABILITIES_1)) {
  264. if (esdhc_is_usdhc(imx_data)) {
  265. if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
  266. val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;
  267. else
  268. /* imx6q/dl does not have cap_1 register, fake one */
  269. val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
  270. | SDHCI_SUPPORT_SDR50
  271. | SDHCI_USE_SDR50_TUNING
  272. | (SDHCI_TUNING_MODE_3 << SDHCI_RETUNING_MODE_SHIFT);
  273. if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
  274. val |= SDHCI_SUPPORT_HS400;
  275. /*
  276. * Do not advertise faster UHS modes if there are no
  277. * pinctrl states for 100MHz/200MHz.
  278. */
  279. if (IS_ERR_OR_NULL(imx_data->pins_100mhz) ||
  280. IS_ERR_OR_NULL(imx_data->pins_200mhz))
  281. val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50
  282. | SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);
  283. }
  284. }
  285. if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {
  286. val = 0;
  287. val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT;
  288. val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT;
  289. val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT;
  290. }
  291. if (unlikely(reg == SDHCI_INT_STATUS)) {
  292. if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
  293. val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
  294. val |= SDHCI_INT_ADMA_ERROR;
  295. }
  296. /*
  297. * mask off the interrupt we get in response to the manually
  298. * sent CMD12
  299. */
  300. if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
  301. ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
  302. val &= ~SDHCI_INT_RESPONSE;
  303. writel(SDHCI_INT_RESPONSE, host->ioaddr +
  304. SDHCI_INT_STATUS);
  305. imx_data->multiblock_status = NO_CMD_PENDING;
  306. }
  307. }
  308. return val;
  309. }
  310. static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
  311. {
  312. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  313. struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
  314. u32 data;
  315. if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE ||
  316. reg == SDHCI_INT_STATUS)) {
  317. if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) {
  318. /*
  319. * Clear and then set D3CD bit to avoid missing the
  320. * card interrupt. This is an eSDHC controller problem
  321. * so we need to apply the following workaround: clear
  322. * and set D3CD bit will make eSDHC re-sample the card
  323. * interrupt. In case a card interrupt was lost,
  324. * re-sample it by the following steps.
  325. */
  326. data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
  327. data &= ~ESDHC_CTRL_D3CD;
  328. writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
  329. data |= ESDHC_CTRL_D3CD;
  330. writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
  331. }
  332. if (val & SDHCI_INT_ADMA_ERROR) {
  333. val &= ~SDHCI_INT_ADMA_ERROR;
  334. val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
  335. }
  336. }
  337. if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
  338. && (reg == SDHCI_INT_STATUS)
  339. && (val & SDHCI_INT_DATA_END))) {
  340. u32 v;
  341. v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
  342. v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
  343. writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
  344. if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
  345. {
  346. /* send a manual CMD12 with RESPTYP=none */
  347. data = MMC_STOP_TRANSMISSION << 24 |
  348. SDHCI_CMD_ABORTCMD << 16;
  349. writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
  350. imx_data->multiblock_status = WAIT_FOR_INT;
  351. }
  352. }
  353. writel(val, host->ioaddr + reg);
  354. }
  355. static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
  356. {
  357. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  358. struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
  359. u16 ret = 0;
  360. u32 val;
  361. if (unlikely(reg == SDHCI_HOST_VERSION)) {
  362. reg ^= 2;
  363. if (esdhc_is_usdhc(imx_data)) {
  364. /*
  365. * The usdhc register returns a wrong host version.
  366. * Correct it here.
  367. */
  368. return SDHCI_SPEC_300;
  369. }
  370. }
  371. if (unlikely(reg == SDHCI_HOST_CONTROL2)) {
  372. val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
  373. if (val & ESDHC_VENDOR_SPEC_VSELECT)
  374. ret |= SDHCI_CTRL_VDD_180;
  375. if (esdhc_is_usdhc(imx_data)) {
  376. if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
  377. val = readl(host->ioaddr + ESDHC_MIX_CTRL);
  378. else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
  379. /* the std tuning bits is in ACMD12_ERR for imx6sl */
  380. val = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
  381. }
  382. if (val & ESDHC_MIX_CTRL_EXE_TUNE)
  383. ret |= SDHCI_CTRL_EXEC_TUNING;
  384. if (val & ESDHC_MIX_CTRL_SMPCLK_SEL)
  385. ret |= SDHCI_CTRL_TUNED_CLK;
  386. ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
  387. return ret;
  388. }
  389. if (unlikely(reg == SDHCI_TRANSFER_MODE)) {
  390. if (esdhc_is_usdhc(imx_data)) {
  391. u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
  392. ret = m & ESDHC_MIX_CTRL_SDHCI_MASK;
  393. /* Swap AC23 bit */
  394. if (m & ESDHC_MIX_CTRL_AC23EN) {
  395. ret &= ~ESDHC_MIX_CTRL_AC23EN;
  396. ret |= SDHCI_TRNS_AUTO_CMD23;
  397. }
  398. } else {
  399. ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
  400. }
  401. return ret;
  402. }
  403. return readw(host->ioaddr + reg);
  404. }
  405. static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
  406. {
  407. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  408. struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
  409. u32 new_val = 0;
  410. switch (reg) {
  411. case SDHCI_CLOCK_CONTROL:
  412. new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
  413. if (val & SDHCI_CLOCK_CARD_EN)
  414. new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
  415. else
  416. new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
  417. writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
  418. return;
  419. case SDHCI_HOST_CONTROL2:
  420. new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
  421. if (val & SDHCI_CTRL_VDD_180)
  422. new_val |= ESDHC_VENDOR_SPEC_VSELECT;
  423. else
  424. new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
  425. writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
  426. if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
  427. new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
  428. if (val & SDHCI_CTRL_TUNED_CLK) {
  429. new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL;
  430. new_val |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
  431. } else {
  432. new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
  433. new_val &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
  434. }
  435. writel(new_val , host->ioaddr + ESDHC_MIX_CTRL);
  436. } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
  437. u32 v = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
  438. u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
  439. if (val & SDHCI_CTRL_TUNED_CLK) {
  440. v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
  441. } else {
  442. v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
  443. m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
  444. m &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
  445. }
  446. if (val & SDHCI_CTRL_EXEC_TUNING) {
  447. v |= ESDHC_MIX_CTRL_EXE_TUNE;
  448. m |= ESDHC_MIX_CTRL_FBCLK_SEL;
  449. m |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
  450. } else {
  451. v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
  452. }
  453. writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
  454. writel(m, host->ioaddr + ESDHC_MIX_CTRL);
  455. }
  456. return;
  457. case SDHCI_TRANSFER_MODE:
  458. if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
  459. && (host->cmd->opcode == SD_IO_RW_EXTENDED)
  460. && (host->cmd->data->blocks > 1)
  461. && (host->cmd->data->flags & MMC_DATA_READ)) {
  462. u32 v;
  463. v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
  464. v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
  465. writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
  466. }
  467. if (esdhc_is_usdhc(imx_data)) {
  468. u32 wml;
  469. u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
  470. /* Swap AC23 bit */
  471. if (val & SDHCI_TRNS_AUTO_CMD23) {
  472. val &= ~SDHCI_TRNS_AUTO_CMD23;
  473. val |= ESDHC_MIX_CTRL_AC23EN;
  474. }
  475. m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
  476. writel(m, host->ioaddr + ESDHC_MIX_CTRL);
  477. /* Set watermark levels for PIO access to maximum value
  478. * (128 words) to accommodate full 512 bytes buffer.
  479. * For DMA access restore the levels to default value.
  480. */
  481. m = readl(host->ioaddr + ESDHC_WTMK_LVL);
  482. if (val & SDHCI_TRNS_DMA)
  483. wml = ESDHC_WTMK_LVL_WML_VAL_DEF;
  484. else
  485. wml = ESDHC_WTMK_LVL_WML_VAL_MAX;
  486. m &= ~(ESDHC_WTMK_LVL_RD_WML_MASK |
  487. ESDHC_WTMK_LVL_WR_WML_MASK);
  488. m |= (wml << ESDHC_WTMK_LVL_RD_WML_SHIFT) |
  489. (wml << ESDHC_WTMK_LVL_WR_WML_SHIFT);
  490. writel(m, host->ioaddr + ESDHC_WTMK_LVL);
  491. } else {
  492. /*
  493. * Postpone this write, we must do it together with a
  494. * command write that is down below.
  495. */
  496. imx_data->scratchpad = val;
  497. }
  498. return;
  499. case SDHCI_COMMAND:
  500. if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
  501. val |= SDHCI_CMD_ABORTCMD;
  502. if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
  503. (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
  504. imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
  505. if (esdhc_is_usdhc(imx_data))
  506. writel(val << 16,
  507. host->ioaddr + SDHCI_TRANSFER_MODE);
  508. else
  509. writel(val << 16 | imx_data->scratchpad,
  510. host->ioaddr + SDHCI_TRANSFER_MODE);
  511. return;
  512. case SDHCI_BLOCK_SIZE:
  513. val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
  514. break;
  515. }
  516. esdhc_clrset_le(host, 0xffff, val, reg);
  517. }
  518. static u8 esdhc_readb_le(struct sdhci_host *host, int reg)
  519. {
  520. u8 ret;
  521. u32 val;
  522. switch (reg) {
  523. case SDHCI_HOST_CONTROL:
  524. val = readl(host->ioaddr + reg);
  525. ret = val & SDHCI_CTRL_LED;
  526. ret |= (val >> 5) & SDHCI_CTRL_DMA_MASK;
  527. ret |= (val & ESDHC_CTRL_4BITBUS);
  528. ret |= (val & ESDHC_CTRL_8BITBUS) << 3;
  529. return ret;
  530. }
  531. return readb(host->ioaddr + reg);
  532. }
  533. static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
  534. {
  535. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  536. struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
  537. u32 new_val = 0;
  538. u32 mask;
  539. switch (reg) {
  540. case SDHCI_POWER_CONTROL:
  541. /*
  542. * FSL put some DMA bits here
  543. * If your board has a regulator, code should be here
  544. */
  545. return;
  546. case SDHCI_HOST_CONTROL:
  547. /* FSL messed up here, so we need to manually compose it. */
  548. new_val = val & SDHCI_CTRL_LED;
  549. /* ensure the endianness */
  550. new_val |= ESDHC_HOST_CONTROL_LE;
  551. /* bits 8&9 are reserved on mx25 */
  552. if (!is_imx25_esdhc(imx_data)) {
  553. /* DMA mode bits are shifted */
  554. new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
  555. }
  556. /*
  557. * Do not touch buswidth bits here. This is done in
  558. * esdhc_pltfm_bus_width.
  559. * Do not touch the D3CD bit either which is used for the
  560. * SDIO interrupt erratum workaround.
  561. */
  562. mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
  563. esdhc_clrset_le(host, mask, new_val, reg);
  564. return;
  565. case SDHCI_SOFTWARE_RESET:
  566. if (val & SDHCI_RESET_DATA)
  567. new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL);
  568. break;
  569. }
  570. esdhc_clrset_le(host, 0xff, val, reg);
  571. if (reg == SDHCI_SOFTWARE_RESET) {
  572. if (val & SDHCI_RESET_ALL) {
  573. /*
  574. * The esdhc has a design violation to SDHC spec which
  575. * tells that software reset should not affect card
  576. * detection circuit. But esdhc clears its SYSCTL
  577. * register bits [0..2] during the software reset. This
  578. * will stop those clocks that card detection circuit
  579. * relies on. To work around it, we turn the clocks on
  580. * back to keep card detection circuit functional.
  581. */
  582. esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
  583. /*
  584. * The reset on usdhc fails to clear MIX_CTRL register.
  585. * Do it manually here.
  586. */
  587. if (esdhc_is_usdhc(imx_data)) {
  588. /*
  589. * the tuning bits should be kept during reset
  590. */
  591. new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
  592. writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK,
  593. host->ioaddr + ESDHC_MIX_CTRL);
  594. imx_data->is_ddr = 0;
  595. }
  596. } else if (val & SDHCI_RESET_DATA) {
  597. /*
  598. * The eSDHC DAT line software reset clears at least the
  599. * data transfer width on i.MX25, so make sure that the
  600. * Host Control register is unaffected.
  601. */
  602. esdhc_clrset_le(host, 0xff, new_val,
  603. SDHCI_HOST_CONTROL);
  604. }
  605. }
  606. }
  607. static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
  608. {
  609. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  610. return pltfm_host->clock;
  611. }
  612. static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
  613. {
  614. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  615. return pltfm_host->clock / 256 / 16;
  616. }
  617. static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
  618. unsigned int clock)
  619. {
  620. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  621. struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
  622. unsigned int host_clock = pltfm_host->clock;
  623. int ddr_pre_div = imx_data->is_ddr ? 2 : 1;
  624. int pre_div = 1;
  625. int div = 1;
  626. u32 temp, val;
  627. if (esdhc_is_usdhc(imx_data)) {
  628. val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
  629. writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
  630. host->ioaddr + ESDHC_VENDOR_SPEC);
  631. }
  632. if (clock == 0) {
  633. host->mmc->actual_clock = 0;
  634. return;
  635. }
  636. /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
  637. if (is_imx53_esdhc(imx_data)) {
  638. /*
  639. * According to the i.MX53 reference manual, if DLLCTRL[10] can
  640. * be set, then the controller is eSDHCv3, else it is eSDHCv2.
  641. */
  642. val = readl(host->ioaddr + ESDHC_DLL_CTRL);
  643. writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL);
  644. temp = readl(host->ioaddr + ESDHC_DLL_CTRL);
  645. writel(val, host->ioaddr + ESDHC_DLL_CTRL);
  646. if (temp & BIT(10))
  647. pre_div = 2;
  648. }
  649. temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
  650. temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
  651. | ESDHC_CLOCK_MASK);
  652. sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
  653. while (host_clock / (16 * pre_div * ddr_pre_div) > clock &&
  654. pre_div < 256)
  655. pre_div *= 2;
  656. while (host_clock / (div * pre_div * ddr_pre_div) > clock && div < 16)
  657. div++;
  658. host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div);
  659. dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
  660. clock, host->mmc->actual_clock);
  661. pre_div >>= 1;
  662. div--;
  663. temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
  664. temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
  665. | (div << ESDHC_DIVIDER_SHIFT)
  666. | (pre_div << ESDHC_PREDIV_SHIFT));
  667. sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
  668. if (esdhc_is_usdhc(imx_data)) {
  669. val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
  670. writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
  671. host->ioaddr + ESDHC_VENDOR_SPEC);
  672. }
  673. mdelay(1);
  674. }
  675. static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
  676. {
  677. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  678. struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
  679. struct esdhc_platform_data *boarddata = &imx_data->boarddata;
  680. switch (boarddata->wp_type) {
  681. case ESDHC_WP_GPIO:
  682. return mmc_gpio_get_ro(host->mmc);
  683. case ESDHC_WP_CONTROLLER:
  684. return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
  685. SDHCI_WRITE_PROTECT);
  686. case ESDHC_WP_NONE:
  687. break;
  688. }
  689. return -ENOSYS;
  690. }
  691. static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
  692. {
  693. u32 ctrl;
  694. switch (width) {
  695. case MMC_BUS_WIDTH_8:
  696. ctrl = ESDHC_CTRL_8BITBUS;
  697. break;
  698. case MMC_BUS_WIDTH_4:
  699. ctrl = ESDHC_CTRL_4BITBUS;
  700. break;
  701. default:
  702. ctrl = 0;
  703. break;
  704. }
  705. esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
  706. SDHCI_HOST_CONTROL);
  707. }
  708. static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
  709. {
  710. u32 reg;
  711. /* FIXME: delay a bit for card to be ready for next tuning due to errors */
  712. mdelay(1);
  713. reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
  714. reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
  715. ESDHC_MIX_CTRL_FBCLK_SEL;
  716. writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
  717. writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
  718. dev_dbg(mmc_dev(host->mmc),
  719. "tuning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
  720. val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
  721. }
  722. static void esdhc_post_tuning(struct sdhci_host *host)
  723. {
  724. u32 reg;
  725. reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
  726. reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
  727. reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
  728. writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
  729. }
  730. static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
  731. {
  732. int min, max, avg, ret;
  733. /* find the mininum delay first which can pass tuning */
  734. min = ESDHC_TUNE_CTRL_MIN;
  735. while (min < ESDHC_TUNE_CTRL_MAX) {
  736. esdhc_prepare_tuning(host, min);
  737. if (!mmc_send_tuning(host->mmc, opcode, NULL))
  738. break;
  739. min += ESDHC_TUNE_CTRL_STEP;
  740. }
  741. /* find the maxinum delay which can not pass tuning */
  742. max = min + ESDHC_TUNE_CTRL_STEP;
  743. while (max < ESDHC_TUNE_CTRL_MAX) {
  744. esdhc_prepare_tuning(host, max);
  745. if (mmc_send_tuning(host->mmc, opcode, NULL)) {
  746. max -= ESDHC_TUNE_CTRL_STEP;
  747. break;
  748. }
  749. max += ESDHC_TUNE_CTRL_STEP;
  750. }
  751. /* use average delay to get the best timing */
  752. avg = (min + max) / 2;
  753. esdhc_prepare_tuning(host, avg);
  754. ret = mmc_send_tuning(host->mmc, opcode, NULL);
  755. esdhc_post_tuning(host);
  756. dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n",
  757. ret ? "failed" : "passed", avg, ret);
  758. return ret;
  759. }
  760. static int esdhc_change_pinstate(struct sdhci_host *host,
  761. unsigned int uhs)
  762. {
  763. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  764. struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
  765. struct pinctrl_state *pinctrl;
  766. dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);
  767. if (IS_ERR(imx_data->pinctrl) ||
  768. IS_ERR(imx_data->pins_default) ||
  769. IS_ERR(imx_data->pins_100mhz) ||
  770. IS_ERR(imx_data->pins_200mhz))
  771. return -EINVAL;
  772. switch (uhs) {
  773. case MMC_TIMING_UHS_SDR50:
  774. case MMC_TIMING_UHS_DDR50:
  775. pinctrl = imx_data->pins_100mhz;
  776. break;
  777. case MMC_TIMING_UHS_SDR104:
  778. case MMC_TIMING_MMC_HS200:
  779. case MMC_TIMING_MMC_HS400:
  780. pinctrl = imx_data->pins_200mhz;
  781. break;
  782. default:
  783. /* back to default state for other legacy timing */
  784. pinctrl = imx_data->pins_default;
  785. }
  786. return pinctrl_select_state(imx_data->pinctrl, pinctrl);
  787. }
  788. /*
  789. * For HS400 eMMC, there is a data_strobe line. This signal is generated
  790. * by the device and used for data output and CRC status response output
  791. * in HS400 mode. The frequency of this signal follows the frequency of
  792. * CLK generated by host. The host receives the data which is aligned to the
  793. * edge of data_strobe line. Due to the time delay between CLK line and
  794. * data_strobe line, if the delay time is larger than one clock cycle,
  795. * then CLK and data_strobe line will be misaligned, read error shows up.
  796. * So when the CLK is higher than 100MHz, each clock cycle is short enough,
  797. * host should configure the delay target.
  798. */
  799. static void esdhc_set_strobe_dll(struct sdhci_host *host)
  800. {
  801. u32 v;
  802. if (host->mmc->actual_clock > ESDHC_STROBE_DLL_CLK_FREQ) {
  803. /* disable clock before enabling strobe dll */
  804. writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) &
  805. ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
  806. host->ioaddr + ESDHC_VENDOR_SPEC);
  807. /* force a reset on strobe dll */
  808. writel(ESDHC_STROBE_DLL_CTRL_RESET,
  809. host->ioaddr + ESDHC_STROBE_DLL_CTRL);
  810. /*
  811. * enable strobe dll ctrl and adjust the delay target
  812. * for the uSDHC loopback read clock
  813. */
  814. v = ESDHC_STROBE_DLL_CTRL_ENABLE |
  815. (7 << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
  816. writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
  817. /* wait 1us to make sure strobe dll status register stable */
  818. udelay(1);
  819. v = readl(host->ioaddr + ESDHC_STROBE_DLL_STATUS);
  820. if (!(v & ESDHC_STROBE_DLL_STS_REF_LOCK))
  821. dev_warn(mmc_dev(host->mmc),
  822. "warning! HS400 strobe DLL status REF not lock!\n");
  823. if (!(v & ESDHC_STROBE_DLL_STS_SLV_LOCK))
  824. dev_warn(mmc_dev(host->mmc),
  825. "warning! HS400 strobe DLL status SLV not lock!\n");
  826. }
  827. }
  828. static void esdhc_reset_tuning(struct sdhci_host *host)
  829. {
  830. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  831. struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
  832. u32 ctrl;
  833. /* Reset the tuning circuit */
  834. if (esdhc_is_usdhc(imx_data)) {
  835. if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
  836. ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL);
  837. ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
  838. ctrl &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
  839. writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL);
  840. writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
  841. } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
  842. ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
  843. ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
  844. writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
  845. }
  846. }
  847. }
  848. static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
  849. {
  850. u32 m;
  851. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  852. struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
  853. struct esdhc_platform_data *boarddata = &imx_data->boarddata;
  854. /* disable ddr mode and disable HS400 mode */
  855. m = readl(host->ioaddr + ESDHC_MIX_CTRL);
  856. m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN);
  857. imx_data->is_ddr = 0;
  858. switch (timing) {
  859. case MMC_TIMING_UHS_SDR12:
  860. case MMC_TIMING_UHS_SDR25:
  861. case MMC_TIMING_UHS_SDR50:
  862. case MMC_TIMING_UHS_SDR104:
  863. case MMC_TIMING_MMC_HS:
  864. case MMC_TIMING_MMC_HS200:
  865. writel(m, host->ioaddr + ESDHC_MIX_CTRL);
  866. break;
  867. case MMC_TIMING_UHS_DDR50:
  868. case MMC_TIMING_MMC_DDR52:
  869. m |= ESDHC_MIX_CTRL_DDREN;
  870. writel(m, host->ioaddr + ESDHC_MIX_CTRL);
  871. imx_data->is_ddr = 1;
  872. if (boarddata->delay_line) {
  873. u32 v;
  874. v = boarddata->delay_line <<
  875. ESDHC_DLL_OVERRIDE_VAL_SHIFT |
  876. (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT);
  877. if (is_imx53_esdhc(imx_data))
  878. v <<= 1;
  879. writel(v, host->ioaddr + ESDHC_DLL_CTRL);
  880. }
  881. break;
  882. case MMC_TIMING_MMC_HS400:
  883. m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN;
  884. writel(m, host->ioaddr + ESDHC_MIX_CTRL);
  885. imx_data->is_ddr = 1;
  886. /* update clock after enable DDR for strobe DLL lock */
  887. host->ops->set_clock(host, host->clock);
  888. esdhc_set_strobe_dll(host);
  889. break;
  890. case MMC_TIMING_LEGACY:
  891. default:
  892. esdhc_reset_tuning(host);
  893. break;
  894. }
  895. esdhc_change_pinstate(host, timing);
  896. }
  897. static void esdhc_reset(struct sdhci_host *host, u8 mask)
  898. {
  899. sdhci_reset(host, mask);
  900. sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
  901. sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
  902. }
  903. static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host)
  904. {
  905. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  906. struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
  907. /* Doc Erratum: the uSDHC actual maximum timeout count is 1 << 29 */
  908. return esdhc_is_usdhc(imx_data) ? 1 << 29 : 1 << 27;
  909. }
  910. static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
  911. {
  912. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  913. struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
  914. /* use maximum timeout counter */
  915. esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK,
  916. esdhc_is_usdhc(imx_data) ? 0xF : 0xE,
  917. SDHCI_TIMEOUT_CONTROL);
  918. }
  919. static struct sdhci_ops sdhci_esdhc_ops = {
  920. .read_l = esdhc_readl_le,
  921. .read_w = esdhc_readw_le,
  922. .read_b = esdhc_readb_le,
  923. .write_l = esdhc_writel_le,
  924. .write_w = esdhc_writew_le,
  925. .write_b = esdhc_writeb_le,
  926. .set_clock = esdhc_pltfm_set_clock,
  927. .get_max_clock = esdhc_pltfm_get_max_clock,
  928. .get_min_clock = esdhc_pltfm_get_min_clock,
  929. .get_max_timeout_count = esdhc_get_max_timeout_count,
  930. .get_ro = esdhc_pltfm_get_ro,
  931. .set_timeout = esdhc_set_timeout,
  932. .set_bus_width = esdhc_pltfm_set_bus_width,
  933. .set_uhs_signaling = esdhc_set_uhs_signaling,
  934. .reset = esdhc_reset,
  935. };
  936. static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
  937. .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
  938. | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
  939. | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
  940. | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
  941. .ops = &sdhci_esdhc_ops,
  942. };
  943. static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host)
  944. {
  945. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  946. struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
  947. int tmp;
  948. if (esdhc_is_usdhc(imx_data)) {
  949. /*
  950. * The imx6q ROM code will change the default watermark
  951. * level setting to something insane. Change it back here.
  952. */
  953. writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL);
  954. /*
  955. * ROM code will change the bit burst_length_enable setting
  956. * to zero if this usdhc is chosen to boot system. Change
  957. * it back here, otherwise it will impact the performance a
  958. * lot. This bit is used to enable/disable the burst length
  959. * for the external AHB2AXI bridge. It's useful especially
  960. * for INCR transfer because without burst length indicator,
  961. * the AHB2AXI bridge does not know the burst length in
  962. * advance. And without burst length indicator, AHB INCR
  963. * transfer can only be converted to singles on the AXI side.
  964. */
  965. writel(readl(host->ioaddr + SDHCI_HOST_CONTROL)
  966. | ESDHC_BURST_LEN_EN_INCR,
  967. host->ioaddr + SDHCI_HOST_CONTROL);
  968. /*
  969. * erratum ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
  970. * TO1.1, it's harmless for MX6SL
  971. */
  972. writel(readl(host->ioaddr + 0x6c) & ~BIT(7),
  973. host->ioaddr + 0x6c);
  974. /* disable DLL_CTRL delay line settings */
  975. writel(0x0, host->ioaddr + ESDHC_DLL_CTRL);
  976. if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
  977. tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
  978. tmp |= ESDHC_STD_TUNING_EN |
  979. ESDHC_TUNING_START_TAP_DEFAULT;
  980. if (imx_data->boarddata.tuning_start_tap) {
  981. tmp &= ~ESDHC_TUNING_START_TAP_MASK;
  982. tmp |= imx_data->boarddata.tuning_start_tap;
  983. }
  984. if (imx_data->boarddata.tuning_step) {
  985. tmp &= ~ESDHC_TUNING_STEP_MASK;
  986. tmp |= imx_data->boarddata.tuning_step
  987. << ESDHC_TUNING_STEP_SHIFT;
  988. }
  989. writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
  990. }
  991. }
  992. }
  993. #ifdef CONFIG_OF
  994. static int
  995. sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
  996. struct sdhci_host *host,
  997. struct pltfm_imx_data *imx_data)
  998. {
  999. struct device_node *np = pdev->dev.of_node;
  1000. struct esdhc_platform_data *boarddata = &imx_data->boarddata;
  1001. int ret;
  1002. if (of_get_property(np, "fsl,wp-controller", NULL))
  1003. boarddata->wp_type = ESDHC_WP_CONTROLLER;
  1004. boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
  1005. if (gpio_is_valid(boarddata->wp_gpio))
  1006. boarddata->wp_type = ESDHC_WP_GPIO;
  1007. of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step);
  1008. of_property_read_u32(np, "fsl,tuning-start-tap",
  1009. &boarddata->tuning_start_tap);
  1010. if (of_find_property(np, "no-1-8-v", NULL))
  1011. host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
  1012. if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line))
  1013. boarddata->delay_line = 0;
  1014. mmc_of_parse_voltage(np, &host->ocr_mask);
  1015. if (esdhc_is_usdhc(imx_data) && !IS_ERR(imx_data->pins_default)) {
  1016. imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
  1017. ESDHC_PINCTRL_STATE_100MHZ);
  1018. imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
  1019. ESDHC_PINCTRL_STATE_200MHZ);
  1020. }
  1021. /* call to generic mmc_of_parse to support additional capabilities */
  1022. ret = mmc_of_parse(host->mmc);
  1023. if (ret)
  1024. return ret;
  1025. if (mmc_gpio_get_cd(host->mmc) >= 0)
  1026. host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
  1027. return 0;
  1028. }
  1029. #else
  1030. static inline int
  1031. sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
  1032. struct sdhci_host *host,
  1033. struct pltfm_imx_data *imx_data)
  1034. {
  1035. return -ENODEV;
  1036. }
  1037. #endif
  1038. static int sdhci_esdhc_imx_probe_nondt(struct platform_device *pdev,
  1039. struct sdhci_host *host,
  1040. struct pltfm_imx_data *imx_data)
  1041. {
  1042. struct esdhc_platform_data *boarddata = &imx_data->boarddata;
  1043. int err;
  1044. if (!host->mmc->parent->platform_data) {
  1045. dev_err(mmc_dev(host->mmc), "no board data!\n");
  1046. return -EINVAL;
  1047. }
  1048. imx_data->boarddata = *((struct esdhc_platform_data *)
  1049. host->mmc->parent->platform_data);
  1050. /* write_protect */
  1051. if (boarddata->wp_type == ESDHC_WP_GPIO) {
  1052. err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio);
  1053. if (err) {
  1054. dev_err(mmc_dev(host->mmc),
  1055. "failed to request write-protect gpio!\n");
  1056. return err;
  1057. }
  1058. host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
  1059. }
  1060. /* card_detect */
  1061. switch (boarddata->cd_type) {
  1062. case ESDHC_CD_GPIO:
  1063. err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0);
  1064. if (err) {
  1065. dev_err(mmc_dev(host->mmc),
  1066. "failed to request card-detect gpio!\n");
  1067. return err;
  1068. }
  1069. /* fall through */
  1070. case ESDHC_CD_CONTROLLER:
  1071. /* we have a working card_detect back */
  1072. host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
  1073. break;
  1074. case ESDHC_CD_PERMANENT:
  1075. host->mmc->caps |= MMC_CAP_NONREMOVABLE;
  1076. break;
  1077. case ESDHC_CD_NONE:
  1078. break;
  1079. }
  1080. switch (boarddata->max_bus_width) {
  1081. case 8:
  1082. host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA;
  1083. break;
  1084. case 4:
  1085. host->mmc->caps |= MMC_CAP_4_BIT_DATA;
  1086. break;
  1087. case 1:
  1088. default:
  1089. host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
  1090. break;
  1091. }
  1092. return 0;
  1093. }
  1094. static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
  1095. {
  1096. const struct of_device_id *of_id =
  1097. of_match_device(imx_esdhc_dt_ids, &pdev->dev);
  1098. struct sdhci_pltfm_host *pltfm_host;
  1099. struct sdhci_host *host;
  1100. int err;
  1101. struct pltfm_imx_data *imx_data;
  1102. host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata,
  1103. sizeof(*imx_data));
  1104. if (IS_ERR(host))
  1105. return PTR_ERR(host);
  1106. pltfm_host = sdhci_priv(host);
  1107. imx_data = sdhci_pltfm_priv(pltfm_host);
  1108. imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *)
  1109. pdev->id_entry->driver_data;
  1110. imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
  1111. if (IS_ERR(imx_data->clk_ipg)) {
  1112. err = PTR_ERR(imx_data->clk_ipg);
  1113. goto free_sdhci;
  1114. }
  1115. imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
  1116. if (IS_ERR(imx_data->clk_ahb)) {
  1117. err = PTR_ERR(imx_data->clk_ahb);
  1118. goto free_sdhci;
  1119. }
  1120. imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
  1121. if (IS_ERR(imx_data->clk_per)) {
  1122. err = PTR_ERR(imx_data->clk_per);
  1123. goto free_sdhci;
  1124. }
  1125. pltfm_host->clk = imx_data->clk_per;
  1126. pltfm_host->clock = clk_get_rate(pltfm_host->clk);
  1127. err = clk_prepare_enable(imx_data->clk_per);
  1128. if (err)
  1129. goto free_sdhci;
  1130. err = clk_prepare_enable(imx_data->clk_ipg);
  1131. if (err)
  1132. goto disable_per_clk;
  1133. err = clk_prepare_enable(imx_data->clk_ahb);
  1134. if (err)
  1135. goto disable_ipg_clk;
  1136. imx_data->pinctrl = devm_pinctrl_get(&pdev->dev);
  1137. if (IS_ERR(imx_data->pinctrl)) {
  1138. err = PTR_ERR(imx_data->pinctrl);
  1139. goto disable_ahb_clk;
  1140. }
  1141. imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl,
  1142. PINCTRL_STATE_DEFAULT);
  1143. if (IS_ERR(imx_data->pins_default))
  1144. dev_warn(mmc_dev(host->mmc), "could not get default state\n");
  1145. if (esdhc_is_usdhc(imx_data)) {
  1146. host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
  1147. host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;
  1148. if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200))
  1149. host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
  1150. /* clear tuning bits in case ROM has set it already */
  1151. writel(0x0, host->ioaddr + ESDHC_MIX_CTRL);
  1152. writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
  1153. writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
  1154. }
  1155. if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
  1156. sdhci_esdhc_ops.platform_execute_tuning =
  1157. esdhc_executing_tuning;
  1158. if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
  1159. host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
  1160. if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
  1161. host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400;
  1162. if (of_id)
  1163. err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data);
  1164. else
  1165. err = sdhci_esdhc_imx_probe_nondt(pdev, host, imx_data);
  1166. if (err)
  1167. goto disable_ahb_clk;
  1168. sdhci_esdhc_imx_hwinit(host);
  1169. err = sdhci_add_host(host);
  1170. if (err)
  1171. goto disable_ahb_clk;
  1172. pm_runtime_set_active(&pdev->dev);
  1173. pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
  1174. pm_runtime_use_autosuspend(&pdev->dev);
  1175. pm_suspend_ignore_children(&pdev->dev, 1);
  1176. pm_runtime_enable(&pdev->dev);
  1177. return 0;
  1178. disable_ahb_clk:
  1179. clk_disable_unprepare(imx_data->clk_ahb);
  1180. disable_ipg_clk:
  1181. clk_disable_unprepare(imx_data->clk_ipg);
  1182. disable_per_clk:
  1183. clk_disable_unprepare(imx_data->clk_per);
  1184. free_sdhci:
  1185. sdhci_pltfm_free(pdev);
  1186. return err;
  1187. }
  1188. static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
  1189. {
  1190. struct sdhci_host *host = platform_get_drvdata(pdev);
  1191. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  1192. struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
  1193. int dead;
  1194. pm_runtime_get_sync(&pdev->dev);
  1195. dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
  1196. pm_runtime_disable(&pdev->dev);
  1197. pm_runtime_put_noidle(&pdev->dev);
  1198. sdhci_remove_host(host, dead);
  1199. clk_disable_unprepare(imx_data->clk_per);
  1200. clk_disable_unprepare(imx_data->clk_ipg);
  1201. clk_disable_unprepare(imx_data->clk_ahb);
  1202. sdhci_pltfm_free(pdev);
  1203. return 0;
  1204. }
  1205. #ifdef CONFIG_PM_SLEEP
  1206. static int sdhci_esdhc_suspend(struct device *dev)
  1207. {
  1208. struct sdhci_host *host = dev_get_drvdata(dev);
  1209. if (host->tuning_mode != SDHCI_TUNING_MODE_3)
  1210. mmc_retune_needed(host->mmc);
  1211. return sdhci_suspend_host(host);
  1212. }
  1213. static int sdhci_esdhc_resume(struct device *dev)
  1214. {
  1215. struct sdhci_host *host = dev_get_drvdata(dev);
  1216. /* re-initialize hw state in case it's lost in low power mode */
  1217. sdhci_esdhc_imx_hwinit(host);
  1218. return sdhci_resume_host(host);
  1219. }
  1220. #endif
  1221. #ifdef CONFIG_PM
  1222. static int sdhci_esdhc_runtime_suspend(struct device *dev)
  1223. {
  1224. struct sdhci_host *host = dev_get_drvdata(dev);
  1225. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  1226. struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
  1227. int ret;
  1228. ret = sdhci_runtime_suspend_host(host);
  1229. if (ret)
  1230. return ret;
  1231. if (host->tuning_mode != SDHCI_TUNING_MODE_3)
  1232. mmc_retune_needed(host->mmc);
  1233. if (!sdhci_sdio_irq_enabled(host)) {
  1234. imx_data->actual_clock = host->mmc->actual_clock;
  1235. esdhc_pltfm_set_clock(host, 0);
  1236. clk_disable_unprepare(imx_data->clk_per);
  1237. clk_disable_unprepare(imx_data->clk_ipg);
  1238. }
  1239. clk_disable_unprepare(imx_data->clk_ahb);
  1240. return ret;
  1241. }
  1242. static int sdhci_esdhc_runtime_resume(struct device *dev)
  1243. {
  1244. struct sdhci_host *host = dev_get_drvdata(dev);
  1245. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  1246. struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
  1247. int err;
  1248. err = clk_prepare_enable(imx_data->clk_ahb);
  1249. if (err)
  1250. return err;
  1251. if (!sdhci_sdio_irq_enabled(host)) {
  1252. err = clk_prepare_enable(imx_data->clk_per);
  1253. if (err)
  1254. goto disable_ahb_clk;
  1255. err = clk_prepare_enable(imx_data->clk_ipg);
  1256. if (err)
  1257. goto disable_per_clk;
  1258. esdhc_pltfm_set_clock(host, imx_data->actual_clock);
  1259. }
  1260. err = sdhci_runtime_resume_host(host);
  1261. if (err)
  1262. goto disable_ipg_clk;
  1263. return 0;
  1264. disable_ipg_clk:
  1265. if (!sdhci_sdio_irq_enabled(host))
  1266. clk_disable_unprepare(imx_data->clk_ipg);
  1267. disable_per_clk:
  1268. if (!sdhci_sdio_irq_enabled(host))
  1269. clk_disable_unprepare(imx_data->clk_per);
  1270. disable_ahb_clk:
  1271. clk_disable_unprepare(imx_data->clk_ahb);
  1272. return err;
  1273. }
  1274. #endif
  1275. static const struct dev_pm_ops sdhci_esdhc_pmops = {
  1276. SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume)
  1277. SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend,
  1278. sdhci_esdhc_runtime_resume, NULL)
  1279. };
  1280. static struct platform_driver sdhci_esdhc_imx_driver = {
  1281. .driver = {
  1282. .name = "sdhci-esdhc-imx",
  1283. .of_match_table = imx_esdhc_dt_ids,
  1284. .pm = &sdhci_esdhc_pmops,
  1285. },
  1286. .id_table = imx_esdhc_devtype,
  1287. .probe = sdhci_esdhc_imx_probe,
  1288. .remove = sdhci_esdhc_imx_remove,
  1289. };
  1290. module_platform_driver(sdhci_esdhc_imx_driver);
  1291. MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
  1292. MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");
  1293. MODULE_LICENSE("GPL v2");