sdhci-pci-o2micro.c 14 KB

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  1. /*
  2. * Copyright (C) 2013 BayHub Technology Ltd.
  3. *
  4. * Authors: Peter Guo <peter.guo@bayhubtech.com>
  5. * Adam Lee <adam.lee@canonical.com>
  6. * Ernest Zhang <ernest.zhang@bayhubtech.com>
  7. *
  8. * This software is licensed under the terms of the GNU General Public
  9. * License version 2, as published by the Free Software Foundation, and
  10. * may be copied, distributed, and modified under those terms.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. */
  18. #include <linux/pci.h>
  19. #include <linux/mmc/host.h>
  20. #include <linux/mmc/mmc.h>
  21. #include <linux/delay.h>
  22. #include "sdhci.h"
  23. #include "sdhci-pci.h"
  24. /*
  25. * O2Micro device registers
  26. */
  27. #define O2_SD_MISC_REG5 0x64
  28. #define O2_SD_LD0_CTRL 0x68
  29. #define O2_SD_DEV_CTRL 0x88
  30. #define O2_SD_LOCK_WP 0xD3
  31. #define O2_SD_TEST_REG 0xD4
  32. #define O2_SD_FUNC_REG0 0xDC
  33. #define O2_SD_MULTI_VCC3V 0xEE
  34. #define O2_SD_CLKREQ 0xEC
  35. #define O2_SD_CAPS 0xE0
  36. #define O2_SD_ADMA1 0xE2
  37. #define O2_SD_ADMA2 0xE7
  38. #define O2_SD_INF_MOD 0xF1
  39. #define O2_SD_MISC_CTRL4 0xFC
  40. #define O2_SD_TUNING_CTRL 0x300
  41. #define O2_SD_PLL_SETTING 0x304
  42. #define O2_SD_MISC_SETTING 0x308
  43. #define O2_SD_CLK_SETTING 0x328
  44. #define O2_SD_CAP_REG2 0x330
  45. #define O2_SD_CAP_REG0 0x334
  46. #define O2_SD_UHS1_CAP_SETTING 0x33C
  47. #define O2_SD_DELAY_CTRL 0x350
  48. #define O2_SD_UHS2_L1_CTRL 0x35C
  49. #define O2_SD_FUNC_REG3 0x3E0
  50. #define O2_SD_FUNC_REG4 0x3E4
  51. #define O2_SD_LED_ENABLE BIT(6)
  52. #define O2_SD_FREG0_LEDOFF BIT(13)
  53. #define O2_SD_FREG4_ENABLE_CLK_SET BIT(22)
  54. #define O2_SD_VENDOR_SETTING 0x110
  55. #define O2_SD_VENDOR_SETTING2 0x1C8
  56. #define O2_SD_HW_TUNING_DISABLE BIT(4)
  57. static void sdhci_o2_set_tuning_mode(struct sdhci_host *host)
  58. {
  59. u16 reg;
  60. /* enable hardware tuning */
  61. reg = sdhci_readw(host, O2_SD_VENDOR_SETTING);
  62. reg &= ~O2_SD_HW_TUNING_DISABLE;
  63. sdhci_writew(host, reg, O2_SD_VENDOR_SETTING);
  64. }
  65. static void __sdhci_o2_execute_tuning(struct sdhci_host *host, u32 opcode)
  66. {
  67. int i;
  68. sdhci_send_tuning(host, MMC_SEND_TUNING_BLOCK_HS200);
  69. for (i = 0; i < 150; i++) {
  70. u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  71. if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
  72. if (ctrl & SDHCI_CTRL_TUNED_CLK) {
  73. host->tuning_done = true;
  74. return;
  75. }
  76. pr_warn("%s: HW tuning failed !\n",
  77. mmc_hostname(host->mmc));
  78. break;
  79. }
  80. mdelay(1);
  81. }
  82. pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
  83. mmc_hostname(host->mmc));
  84. sdhci_reset_tuning(host);
  85. }
  86. static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode)
  87. {
  88. struct sdhci_host *host = mmc_priv(mmc);
  89. int current_bus_width = 0;
  90. /*
  91. * This handler only implements the eMMC tuning that is specific to
  92. * this controller. Fall back to the standard method for other TIMING.
  93. */
  94. if (host->timing != MMC_TIMING_MMC_HS200)
  95. return sdhci_execute_tuning(mmc, opcode);
  96. if (WARN_ON(opcode != MMC_SEND_TUNING_BLOCK_HS200))
  97. return -EINVAL;
  98. /*
  99. * o2 sdhci host didn't support 8bit emmc tuning
  100. */
  101. if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) {
  102. current_bus_width = mmc->ios.bus_width;
  103. mmc->ios.bus_width = MMC_BUS_WIDTH_4;
  104. sdhci_set_bus_width(host, MMC_BUS_WIDTH_4);
  105. }
  106. sdhci_o2_set_tuning_mode(host);
  107. sdhci_start_tuning(host);
  108. __sdhci_o2_execute_tuning(host, opcode);
  109. sdhci_end_tuning(host);
  110. if (current_bus_width == MMC_BUS_WIDTH_8) {
  111. mmc->ios.bus_width = MMC_BUS_WIDTH_8;
  112. sdhci_set_bus_width(host, current_bus_width);
  113. }
  114. host->flags &= ~SDHCI_HS400_TUNING;
  115. return 0;
  116. }
  117. static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value)
  118. {
  119. u32 scratch_32;
  120. pci_read_config_dword(chip->pdev,
  121. O2_SD_PLL_SETTING, &scratch_32);
  122. scratch_32 &= 0x0000FFFF;
  123. scratch_32 |= value;
  124. pci_write_config_dword(chip->pdev,
  125. O2_SD_PLL_SETTING, scratch_32);
  126. }
  127. static void o2_pci_led_enable(struct sdhci_pci_chip *chip)
  128. {
  129. int ret;
  130. u32 scratch_32;
  131. /* Set led of SD host function enable */
  132. ret = pci_read_config_dword(chip->pdev,
  133. O2_SD_FUNC_REG0, &scratch_32);
  134. if (ret)
  135. return;
  136. scratch_32 &= ~O2_SD_FREG0_LEDOFF;
  137. pci_write_config_dword(chip->pdev,
  138. O2_SD_FUNC_REG0, scratch_32);
  139. ret = pci_read_config_dword(chip->pdev,
  140. O2_SD_TEST_REG, &scratch_32);
  141. if (ret)
  142. return;
  143. scratch_32 |= O2_SD_LED_ENABLE;
  144. pci_write_config_dword(chip->pdev,
  145. O2_SD_TEST_REG, scratch_32);
  146. }
  147. static void sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip *chip)
  148. {
  149. u32 scratch_32;
  150. int ret;
  151. /* Improve write performance for SD3.0 */
  152. ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32);
  153. if (ret)
  154. return;
  155. scratch_32 &= ~((1 << 12) | (1 << 13) | (1 << 14));
  156. pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32);
  157. /* Enable Link abnormal reset generating Reset */
  158. ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32);
  159. if (ret)
  160. return;
  161. scratch_32 &= ~((1 << 19) | (1 << 11));
  162. scratch_32 |= (1 << 10);
  163. pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32);
  164. /* set card power over current protection */
  165. ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32);
  166. if (ret)
  167. return;
  168. scratch_32 |= (1 << 4);
  169. pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32);
  170. /* adjust the output delay for SD mode */
  171. pci_write_config_dword(chip->pdev, O2_SD_DELAY_CTRL, 0x00002492);
  172. /* Set the output voltage setting of Aux 1.2v LDO */
  173. ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32);
  174. if (ret)
  175. return;
  176. scratch_32 &= ~(3 << 12);
  177. pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32);
  178. /* Set Max power supply capability of SD host */
  179. ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32);
  180. if (ret)
  181. return;
  182. scratch_32 &= ~(0x01FE);
  183. scratch_32 |= 0x00CC;
  184. pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32);
  185. /* Set DLL Tuning Window */
  186. ret = pci_read_config_dword(chip->pdev,
  187. O2_SD_TUNING_CTRL, &scratch_32);
  188. if (ret)
  189. return;
  190. scratch_32 &= ~(0x000000FF);
  191. scratch_32 |= 0x00000066;
  192. pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32);
  193. /* Set UHS2 T_EIDLE */
  194. ret = pci_read_config_dword(chip->pdev,
  195. O2_SD_UHS2_L1_CTRL, &scratch_32);
  196. if (ret)
  197. return;
  198. scratch_32 &= ~(0x000000FC);
  199. scratch_32 |= 0x00000084;
  200. pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32);
  201. /* Set UHS2 Termination */
  202. ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32);
  203. if (ret)
  204. return;
  205. scratch_32 &= ~((1 << 21) | (1 << 30));
  206. pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32);
  207. /* Set L1 Entrance Timer */
  208. ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32);
  209. if (ret)
  210. return;
  211. scratch_32 &= ~(0xf0000000);
  212. scratch_32 |= 0x30000000;
  213. pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32);
  214. ret = pci_read_config_dword(chip->pdev,
  215. O2_SD_MISC_CTRL4, &scratch_32);
  216. if (ret)
  217. return;
  218. scratch_32 &= ~(0x000f0000);
  219. scratch_32 |= 0x00080000;
  220. pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32);
  221. }
  222. static void sdhci_pci_o2_enable_msi(struct sdhci_pci_chip *chip,
  223. struct sdhci_host *host)
  224. {
  225. int ret;
  226. ret = pci_find_capability(chip->pdev, PCI_CAP_ID_MSI);
  227. if (!ret) {
  228. pr_info("%s: unsupport msi, use INTx irq\n",
  229. mmc_hostname(host->mmc));
  230. return;
  231. }
  232. ret = pci_alloc_irq_vectors(chip->pdev, 1, 1,
  233. PCI_IRQ_MSI | PCI_IRQ_MSIX);
  234. if (ret < 0) {
  235. pr_err("%s: enable PCI MSI failed, err=%d\n",
  236. mmc_hostname(host->mmc), ret);
  237. return;
  238. }
  239. host->irq = pci_irq_vector(chip->pdev, 0);
  240. }
  241. int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot)
  242. {
  243. struct sdhci_pci_chip *chip;
  244. struct sdhci_host *host;
  245. u32 reg, caps;
  246. int ret;
  247. chip = slot->chip;
  248. host = slot->host;
  249. caps = sdhci_readl(host, SDHCI_CAPABILITIES);
  250. /*
  251. * mmc_select_bus_width() will test the bus to determine the actual bus
  252. * width.
  253. */
  254. if (caps & SDHCI_CAN_DO_8BIT)
  255. host->mmc->caps |= MMC_CAP_8_BIT_DATA;
  256. switch (chip->pdev->device) {
  257. case PCI_DEVICE_ID_O2_SDS0:
  258. case PCI_DEVICE_ID_O2_SEABIRD0:
  259. case PCI_DEVICE_ID_O2_SEABIRD1:
  260. case PCI_DEVICE_ID_O2_SDS1:
  261. case PCI_DEVICE_ID_O2_FUJIN2:
  262. reg = sdhci_readl(host, O2_SD_VENDOR_SETTING);
  263. if (reg & 0x1)
  264. host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
  265. sdhci_pci_o2_enable_msi(chip, host);
  266. if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD0) {
  267. ret = pci_read_config_dword(chip->pdev,
  268. O2_SD_MISC_SETTING, &reg);
  269. if (ret)
  270. return -EIO;
  271. if (reg & (1 << 4)) {
  272. pr_info("%s: emmc 1.8v flag is set, force 1.8v signaling voltage\n",
  273. mmc_hostname(host->mmc));
  274. host->flags &= ~SDHCI_SIGNALING_330;
  275. host->flags |= SDHCI_SIGNALING_180;
  276. host->mmc->caps2 |= MMC_CAP2_NO_SD;
  277. host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
  278. }
  279. }
  280. host->mmc_host_ops.execute_tuning = sdhci_o2_execute_tuning;
  281. if (chip->pdev->device != PCI_DEVICE_ID_O2_FUJIN2)
  282. break;
  283. /* set dll watch dog timer */
  284. reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2);
  285. reg |= (1 << 12);
  286. sdhci_writel(host, reg, O2_SD_VENDOR_SETTING2);
  287. break;
  288. default:
  289. break;
  290. }
  291. return 0;
  292. }
  293. int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip)
  294. {
  295. int ret;
  296. u8 scratch;
  297. u32 scratch_32;
  298. switch (chip->pdev->device) {
  299. case PCI_DEVICE_ID_O2_8220:
  300. case PCI_DEVICE_ID_O2_8221:
  301. case PCI_DEVICE_ID_O2_8320:
  302. case PCI_DEVICE_ID_O2_8321:
  303. /* This extra setup is required due to broken ADMA. */
  304. ret = pci_read_config_byte(chip->pdev,
  305. O2_SD_LOCK_WP, &scratch);
  306. if (ret)
  307. return ret;
  308. scratch &= 0x7f;
  309. pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
  310. /* Set Multi 3 to VCC3V# */
  311. pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08);
  312. /* Disable CLK_REQ# support after media DET */
  313. ret = pci_read_config_byte(chip->pdev,
  314. O2_SD_CLKREQ, &scratch);
  315. if (ret)
  316. return ret;
  317. scratch |= 0x20;
  318. pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);
  319. /* Choose capabilities, enable SDMA. We have to write 0x01
  320. * to the capabilities register first to unlock it.
  321. */
  322. ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);
  323. if (ret)
  324. return ret;
  325. scratch |= 0x01;
  326. pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);
  327. pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73);
  328. /* Disable ADMA1/2 */
  329. pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39);
  330. pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08);
  331. /* Disable the infinite transfer mode */
  332. ret = pci_read_config_byte(chip->pdev,
  333. O2_SD_INF_MOD, &scratch);
  334. if (ret)
  335. return ret;
  336. scratch |= 0x08;
  337. pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);
  338. /* Lock WP */
  339. ret = pci_read_config_byte(chip->pdev,
  340. O2_SD_LOCK_WP, &scratch);
  341. if (ret)
  342. return ret;
  343. scratch |= 0x80;
  344. pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
  345. break;
  346. case PCI_DEVICE_ID_O2_SDS0:
  347. case PCI_DEVICE_ID_O2_SDS1:
  348. case PCI_DEVICE_ID_O2_FUJIN2:
  349. /* UnLock WP */
  350. ret = pci_read_config_byte(chip->pdev,
  351. O2_SD_LOCK_WP, &scratch);
  352. if (ret)
  353. return ret;
  354. scratch &= 0x7f;
  355. pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
  356. /* DevId=8520 subId= 0x11 or 0x12 Type Chip support */
  357. if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) {
  358. ret = pci_read_config_dword(chip->pdev,
  359. O2_SD_FUNC_REG0,
  360. &scratch_32);
  361. scratch_32 = ((scratch_32 & 0xFF000000) >> 24);
  362. /* Check Whether subId is 0x11 or 0x12 */
  363. if ((scratch_32 == 0x11) || (scratch_32 == 0x12)) {
  364. scratch_32 = 0x25100000;
  365. o2_pci_set_baseclk(chip, scratch_32);
  366. ret = pci_read_config_dword(chip->pdev,
  367. O2_SD_FUNC_REG4,
  368. &scratch_32);
  369. /* Enable Base Clk setting change */
  370. scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;
  371. pci_write_config_dword(chip->pdev,
  372. O2_SD_FUNC_REG4,
  373. scratch_32);
  374. /* Set Tuning Window to 4 */
  375. pci_write_config_byte(chip->pdev,
  376. O2_SD_TUNING_CTRL, 0x44);
  377. break;
  378. }
  379. }
  380. /* Enable 8520 led function */
  381. o2_pci_led_enable(chip);
  382. /* Set timeout CLK */
  383. ret = pci_read_config_dword(chip->pdev,
  384. O2_SD_CLK_SETTING, &scratch_32);
  385. if (ret)
  386. return ret;
  387. scratch_32 &= ~(0xFF00);
  388. scratch_32 |= 0x07E0C800;
  389. pci_write_config_dword(chip->pdev,
  390. O2_SD_CLK_SETTING, scratch_32);
  391. ret = pci_read_config_dword(chip->pdev,
  392. O2_SD_CLKREQ, &scratch_32);
  393. if (ret)
  394. return ret;
  395. scratch_32 |= 0x3;
  396. pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32);
  397. ret = pci_read_config_dword(chip->pdev,
  398. O2_SD_PLL_SETTING, &scratch_32);
  399. if (ret)
  400. return ret;
  401. scratch_32 &= ~(0x1F3F070E);
  402. scratch_32 |= 0x18270106;
  403. pci_write_config_dword(chip->pdev,
  404. O2_SD_PLL_SETTING, scratch_32);
  405. /* Disable UHS1 funciton */
  406. ret = pci_read_config_dword(chip->pdev,
  407. O2_SD_CAP_REG2, &scratch_32);
  408. if (ret)
  409. return ret;
  410. scratch_32 &= ~(0xE0);
  411. pci_write_config_dword(chip->pdev,
  412. O2_SD_CAP_REG2, scratch_32);
  413. if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2)
  414. sdhci_pci_o2_fujin2_pci_init(chip);
  415. /* Lock WP */
  416. ret = pci_read_config_byte(chip->pdev,
  417. O2_SD_LOCK_WP, &scratch);
  418. if (ret)
  419. return ret;
  420. scratch |= 0x80;
  421. pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
  422. break;
  423. case PCI_DEVICE_ID_O2_SEABIRD0:
  424. if (chip->pdev->revision == 0x01)
  425. chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
  426. /* fall through */
  427. case PCI_DEVICE_ID_O2_SEABIRD1:
  428. /* UnLock WP */
  429. ret = pci_read_config_byte(chip->pdev,
  430. O2_SD_LOCK_WP, &scratch);
  431. if (ret)
  432. return ret;
  433. scratch &= 0x7f;
  434. pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
  435. ret = pci_read_config_dword(chip->pdev,
  436. O2_SD_PLL_SETTING, &scratch_32);
  437. if ((scratch_32 & 0xff000000) == 0x01000000) {
  438. scratch_32 &= 0x0000FFFF;
  439. scratch_32 |= 0x1F340000;
  440. pci_write_config_dword(chip->pdev,
  441. O2_SD_PLL_SETTING, scratch_32);
  442. } else {
  443. scratch_32 &= 0x0000FFFF;
  444. scratch_32 |= 0x25100000;
  445. pci_write_config_dword(chip->pdev,
  446. O2_SD_PLL_SETTING, scratch_32);
  447. ret = pci_read_config_dword(chip->pdev,
  448. O2_SD_FUNC_REG4,
  449. &scratch_32);
  450. scratch_32 |= (1 << 22);
  451. pci_write_config_dword(chip->pdev,
  452. O2_SD_FUNC_REG4, scratch_32);
  453. }
  454. /* Set Tuning Windows to 5 */
  455. pci_write_config_byte(chip->pdev,
  456. O2_SD_TUNING_CTRL, 0x55);
  457. /* Lock WP */
  458. ret = pci_read_config_byte(chip->pdev,
  459. O2_SD_LOCK_WP, &scratch);
  460. if (ret)
  461. return ret;
  462. scratch |= 0x80;
  463. pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
  464. break;
  465. }
  466. return 0;
  467. }
  468. #ifdef CONFIG_PM_SLEEP
  469. int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip)
  470. {
  471. sdhci_pci_o2_probe(chip);
  472. return sdhci_pci_resume_host(chip);
  473. }
  474. #endif