sdhci-pci.h 5.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. #ifndef __SDHCI_PCI_H
  3. #define __SDHCI_PCI_H
  4. /*
  5. * PCI device IDs, sub IDs
  6. */
  7. #define PCI_DEVICE_ID_O2_SDS0 0x8420
  8. #define PCI_DEVICE_ID_O2_SDS1 0x8421
  9. #define PCI_DEVICE_ID_O2_FUJIN2 0x8520
  10. #define PCI_DEVICE_ID_O2_SEABIRD0 0x8620
  11. #define PCI_DEVICE_ID_O2_SEABIRD1 0x8621
  12. #define PCI_DEVICE_ID_INTEL_PCH_SDIO0 0x8809
  13. #define PCI_DEVICE_ID_INTEL_PCH_SDIO1 0x880a
  14. #define PCI_DEVICE_ID_INTEL_BYT_EMMC 0x0f14
  15. #define PCI_DEVICE_ID_INTEL_BYT_SDIO 0x0f15
  16. #define PCI_DEVICE_ID_INTEL_BYT_SD 0x0f16
  17. #define PCI_DEVICE_ID_INTEL_BYT_EMMC2 0x0f50
  18. #define PCI_DEVICE_ID_INTEL_BSW_EMMC 0x2294
  19. #define PCI_DEVICE_ID_INTEL_BSW_SDIO 0x2295
  20. #define PCI_DEVICE_ID_INTEL_BSW_SD 0x2296
  21. #define PCI_DEVICE_ID_INTEL_MRFLD_MMC 0x1190
  22. #define PCI_DEVICE_ID_INTEL_CLV_SDIO0 0x08f9
  23. #define PCI_DEVICE_ID_INTEL_CLV_SDIO1 0x08fa
  24. #define PCI_DEVICE_ID_INTEL_CLV_SDIO2 0x08fb
  25. #define PCI_DEVICE_ID_INTEL_CLV_EMMC0 0x08e5
  26. #define PCI_DEVICE_ID_INTEL_CLV_EMMC1 0x08e6
  27. #define PCI_DEVICE_ID_INTEL_QRK_SD 0x08A7
  28. #define PCI_DEVICE_ID_INTEL_SPT_EMMC 0x9d2b
  29. #define PCI_DEVICE_ID_INTEL_SPT_SDIO 0x9d2c
  30. #define PCI_DEVICE_ID_INTEL_SPT_SD 0x9d2d
  31. #define PCI_DEVICE_ID_INTEL_DNV_EMMC 0x19db
  32. #define PCI_DEVICE_ID_INTEL_CDF_EMMC 0x18db
  33. #define PCI_DEVICE_ID_INTEL_BXT_SD 0x0aca
  34. #define PCI_DEVICE_ID_INTEL_BXT_EMMC 0x0acc
  35. #define PCI_DEVICE_ID_INTEL_BXT_SDIO 0x0ad0
  36. #define PCI_DEVICE_ID_INTEL_BXTM_SD 0x1aca
  37. #define PCI_DEVICE_ID_INTEL_BXTM_EMMC 0x1acc
  38. #define PCI_DEVICE_ID_INTEL_BXTM_SDIO 0x1ad0
  39. #define PCI_DEVICE_ID_INTEL_APL_SD 0x5aca
  40. #define PCI_DEVICE_ID_INTEL_APL_EMMC 0x5acc
  41. #define PCI_DEVICE_ID_INTEL_APL_SDIO 0x5ad0
  42. #define PCI_DEVICE_ID_INTEL_GLK_SD 0x31ca
  43. #define PCI_DEVICE_ID_INTEL_GLK_EMMC 0x31cc
  44. #define PCI_DEVICE_ID_INTEL_GLK_SDIO 0x31d0
  45. #define PCI_DEVICE_ID_INTEL_CNP_EMMC 0x9dc4
  46. #define PCI_DEVICE_ID_INTEL_CNP_SD 0x9df5
  47. #define PCI_DEVICE_ID_INTEL_CNPH_SD 0xa375
  48. #define PCI_DEVICE_ID_INTEL_ICP_EMMC 0x34c4
  49. #define PCI_DEVICE_ID_INTEL_ICP_SD 0x34f8
  50. #define PCI_DEVICE_ID_INTEL_CML_EMMC 0x02c4
  51. #define PCI_DEVICE_ID_INTEL_CML_SD 0x02f5
  52. #define PCI_DEVICE_ID_SYSKONNECT_8000 0x8000
  53. #define PCI_DEVICE_ID_VIA_95D0 0x95d0
  54. #define PCI_DEVICE_ID_REALTEK_5250 0x5250
  55. #define PCI_SUBDEVICE_ID_NI_7884 0x7884
  56. #define PCI_SUBDEVICE_ID_NI_78E3 0x78e3
  57. #define PCI_VENDOR_ID_ARASAN 0x16e6
  58. #define PCI_DEVICE_ID_ARASAN_PHY_EMMC 0x0670
  59. #define PCI_DEVICE_ID_SYNOPSYS_DWC_MSHC 0xc202
  60. /*
  61. * PCI device class and mask
  62. */
  63. #define SYSTEM_SDHCI (PCI_CLASS_SYSTEM_SDHCI << 8)
  64. #define PCI_CLASS_MASK 0xFFFF00
  65. /*
  66. * Macros for PCI device-description
  67. */
  68. #define _PCI_VEND(vend) PCI_VENDOR_ID_##vend
  69. #define _PCI_DEV(vend, dev) PCI_DEVICE_ID_##vend##_##dev
  70. #define _PCI_SUBDEV(subvend, subdev) PCI_SUBDEVICE_ID_##subvend##_##subdev
  71. #define SDHCI_PCI_DEVICE(vend, dev, cfg) { \
  72. .vendor = _PCI_VEND(vend), .device = _PCI_DEV(vend, dev), \
  73. .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \
  74. .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \
  75. }
  76. #define SDHCI_PCI_SUBDEVICE(vend, dev, subvend, subdev, cfg) { \
  77. .vendor = _PCI_VEND(vend), .device = _PCI_DEV(vend, dev), \
  78. .subvendor = _PCI_VEND(subvend), \
  79. .subdevice = _PCI_SUBDEV(subvend, subdev), \
  80. .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \
  81. }
  82. #define SDHCI_PCI_DEVICE_CLASS(vend, cl, cl_msk, cfg) { \
  83. .vendor = _PCI_VEND(vend), .device = PCI_ANY_ID, \
  84. .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \
  85. .class = (cl), .class_mask = (cl_msk), \
  86. .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \
  87. }
  88. /*
  89. * PCI registers
  90. */
  91. #define PCI_SDHCI_IFPIO 0x00
  92. #define PCI_SDHCI_IFDMA 0x01
  93. #define PCI_SDHCI_IFVENDOR 0x02
  94. #define PCI_SLOT_INFO 0x40 /* 8 bits */
  95. #define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7)
  96. #define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07
  97. #define MAX_SLOTS 8
  98. struct sdhci_pci_chip;
  99. struct sdhci_pci_slot;
  100. struct sdhci_pci_fixes {
  101. unsigned int quirks;
  102. unsigned int quirks2;
  103. bool allow_runtime_pm;
  104. bool own_cd_for_runtime_pm;
  105. int (*probe) (struct sdhci_pci_chip *);
  106. int (*probe_slot) (struct sdhci_pci_slot *);
  107. int (*add_host) (struct sdhci_pci_slot *);
  108. void (*remove_slot) (struct sdhci_pci_slot *, int);
  109. #ifdef CONFIG_PM_SLEEP
  110. int (*suspend) (struct sdhci_pci_chip *);
  111. int (*resume) (struct sdhci_pci_chip *);
  112. #endif
  113. #ifdef CONFIG_PM
  114. int (*runtime_suspend) (struct sdhci_pci_chip *);
  115. int (*runtime_resume) (struct sdhci_pci_chip *);
  116. #endif
  117. const struct sdhci_ops *ops;
  118. size_t priv_size;
  119. };
  120. struct sdhci_pci_slot {
  121. struct sdhci_pci_chip *chip;
  122. struct sdhci_host *host;
  123. struct sdhci_pci_data *data;
  124. int rst_n_gpio;
  125. int cd_gpio;
  126. int cd_irq;
  127. int cd_idx;
  128. bool cd_override_level;
  129. void (*hw_reset)(struct sdhci_host *host);
  130. unsigned long private[0] ____cacheline_aligned;
  131. };
  132. struct sdhci_pci_chip {
  133. struct pci_dev *pdev;
  134. unsigned int quirks;
  135. unsigned int quirks2;
  136. bool allow_runtime_pm;
  137. bool pm_retune;
  138. bool rpm_retune;
  139. const struct sdhci_pci_fixes *fixes;
  140. int num_slots; /* Slots on controller */
  141. struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */
  142. };
  143. static inline void *sdhci_pci_priv(struct sdhci_pci_slot *slot)
  144. {
  145. return (void *)slot->private;
  146. }
  147. #ifdef CONFIG_PM_SLEEP
  148. int sdhci_pci_resume_host(struct sdhci_pci_chip *chip);
  149. #endif
  150. int sdhci_pci_enable_dma(struct sdhci_host *host);
  151. int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot);
  152. int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip);
  153. #ifdef CONFIG_PM_SLEEP
  154. int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip);
  155. #endif
  156. extern const struct sdhci_pci_fixes sdhci_arasan;
  157. extern const struct sdhci_pci_fixes sdhci_snps;
  158. #endif /* __SDHCI_PCI_H */