sdhci-tegra.c 18 KB

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  1. /*
  2. * Copyright (C) 2010 Google, Inc.
  3. *
  4. * This software is licensed under the terms of the GNU General Public
  5. * License version 2, as published by the Free Software Foundation, and
  6. * may be copied, distributed, and modified under those terms.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. *
  13. */
  14. #include <linux/delay.h>
  15. #include <linux/err.h>
  16. #include <linux/module.h>
  17. #include <linux/init.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/clk.h>
  20. #include <linux/io.h>
  21. #include <linux/of.h>
  22. #include <linux/of_device.h>
  23. #include <linux/reset.h>
  24. #include <linux/mmc/card.h>
  25. #include <linux/mmc/host.h>
  26. #include <linux/mmc/mmc.h>
  27. #include <linux/mmc/slot-gpio.h>
  28. #include <linux/gpio/consumer.h>
  29. #include "sdhci-pltfm.h"
  30. /* Tegra SDHOST controller vendor register definitions */
  31. #define SDHCI_TEGRA_VENDOR_CLOCK_CTRL 0x100
  32. #define SDHCI_CLOCK_CTRL_TAP_MASK 0x00ff0000
  33. #define SDHCI_CLOCK_CTRL_TAP_SHIFT 16
  34. #define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE BIT(5)
  35. #define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE BIT(3)
  36. #define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE BIT(2)
  37. #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120
  38. #define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8
  39. #define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10
  40. #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20
  41. #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200
  42. #define SDHCI_TEGRA_AUTO_CAL_CONFIG 0x1e4
  43. #define SDHCI_AUTO_CAL_START BIT(31)
  44. #define SDHCI_AUTO_CAL_ENABLE BIT(29)
  45. #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0)
  46. #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1)
  47. #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2)
  48. #define NVQUIRK_ENABLE_SDR50 BIT(3)
  49. #define NVQUIRK_ENABLE_SDR104 BIT(4)
  50. #define NVQUIRK_ENABLE_DDR50 BIT(5)
  51. #define NVQUIRK_HAS_PADCALIB BIT(6)
  52. struct sdhci_tegra_soc_data {
  53. const struct sdhci_pltfm_data *pdata;
  54. u32 nvquirks;
  55. };
  56. struct sdhci_tegra {
  57. const struct sdhci_tegra_soc_data *soc_data;
  58. struct gpio_desc *power_gpio;
  59. bool ddr_signaling;
  60. bool pad_calib_required;
  61. struct reset_control *rst;
  62. };
  63. static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
  64. {
  65. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  66. struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
  67. const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
  68. if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) &&
  69. (reg == SDHCI_HOST_VERSION))) {
  70. /* Erratum: Version register is invalid in HW. */
  71. return SDHCI_SPEC_200;
  72. }
  73. return readw(host->ioaddr + reg);
  74. }
  75. static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
  76. {
  77. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  78. switch (reg) {
  79. case SDHCI_TRANSFER_MODE:
  80. /*
  81. * Postpone this write, we must do it together with a
  82. * command write that is down below.
  83. */
  84. pltfm_host->xfer_mode_shadow = val;
  85. return;
  86. case SDHCI_COMMAND:
  87. writel((val << 16) | pltfm_host->xfer_mode_shadow,
  88. host->ioaddr + SDHCI_TRANSFER_MODE);
  89. return;
  90. }
  91. writew(val, host->ioaddr + reg);
  92. }
  93. static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
  94. {
  95. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  96. struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
  97. const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
  98. /* Seems like we're getting spurious timeout and crc errors, so
  99. * disable signalling of them. In case of real errors software
  100. * timers should take care of eventually detecting them.
  101. */
  102. if (unlikely(reg == SDHCI_SIGNAL_ENABLE))
  103. val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC);
  104. writel(val, host->ioaddr + reg);
  105. if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) &&
  106. (reg == SDHCI_INT_ENABLE))) {
  107. /* Erratum: Must enable block gap interrupt detection */
  108. u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
  109. if (val & SDHCI_INT_CARD_INT)
  110. gap_ctrl |= 0x8;
  111. else
  112. gap_ctrl &= ~0x8;
  113. writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
  114. }
  115. }
  116. static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host)
  117. {
  118. return mmc_gpio_get_ro(host->mmc);
  119. }
  120. static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask)
  121. {
  122. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  123. struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
  124. const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
  125. u32 misc_ctrl, clk_ctrl;
  126. sdhci_reset(host, mask);
  127. if (!(mask & SDHCI_RESET_ALL))
  128. return;
  129. misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL);
  130. clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
  131. misc_ctrl &= ~(SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 |
  132. SDHCI_MISC_CTRL_ENABLE_SDR50 |
  133. SDHCI_MISC_CTRL_ENABLE_DDR50 |
  134. SDHCI_MISC_CTRL_ENABLE_SDR104);
  135. clk_ctrl &= ~SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE;
  136. /*
  137. * If the board does not define a regulator for the SDHCI
  138. * IO voltage, then don't advertise support for UHS modes
  139. * even if the device supports it because the IO voltage
  140. * cannot be configured.
  141. */
  142. if (!IS_ERR(host->mmc->supply.vqmmc)) {
  143. /* Erratum: Enable SDHCI spec v3.00 support */
  144. if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300)
  145. misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300;
  146. /* Advertise UHS modes as supported by host */
  147. if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50)
  148. misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR50;
  149. if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50)
  150. misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_DDR50;
  151. if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104)
  152. misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR104;
  153. if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50)
  154. clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE;
  155. }
  156. sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL);
  157. sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
  158. if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB)
  159. tegra_host->pad_calib_required = true;
  160. tegra_host->ddr_signaling = false;
  161. }
  162. static void tegra_sdhci_pad_autocalib(struct sdhci_host *host)
  163. {
  164. u32 val;
  165. mdelay(1);
  166. val = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG);
  167. val |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START;
  168. sdhci_writel(host,val, SDHCI_TEGRA_AUTO_CAL_CONFIG);
  169. }
  170. static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
  171. {
  172. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  173. struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
  174. unsigned long host_clk;
  175. if (!clock)
  176. return sdhci_set_clock(host, clock);
  177. /*
  178. * In DDR50/52 modes the Tegra SDHCI controllers require the SDHCI
  179. * divider to be configured to divided the host clock by two. The SDHCI
  180. * clock divider is calculated as part of sdhci_set_clock() by
  181. * sdhci_calc_clk(). The divider is calculated from host->max_clk and
  182. * the requested clock rate.
  183. *
  184. * By setting the host->max_clk to clock * 2 the divider calculation
  185. * will always result in the correct value for DDR50/52 modes,
  186. * regardless of clock rate rounding, which may happen if the value
  187. * from clk_get_rate() is used.
  188. */
  189. host_clk = tegra_host->ddr_signaling ? clock * 2 : clock;
  190. clk_set_rate(pltfm_host->clk, host_clk);
  191. if (tegra_host->ddr_signaling)
  192. host->max_clk = host_clk;
  193. else
  194. host->max_clk = clk_get_rate(pltfm_host->clk);
  195. sdhci_set_clock(host, clock);
  196. if (tegra_host->pad_calib_required) {
  197. tegra_sdhci_pad_autocalib(host);
  198. tegra_host->pad_calib_required = false;
  199. }
  200. }
  201. static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host,
  202. unsigned timing)
  203. {
  204. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  205. struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
  206. if (timing == MMC_TIMING_UHS_DDR50 ||
  207. timing == MMC_TIMING_MMC_DDR52)
  208. tegra_host->ddr_signaling = true;
  209. sdhci_set_uhs_signaling(host, timing);
  210. }
  211. static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host)
  212. {
  213. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  214. return clk_round_rate(pltfm_host->clk, UINT_MAX);
  215. }
  216. static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap)
  217. {
  218. u32 reg;
  219. reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
  220. reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK;
  221. reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT;
  222. sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
  223. }
  224. static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
  225. {
  226. unsigned int min, max;
  227. /*
  228. * Start search for minimum tap value at 10, as smaller values are
  229. * may wrongly be reported as working but fail at higher speeds,
  230. * according to the TRM.
  231. */
  232. min = 10;
  233. while (min < 255) {
  234. tegra_sdhci_set_tap(host, min);
  235. if (!mmc_send_tuning(host->mmc, opcode, NULL))
  236. break;
  237. min++;
  238. }
  239. /* Find the maximum tap value that still passes. */
  240. max = min + 1;
  241. while (max < 255) {
  242. tegra_sdhci_set_tap(host, max);
  243. if (mmc_send_tuning(host->mmc, opcode, NULL)) {
  244. max--;
  245. break;
  246. }
  247. max++;
  248. }
  249. /* The TRM states the ideal tap value is at 75% in the passing range. */
  250. tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4));
  251. return mmc_send_tuning(host->mmc, opcode, NULL);
  252. }
  253. static void tegra_sdhci_voltage_switch(struct sdhci_host *host)
  254. {
  255. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  256. struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
  257. const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
  258. if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB)
  259. tegra_host->pad_calib_required = true;
  260. }
  261. static const struct sdhci_ops tegra_sdhci_ops = {
  262. .get_ro = tegra_sdhci_get_ro,
  263. .read_w = tegra_sdhci_readw,
  264. .write_l = tegra_sdhci_writel,
  265. .set_clock = tegra_sdhci_set_clock,
  266. .set_bus_width = sdhci_set_bus_width,
  267. .reset = tegra_sdhci_reset,
  268. .platform_execute_tuning = tegra_sdhci_execute_tuning,
  269. .set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
  270. .voltage_switch = tegra_sdhci_voltage_switch,
  271. .get_max_clock = tegra_sdhci_get_max_clock,
  272. };
  273. static const struct sdhci_pltfm_data sdhci_tegra20_pdata = {
  274. .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
  275. SDHCI_QUIRK_SINGLE_POWER_WRITE |
  276. SDHCI_QUIRK_NO_HISPD_BIT |
  277. SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
  278. SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
  279. .ops = &tegra_sdhci_ops,
  280. };
  281. static const struct sdhci_tegra_soc_data soc_data_tegra20 = {
  282. .pdata = &sdhci_tegra20_pdata,
  283. .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 |
  284. NVQUIRK_ENABLE_BLOCK_GAP_DET,
  285. };
  286. static const struct sdhci_pltfm_data sdhci_tegra30_pdata = {
  287. .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
  288. SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
  289. SDHCI_QUIRK_SINGLE_POWER_WRITE |
  290. SDHCI_QUIRK_NO_HISPD_BIT |
  291. SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
  292. SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
  293. .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
  294. SDHCI_QUIRK2_BROKEN_HS200 |
  295. /*
  296. * Auto-CMD23 leads to "Got command interrupt 0x00010000 even
  297. * though no command operation was in progress."
  298. *
  299. * The exact reason is unknown, as the same hardware seems
  300. * to support Auto CMD23 on a downstream 3.1 kernel.
  301. */
  302. SDHCI_QUIRK2_ACMD23_BROKEN,
  303. .ops = &tegra_sdhci_ops,
  304. };
  305. static const struct sdhci_tegra_soc_data soc_data_tegra30 = {
  306. .pdata = &sdhci_tegra30_pdata,
  307. .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 |
  308. NVQUIRK_ENABLE_SDR50 |
  309. NVQUIRK_ENABLE_SDR104 |
  310. NVQUIRK_HAS_PADCALIB,
  311. };
  312. static const struct sdhci_ops tegra114_sdhci_ops = {
  313. .get_ro = tegra_sdhci_get_ro,
  314. .read_w = tegra_sdhci_readw,
  315. .write_w = tegra_sdhci_writew,
  316. .write_l = tegra_sdhci_writel,
  317. .set_clock = tegra_sdhci_set_clock,
  318. .set_bus_width = sdhci_set_bus_width,
  319. .reset = tegra_sdhci_reset,
  320. .platform_execute_tuning = tegra_sdhci_execute_tuning,
  321. .set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
  322. .voltage_switch = tegra_sdhci_voltage_switch,
  323. .get_max_clock = tegra_sdhci_get_max_clock,
  324. };
  325. static const struct sdhci_pltfm_data sdhci_tegra114_pdata = {
  326. .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
  327. SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
  328. SDHCI_QUIRK_SINGLE_POWER_WRITE |
  329. SDHCI_QUIRK_NO_HISPD_BIT |
  330. SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
  331. SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
  332. .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
  333. .ops = &tegra114_sdhci_ops,
  334. };
  335. static const struct sdhci_tegra_soc_data soc_data_tegra114 = {
  336. .pdata = &sdhci_tegra114_pdata,
  337. };
  338. static const struct sdhci_pltfm_data sdhci_tegra124_pdata = {
  339. .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
  340. SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
  341. SDHCI_QUIRK_SINGLE_POWER_WRITE |
  342. SDHCI_QUIRK_NO_HISPD_BIT |
  343. SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
  344. SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
  345. .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
  346. /*
  347. * The TRM states that the SD/MMC controller found on
  348. * Tegra124 can address 34 bits (the maximum supported by
  349. * the Tegra memory controller), but tests show that DMA
  350. * to or from above 4 GiB doesn't work. This is possibly
  351. * caused by missing programming, though it's not obvious
  352. * what sequence is required. Mark 64-bit DMA broken for
  353. * now to fix this for existing users (e.g. Nyan boards).
  354. */
  355. SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
  356. .ops = &tegra114_sdhci_ops,
  357. };
  358. static const struct sdhci_tegra_soc_data soc_data_tegra124 = {
  359. .pdata = &sdhci_tegra124_pdata,
  360. };
  361. static const struct sdhci_pltfm_data sdhci_tegra210_pdata = {
  362. .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
  363. SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
  364. SDHCI_QUIRK_SINGLE_POWER_WRITE |
  365. SDHCI_QUIRK_NO_HISPD_BIT |
  366. SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
  367. SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
  368. .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
  369. .ops = &tegra114_sdhci_ops,
  370. };
  371. static const struct sdhci_tegra_soc_data soc_data_tegra210 = {
  372. .pdata = &sdhci_tegra210_pdata,
  373. };
  374. static const struct sdhci_pltfm_data sdhci_tegra186_pdata = {
  375. .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
  376. SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
  377. SDHCI_QUIRK_SINGLE_POWER_WRITE |
  378. SDHCI_QUIRK_NO_HISPD_BIT |
  379. SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
  380. SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
  381. .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
  382. /* SDHCI controllers on Tegra186 support 40-bit addressing.
  383. * IOVA addresses are 48-bit wide on Tegra186.
  384. * With 64-bit dma mask used for SDHCI, accesses can
  385. * be broken. Disable 64-bit dma, which would fall back
  386. * to 32-bit dma mask. Ideally 40-bit dma mask would work,
  387. * But it is not supported as of now.
  388. */
  389. SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
  390. .ops = &tegra114_sdhci_ops,
  391. };
  392. static const struct sdhci_tegra_soc_data soc_data_tegra186 = {
  393. .pdata = &sdhci_tegra186_pdata,
  394. };
  395. static const struct of_device_id sdhci_tegra_dt_match[] = {
  396. { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 },
  397. { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 },
  398. { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 },
  399. { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 },
  400. { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 },
  401. { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 },
  402. {}
  403. };
  404. MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match);
  405. static int sdhci_tegra_probe(struct platform_device *pdev)
  406. {
  407. const struct of_device_id *match;
  408. const struct sdhci_tegra_soc_data *soc_data;
  409. struct sdhci_host *host;
  410. struct sdhci_pltfm_host *pltfm_host;
  411. struct sdhci_tegra *tegra_host;
  412. struct clk *clk;
  413. int rc;
  414. match = of_match_device(sdhci_tegra_dt_match, &pdev->dev);
  415. if (!match)
  416. return -EINVAL;
  417. soc_data = match->data;
  418. host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host));
  419. if (IS_ERR(host))
  420. return PTR_ERR(host);
  421. pltfm_host = sdhci_priv(host);
  422. tegra_host = sdhci_pltfm_priv(pltfm_host);
  423. tegra_host->ddr_signaling = false;
  424. tegra_host->pad_calib_required = false;
  425. tegra_host->soc_data = soc_data;
  426. rc = mmc_of_parse(host->mmc);
  427. if (rc)
  428. goto err_parse_dt;
  429. if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50)
  430. host->mmc->caps |= MMC_CAP_1_8V_DDR;
  431. /* R1B responses is required to properly manage HW busy detection. */
  432. host->mmc->caps |= MMC_CAP_NEED_RSP_BUSY;
  433. tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power",
  434. GPIOD_OUT_HIGH);
  435. if (IS_ERR(tegra_host->power_gpio)) {
  436. rc = PTR_ERR(tegra_host->power_gpio);
  437. goto err_power_req;
  438. }
  439. clk = devm_clk_get(mmc_dev(host->mmc), NULL);
  440. if (IS_ERR(clk)) {
  441. dev_err(mmc_dev(host->mmc), "clk err\n");
  442. rc = PTR_ERR(clk);
  443. goto err_clk_get;
  444. }
  445. clk_prepare_enable(clk);
  446. pltfm_host->clk = clk;
  447. tegra_host->rst = devm_reset_control_get_exclusive(&pdev->dev,
  448. "sdhci");
  449. if (IS_ERR(tegra_host->rst)) {
  450. rc = PTR_ERR(tegra_host->rst);
  451. dev_err(&pdev->dev, "failed to get reset control: %d\n", rc);
  452. goto err_rst_get;
  453. }
  454. rc = reset_control_assert(tegra_host->rst);
  455. if (rc)
  456. goto err_rst_get;
  457. usleep_range(2000, 4000);
  458. rc = reset_control_deassert(tegra_host->rst);
  459. if (rc)
  460. goto err_rst_get;
  461. usleep_range(2000, 4000);
  462. rc = sdhci_add_host(host);
  463. if (rc)
  464. goto err_add_host;
  465. return 0;
  466. err_add_host:
  467. reset_control_assert(tegra_host->rst);
  468. err_rst_get:
  469. clk_disable_unprepare(pltfm_host->clk);
  470. err_clk_get:
  471. err_power_req:
  472. err_parse_dt:
  473. sdhci_pltfm_free(pdev);
  474. return rc;
  475. }
  476. static int sdhci_tegra_remove(struct platform_device *pdev)
  477. {
  478. struct sdhci_host *host = platform_get_drvdata(pdev);
  479. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  480. struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
  481. sdhci_remove_host(host, 0);
  482. reset_control_assert(tegra_host->rst);
  483. usleep_range(2000, 4000);
  484. clk_disable_unprepare(pltfm_host->clk);
  485. sdhci_pltfm_free(pdev);
  486. return 0;
  487. }
  488. static struct platform_driver sdhci_tegra_driver = {
  489. .driver = {
  490. .name = "sdhci-tegra",
  491. .of_match_table = sdhci_tegra_dt_match,
  492. .pm = &sdhci_pltfm_pmops,
  493. },
  494. .probe = sdhci_tegra_probe,
  495. .remove = sdhci_tegra_remove,
  496. };
  497. module_platform_driver(sdhci_tegra_driver);
  498. MODULE_DESCRIPTION("SDHCI driver for Tegra");
  499. MODULE_AUTHOR("Google, Inc.");
  500. MODULE_LICENSE("GPL v2");