sdhci_f_sdh30.c 6.7 KB

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  1. /*
  2. * linux/drivers/mmc/host/sdhci_f_sdh30.c
  3. *
  4. * Copyright (C) 2013 - 2015 Fujitsu Semiconductor, Ltd
  5. * Vincent Yang <vincent.yang@tw.fujitsu.com>
  6. * Copyright (C) 2015 Linaro Ltd Andy Green <andy.green@linaro.org>
  7. *
  8. * This program is free software: you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation, version 2 of the License.
  11. */
  12. #include <linux/acpi.h>
  13. #include <linux/err.h>
  14. #include <linux/delay.h>
  15. #include <linux/module.h>
  16. #include <linux/of.h>
  17. #include <linux/property.h>
  18. #include <linux/clk.h>
  19. #include "sdhci-pltfm.h"
  20. /* F_SDH30 extended Controller registers */
  21. #define F_SDH30_AHB_CONFIG 0x100
  22. #define F_SDH30_AHB_BIGED 0x00000040
  23. #define F_SDH30_BUSLOCK_DMA 0x00000020
  24. #define F_SDH30_BUSLOCK_EN 0x00000010
  25. #define F_SDH30_SIN 0x00000008
  26. #define F_SDH30_AHB_INCR_16 0x00000004
  27. #define F_SDH30_AHB_INCR_8 0x00000002
  28. #define F_SDH30_AHB_INCR_4 0x00000001
  29. #define F_SDH30_TUNING_SETTING 0x108
  30. #define F_SDH30_CMD_CHK_DIS 0x00010000
  31. #define F_SDH30_IO_CONTROL2 0x114
  32. #define F_SDH30_CRES_O_DN 0x00080000
  33. #define F_SDH30_MSEL_O_1_8 0x00040000
  34. #define F_SDH30_ESD_CONTROL 0x124
  35. #define F_SDH30_EMMC_RST 0x00000002
  36. #define F_SDH30_EMMC_HS200 0x01000000
  37. #define F_SDH30_CMD_DAT_DELAY 0x200
  38. #define F_SDH30_MIN_CLOCK 400000
  39. struct f_sdhost_priv {
  40. struct clk *clk_iface;
  41. struct clk *clk;
  42. u32 vendor_hs200;
  43. struct device *dev;
  44. bool enable_cmd_dat_delay;
  45. };
  46. static void sdhci_f_sdh30_soft_voltage_switch(struct sdhci_host *host)
  47. {
  48. struct f_sdhost_priv *priv = sdhci_priv(host);
  49. u32 ctrl = 0;
  50. usleep_range(2500, 3000);
  51. ctrl = sdhci_readl(host, F_SDH30_IO_CONTROL2);
  52. ctrl |= F_SDH30_CRES_O_DN;
  53. sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2);
  54. ctrl |= F_SDH30_MSEL_O_1_8;
  55. sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2);
  56. ctrl &= ~F_SDH30_CRES_O_DN;
  57. sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2);
  58. usleep_range(2500, 3000);
  59. if (priv->vendor_hs200) {
  60. dev_info(priv->dev, "%s: setting hs200\n", __func__);
  61. ctrl = sdhci_readl(host, F_SDH30_ESD_CONTROL);
  62. ctrl |= priv->vendor_hs200;
  63. sdhci_writel(host, ctrl, F_SDH30_ESD_CONTROL);
  64. }
  65. ctrl = sdhci_readl(host, F_SDH30_TUNING_SETTING);
  66. ctrl |= F_SDH30_CMD_CHK_DIS;
  67. sdhci_writel(host, ctrl, F_SDH30_TUNING_SETTING);
  68. }
  69. static unsigned int sdhci_f_sdh30_get_min_clock(struct sdhci_host *host)
  70. {
  71. return F_SDH30_MIN_CLOCK;
  72. }
  73. static void sdhci_f_sdh30_reset(struct sdhci_host *host, u8 mask)
  74. {
  75. struct f_sdhost_priv *priv = sdhci_priv(host);
  76. u32 ctl;
  77. if (sdhci_readw(host, SDHCI_CLOCK_CONTROL) == 0)
  78. sdhci_writew(host, 0xBC01, SDHCI_CLOCK_CONTROL);
  79. sdhci_reset(host, mask);
  80. if (priv->enable_cmd_dat_delay) {
  81. ctl = sdhci_readl(host, F_SDH30_ESD_CONTROL);
  82. ctl |= F_SDH30_CMD_DAT_DELAY;
  83. sdhci_writel(host, ctl, F_SDH30_ESD_CONTROL);
  84. }
  85. }
  86. static const struct sdhci_ops sdhci_f_sdh30_ops = {
  87. .voltage_switch = sdhci_f_sdh30_soft_voltage_switch,
  88. .get_min_clock = sdhci_f_sdh30_get_min_clock,
  89. .reset = sdhci_f_sdh30_reset,
  90. .set_clock = sdhci_set_clock,
  91. .set_bus_width = sdhci_set_bus_width,
  92. .set_uhs_signaling = sdhci_set_uhs_signaling,
  93. };
  94. static int sdhci_f_sdh30_probe(struct platform_device *pdev)
  95. {
  96. struct sdhci_host *host;
  97. struct device *dev = &pdev->dev;
  98. struct resource *res;
  99. int irq, ctrl = 0, ret = 0;
  100. struct f_sdhost_priv *priv;
  101. u32 reg = 0;
  102. irq = platform_get_irq(pdev, 0);
  103. if (irq < 0) {
  104. dev_err(dev, "%s: no irq specified\n", __func__);
  105. return irq;
  106. }
  107. host = sdhci_alloc_host(dev, sizeof(struct f_sdhost_priv));
  108. if (IS_ERR(host))
  109. return PTR_ERR(host);
  110. priv = sdhci_priv(host);
  111. priv->dev = dev;
  112. host->quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
  113. SDHCI_QUIRK_INVERTED_WRITE_PROTECT;
  114. host->quirks2 = SDHCI_QUIRK2_SUPPORT_SINGLE |
  115. SDHCI_QUIRK2_TUNING_WORK_AROUND;
  116. priv->enable_cmd_dat_delay = device_property_read_bool(dev,
  117. "fujitsu,cmd-dat-delay-select");
  118. ret = mmc_of_parse(host->mmc);
  119. if (ret)
  120. goto err;
  121. platform_set_drvdata(pdev, host);
  122. host->hw_name = "f_sdh30";
  123. host->ops = &sdhci_f_sdh30_ops;
  124. host->irq = irq;
  125. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  126. host->ioaddr = devm_ioremap_resource(&pdev->dev, res);
  127. if (IS_ERR(host->ioaddr)) {
  128. ret = PTR_ERR(host->ioaddr);
  129. goto err;
  130. }
  131. if (dev_of_node(dev)) {
  132. sdhci_get_of_property(pdev);
  133. priv->clk_iface = devm_clk_get(&pdev->dev, "iface");
  134. if (IS_ERR(priv->clk_iface)) {
  135. ret = PTR_ERR(priv->clk_iface);
  136. goto err;
  137. }
  138. ret = clk_prepare_enable(priv->clk_iface);
  139. if (ret)
  140. goto err;
  141. priv->clk = devm_clk_get(&pdev->dev, "core");
  142. if (IS_ERR(priv->clk)) {
  143. ret = PTR_ERR(priv->clk);
  144. goto err_clk;
  145. }
  146. ret = clk_prepare_enable(priv->clk);
  147. if (ret)
  148. goto err_clk;
  149. }
  150. /* init vendor specific regs */
  151. ctrl = sdhci_readw(host, F_SDH30_AHB_CONFIG);
  152. ctrl |= F_SDH30_SIN | F_SDH30_AHB_INCR_16 | F_SDH30_AHB_INCR_8 |
  153. F_SDH30_AHB_INCR_4;
  154. ctrl &= ~(F_SDH30_AHB_BIGED | F_SDH30_BUSLOCK_EN);
  155. sdhci_writew(host, ctrl, F_SDH30_AHB_CONFIG);
  156. reg = sdhci_readl(host, F_SDH30_ESD_CONTROL);
  157. sdhci_writel(host, reg & ~F_SDH30_EMMC_RST, F_SDH30_ESD_CONTROL);
  158. msleep(20);
  159. sdhci_writel(host, reg | F_SDH30_EMMC_RST, F_SDH30_ESD_CONTROL);
  160. reg = sdhci_readl(host, SDHCI_CAPABILITIES);
  161. if (reg & SDHCI_CAN_DO_8BIT)
  162. priv->vendor_hs200 = F_SDH30_EMMC_HS200;
  163. ret = sdhci_add_host(host);
  164. if (ret)
  165. goto err_add_host;
  166. return 0;
  167. err_add_host:
  168. clk_disable_unprepare(priv->clk);
  169. err_clk:
  170. clk_disable_unprepare(priv->clk_iface);
  171. err:
  172. sdhci_free_host(host);
  173. return ret;
  174. }
  175. static int sdhci_f_sdh30_remove(struct platform_device *pdev)
  176. {
  177. struct sdhci_host *host = platform_get_drvdata(pdev);
  178. struct f_sdhost_priv *priv = sdhci_priv(host);
  179. sdhci_remove_host(host, readl(host->ioaddr + SDHCI_INT_STATUS) ==
  180. 0xffffffff);
  181. clk_disable_unprepare(priv->clk_iface);
  182. clk_disable_unprepare(priv->clk);
  183. sdhci_free_host(host);
  184. platform_set_drvdata(pdev, NULL);
  185. return 0;
  186. }
  187. #ifdef CONFIG_OF
  188. static const struct of_device_id f_sdh30_dt_ids[] = {
  189. { .compatible = "fujitsu,mb86s70-sdhci-3.0" },
  190. { /* sentinel */ }
  191. };
  192. MODULE_DEVICE_TABLE(of, f_sdh30_dt_ids);
  193. #endif
  194. #ifdef CONFIG_ACPI
  195. static const struct acpi_device_id f_sdh30_acpi_ids[] = {
  196. { "SCX0002" },
  197. { /* sentinel */ }
  198. };
  199. MODULE_DEVICE_TABLE(acpi, f_sdh30_acpi_ids);
  200. #endif
  201. static struct platform_driver sdhci_f_sdh30_driver = {
  202. .driver = {
  203. .name = "f_sdh30",
  204. .of_match_table = of_match_ptr(f_sdh30_dt_ids),
  205. .acpi_match_table = ACPI_PTR(f_sdh30_acpi_ids),
  206. .pm = &sdhci_pltfm_pmops,
  207. },
  208. .probe = sdhci_f_sdh30_probe,
  209. .remove = sdhci_f_sdh30_remove,
  210. };
  211. module_platform_driver(sdhci_f_sdh30_driver);
  212. MODULE_DESCRIPTION("F_SDH30 SD Card Controller driver");
  213. MODULE_LICENSE("GPL v2");
  214. MODULE_AUTHOR("FUJITSU SEMICONDUCTOR LTD.");
  215. MODULE_ALIAS("platform:f_sdh30");