sunxi-mmc.c 40 KB

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  1. /*
  2. * Driver for sunxi SD/MMC host controllers
  3. * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd.
  4. * (C) Copyright 2007-2011 Aaron Maoye <leafy.myeh@reuuimllatech.com>
  5. * (C) Copyright 2013-2014 O2S GmbH <www.o2s.ch>
  6. * (C) Copyright 2013-2014 David Lanzendörfer <david.lanzendoerfer@o2s.ch>
  7. * (C) Copyright 2013-2014 Hans de Goede <hdegoede@redhat.com>
  8. * (C) Copyright 2017 Sootech SA
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. */
  15. #include <linux/clk.h>
  16. #include <linux/clk/sunxi-ng.h>
  17. #include <linux/delay.h>
  18. #include <linux/device.h>
  19. #include <linux/dma-mapping.h>
  20. #include <linux/err.h>
  21. #include <linux/gpio.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/io.h>
  24. #include <linux/kernel.h>
  25. #include <linux/mmc/card.h>
  26. #include <linux/mmc/core.h>
  27. #include <linux/mmc/host.h>
  28. #include <linux/mmc/mmc.h>
  29. #include <linux/mmc/sd.h>
  30. #include <linux/mmc/sdio.h>
  31. #include <linux/mmc/slot-gpio.h>
  32. #include <linux/module.h>
  33. #include <linux/of_address.h>
  34. #include <linux/of_gpio.h>
  35. #include <linux/of_platform.h>
  36. #include <linux/platform_device.h>
  37. #include <linux/pm_runtime.h>
  38. #include <linux/regulator/consumer.h>
  39. #include <linux/reset.h>
  40. #include <linux/scatterlist.h>
  41. #include <linux/slab.h>
  42. #include <linux/spinlock.h>
  43. /* register offset definitions */
  44. #define SDXC_REG_GCTRL (0x00) /* SMC Global Control Register */
  45. #define SDXC_REG_CLKCR (0x04) /* SMC Clock Control Register */
  46. #define SDXC_REG_TMOUT (0x08) /* SMC Time Out Register */
  47. #define SDXC_REG_WIDTH (0x0C) /* SMC Bus Width Register */
  48. #define SDXC_REG_BLKSZ (0x10) /* SMC Block Size Register */
  49. #define SDXC_REG_BCNTR (0x14) /* SMC Byte Count Register */
  50. #define SDXC_REG_CMDR (0x18) /* SMC Command Register */
  51. #define SDXC_REG_CARG (0x1C) /* SMC Argument Register */
  52. #define SDXC_REG_RESP0 (0x20) /* SMC Response Register 0 */
  53. #define SDXC_REG_RESP1 (0x24) /* SMC Response Register 1 */
  54. #define SDXC_REG_RESP2 (0x28) /* SMC Response Register 2 */
  55. #define SDXC_REG_RESP3 (0x2C) /* SMC Response Register 3 */
  56. #define SDXC_REG_IMASK (0x30) /* SMC Interrupt Mask Register */
  57. #define SDXC_REG_MISTA (0x34) /* SMC Masked Interrupt Status Register */
  58. #define SDXC_REG_RINTR (0x38) /* SMC Raw Interrupt Status Register */
  59. #define SDXC_REG_STAS (0x3C) /* SMC Status Register */
  60. #define SDXC_REG_FTRGL (0x40) /* SMC FIFO Threshold Watermark Registe */
  61. #define SDXC_REG_FUNS (0x44) /* SMC Function Select Register */
  62. #define SDXC_REG_CBCR (0x48) /* SMC CIU Byte Count Register */
  63. #define SDXC_REG_BBCR (0x4C) /* SMC BIU Byte Count Register */
  64. #define SDXC_REG_DBGC (0x50) /* SMC Debug Enable Register */
  65. #define SDXC_REG_HWRST (0x78) /* SMC Card Hardware Reset for Register */
  66. #define SDXC_REG_DMAC (0x80) /* SMC IDMAC Control Register */
  67. #define SDXC_REG_DLBA (0x84) /* SMC IDMAC Descriptor List Base Addre */
  68. #define SDXC_REG_IDST (0x88) /* SMC IDMAC Status Register */
  69. #define SDXC_REG_IDIE (0x8C) /* SMC IDMAC Interrupt Enable Register */
  70. #define SDXC_REG_CHDA (0x90)
  71. #define SDXC_REG_CBDA (0x94)
  72. /* New registers introduced in A64 */
  73. #define SDXC_REG_A12A 0x058 /* SMC Auto Command 12 Register */
  74. #define SDXC_REG_SD_NTSR 0x05C /* SMC New Timing Set Register */
  75. #define SDXC_REG_DRV_DL 0x140 /* Drive Delay Control Register */
  76. #define SDXC_REG_SAMP_DL_REG 0x144 /* SMC sample delay control */
  77. #define SDXC_REG_DS_DL_REG 0x148 /* SMC data strobe delay control */
  78. #define mmc_readl(host, reg) \
  79. readl((host)->reg_base + SDXC_##reg)
  80. #define mmc_writel(host, reg, value) \
  81. writel((value), (host)->reg_base + SDXC_##reg)
  82. /* global control register bits */
  83. #define SDXC_SOFT_RESET BIT(0)
  84. #define SDXC_FIFO_RESET BIT(1)
  85. #define SDXC_DMA_RESET BIT(2)
  86. #define SDXC_INTERRUPT_ENABLE_BIT BIT(4)
  87. #define SDXC_DMA_ENABLE_BIT BIT(5)
  88. #define SDXC_DEBOUNCE_ENABLE_BIT BIT(8)
  89. #define SDXC_POSEDGE_LATCH_DATA BIT(9)
  90. #define SDXC_DDR_MODE BIT(10)
  91. #define SDXC_MEMORY_ACCESS_DONE BIT(29)
  92. #define SDXC_ACCESS_DONE_DIRECT BIT(30)
  93. #define SDXC_ACCESS_BY_AHB BIT(31)
  94. #define SDXC_ACCESS_BY_DMA (0 << 31)
  95. #define SDXC_HARDWARE_RESET \
  96. (SDXC_SOFT_RESET | SDXC_FIFO_RESET | SDXC_DMA_RESET)
  97. /* clock control bits */
  98. #define SDXC_MASK_DATA0 BIT(31)
  99. #define SDXC_CARD_CLOCK_ON BIT(16)
  100. #define SDXC_LOW_POWER_ON BIT(17)
  101. /* bus width */
  102. #define SDXC_WIDTH1 0
  103. #define SDXC_WIDTH4 1
  104. #define SDXC_WIDTH8 2
  105. /* smc command bits */
  106. #define SDXC_RESP_EXPIRE BIT(6)
  107. #define SDXC_LONG_RESPONSE BIT(7)
  108. #define SDXC_CHECK_RESPONSE_CRC BIT(8)
  109. #define SDXC_DATA_EXPIRE BIT(9)
  110. #define SDXC_WRITE BIT(10)
  111. #define SDXC_SEQUENCE_MODE BIT(11)
  112. #define SDXC_SEND_AUTO_STOP BIT(12)
  113. #define SDXC_WAIT_PRE_OVER BIT(13)
  114. #define SDXC_STOP_ABORT_CMD BIT(14)
  115. #define SDXC_SEND_INIT_SEQUENCE BIT(15)
  116. #define SDXC_UPCLK_ONLY BIT(21)
  117. #define SDXC_READ_CEATA_DEV BIT(22)
  118. #define SDXC_CCS_EXPIRE BIT(23)
  119. #define SDXC_ENABLE_BIT_BOOT BIT(24)
  120. #define SDXC_ALT_BOOT_OPTIONS BIT(25)
  121. #define SDXC_BOOT_ACK_EXPIRE BIT(26)
  122. #define SDXC_BOOT_ABORT BIT(27)
  123. #define SDXC_VOLTAGE_SWITCH BIT(28)
  124. #define SDXC_USE_HOLD_REGISTER BIT(29)
  125. #define SDXC_START BIT(31)
  126. /* interrupt bits */
  127. #define SDXC_RESP_ERROR BIT(1)
  128. #define SDXC_COMMAND_DONE BIT(2)
  129. #define SDXC_DATA_OVER BIT(3)
  130. #define SDXC_TX_DATA_REQUEST BIT(4)
  131. #define SDXC_RX_DATA_REQUEST BIT(5)
  132. #define SDXC_RESP_CRC_ERROR BIT(6)
  133. #define SDXC_DATA_CRC_ERROR BIT(7)
  134. #define SDXC_RESP_TIMEOUT BIT(8)
  135. #define SDXC_DATA_TIMEOUT BIT(9)
  136. #define SDXC_VOLTAGE_CHANGE_DONE BIT(10)
  137. #define SDXC_FIFO_RUN_ERROR BIT(11)
  138. #define SDXC_HARD_WARE_LOCKED BIT(12)
  139. #define SDXC_START_BIT_ERROR BIT(13)
  140. #define SDXC_AUTO_COMMAND_DONE BIT(14)
  141. #define SDXC_END_BIT_ERROR BIT(15)
  142. #define SDXC_SDIO_INTERRUPT BIT(16)
  143. #define SDXC_CARD_INSERT BIT(30)
  144. #define SDXC_CARD_REMOVE BIT(31)
  145. #define SDXC_INTERRUPT_ERROR_BIT \
  146. (SDXC_RESP_ERROR | SDXC_RESP_CRC_ERROR | SDXC_DATA_CRC_ERROR | \
  147. SDXC_RESP_TIMEOUT | SDXC_DATA_TIMEOUT | SDXC_FIFO_RUN_ERROR | \
  148. SDXC_HARD_WARE_LOCKED | SDXC_START_BIT_ERROR | SDXC_END_BIT_ERROR)
  149. #define SDXC_INTERRUPT_DONE_BIT \
  150. (SDXC_AUTO_COMMAND_DONE | SDXC_DATA_OVER | \
  151. SDXC_COMMAND_DONE | SDXC_VOLTAGE_CHANGE_DONE)
  152. /* status */
  153. #define SDXC_RXWL_FLAG BIT(0)
  154. #define SDXC_TXWL_FLAG BIT(1)
  155. #define SDXC_FIFO_EMPTY BIT(2)
  156. #define SDXC_FIFO_FULL BIT(3)
  157. #define SDXC_CARD_PRESENT BIT(8)
  158. #define SDXC_CARD_DATA_BUSY BIT(9)
  159. #define SDXC_DATA_FSM_BUSY BIT(10)
  160. #define SDXC_DMA_REQUEST BIT(31)
  161. #define SDXC_FIFO_SIZE 16
  162. /* Function select */
  163. #define SDXC_CEATA_ON (0xceaa << 16)
  164. #define SDXC_SEND_IRQ_RESPONSE BIT(0)
  165. #define SDXC_SDIO_READ_WAIT BIT(1)
  166. #define SDXC_ABORT_READ_DATA BIT(2)
  167. #define SDXC_SEND_CCSD BIT(8)
  168. #define SDXC_SEND_AUTO_STOPCCSD BIT(9)
  169. #define SDXC_CEATA_DEV_IRQ_ENABLE BIT(10)
  170. /* IDMA controller bus mod bit field */
  171. #define SDXC_IDMAC_SOFT_RESET BIT(0)
  172. #define SDXC_IDMAC_FIX_BURST BIT(1)
  173. #define SDXC_IDMAC_IDMA_ON BIT(7)
  174. #define SDXC_IDMAC_REFETCH_DES BIT(31)
  175. /* IDMA status bit field */
  176. #define SDXC_IDMAC_TRANSMIT_INTERRUPT BIT(0)
  177. #define SDXC_IDMAC_RECEIVE_INTERRUPT BIT(1)
  178. #define SDXC_IDMAC_FATAL_BUS_ERROR BIT(2)
  179. #define SDXC_IDMAC_DESTINATION_INVALID BIT(4)
  180. #define SDXC_IDMAC_CARD_ERROR_SUM BIT(5)
  181. #define SDXC_IDMAC_NORMAL_INTERRUPT_SUM BIT(8)
  182. #define SDXC_IDMAC_ABNORMAL_INTERRUPT_SUM BIT(9)
  183. #define SDXC_IDMAC_HOST_ABORT_INTERRUPT BIT(10)
  184. #define SDXC_IDMAC_IDLE (0 << 13)
  185. #define SDXC_IDMAC_SUSPEND (1 << 13)
  186. #define SDXC_IDMAC_DESC_READ (2 << 13)
  187. #define SDXC_IDMAC_DESC_CHECK (3 << 13)
  188. #define SDXC_IDMAC_READ_REQUEST_WAIT (4 << 13)
  189. #define SDXC_IDMAC_WRITE_REQUEST_WAIT (5 << 13)
  190. #define SDXC_IDMAC_READ (6 << 13)
  191. #define SDXC_IDMAC_WRITE (7 << 13)
  192. #define SDXC_IDMAC_DESC_CLOSE (8 << 13)
  193. /*
  194. * If the idma-des-size-bits of property is ie 13, bufsize bits are:
  195. * Bits 0-12: buf1 size
  196. * Bits 13-25: buf2 size
  197. * Bits 26-31: not used
  198. * Since we only ever set buf1 size, we can simply store it directly.
  199. */
  200. #define SDXC_IDMAC_DES0_DIC BIT(1) /* disable interrupt on completion */
  201. #define SDXC_IDMAC_DES0_LD BIT(2) /* last descriptor */
  202. #define SDXC_IDMAC_DES0_FD BIT(3) /* first descriptor */
  203. #define SDXC_IDMAC_DES0_CH BIT(4) /* chain mode */
  204. #define SDXC_IDMAC_DES0_ER BIT(5) /* end of ring */
  205. #define SDXC_IDMAC_DES0_CES BIT(30) /* card error summary */
  206. #define SDXC_IDMAC_DES0_OWN BIT(31) /* 1-idma owns it, 0-host owns it */
  207. #define SDXC_CLK_400K 0
  208. #define SDXC_CLK_25M 1
  209. #define SDXC_CLK_50M 2
  210. #define SDXC_CLK_50M_DDR 3
  211. #define SDXC_CLK_50M_DDR_8BIT 4
  212. #define SDXC_2X_TIMING_MODE BIT(31)
  213. #define SDXC_CAL_START BIT(15)
  214. #define SDXC_CAL_DONE BIT(14)
  215. #define SDXC_CAL_DL_SHIFT 8
  216. #define SDXC_CAL_DL_SW_EN BIT(7)
  217. #define SDXC_CAL_DL_SW_SHIFT 0
  218. #define SDXC_CAL_DL_MASK 0x3f
  219. #define SDXC_CAL_TIMEOUT 3 /* in seconds, 3s is enough*/
  220. struct sunxi_mmc_clk_delay {
  221. u32 output;
  222. u32 sample;
  223. };
  224. struct sunxi_idma_des {
  225. __le32 config;
  226. __le32 buf_size;
  227. __le32 buf_addr_ptr1;
  228. __le32 buf_addr_ptr2;
  229. };
  230. struct sunxi_mmc_cfg {
  231. u32 idma_des_size_bits;
  232. const struct sunxi_mmc_clk_delay *clk_delays;
  233. /* does the IP block support autocalibration? */
  234. bool can_calibrate;
  235. /* Does DATA0 needs to be masked while the clock is updated */
  236. bool mask_data0;
  237. /* hardware only supports new timing mode */
  238. bool needs_new_timings;
  239. /* hardware can switch between old and new timing modes */
  240. bool has_timings_switch;
  241. };
  242. struct sunxi_mmc_host {
  243. struct device *dev;
  244. struct mmc_host *mmc;
  245. struct reset_control *reset;
  246. const struct sunxi_mmc_cfg *cfg;
  247. /* IO mapping base */
  248. void __iomem *reg_base;
  249. /* clock management */
  250. struct clk *clk_ahb;
  251. struct clk *clk_mmc;
  252. struct clk *clk_sample;
  253. struct clk *clk_output;
  254. /* irq */
  255. spinlock_t lock;
  256. int irq;
  257. u32 int_sum;
  258. u32 sdio_imask;
  259. /* dma */
  260. dma_addr_t sg_dma;
  261. void *sg_cpu;
  262. bool wait_dma;
  263. struct mmc_request *mrq;
  264. struct mmc_request *manual_stop_mrq;
  265. int ferror;
  266. /* vqmmc */
  267. bool vqmmc_enabled;
  268. /* timings */
  269. bool use_new_timings;
  270. };
  271. static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host)
  272. {
  273. unsigned long expire = jiffies + msecs_to_jiffies(250);
  274. u32 rval;
  275. mmc_writel(host, REG_GCTRL, SDXC_HARDWARE_RESET);
  276. do {
  277. rval = mmc_readl(host, REG_GCTRL);
  278. } while (time_before(jiffies, expire) && (rval & SDXC_HARDWARE_RESET));
  279. if (rval & SDXC_HARDWARE_RESET) {
  280. dev_err(mmc_dev(host->mmc), "fatal err reset timeout\n");
  281. return -EIO;
  282. }
  283. return 0;
  284. }
  285. static int sunxi_mmc_init_host(struct sunxi_mmc_host *host)
  286. {
  287. u32 rval;
  288. if (sunxi_mmc_reset_host(host))
  289. return -EIO;
  290. /*
  291. * Burst 8 transfers, RX trigger level: 7, TX trigger level: 8
  292. *
  293. * TODO: sun9i has a larger FIFO and supports higher trigger values
  294. */
  295. mmc_writel(host, REG_FTRGL, 0x20070008);
  296. /* Maximum timeout value */
  297. mmc_writel(host, REG_TMOUT, 0xffffffff);
  298. /* Unmask SDIO interrupt if needed */
  299. mmc_writel(host, REG_IMASK, host->sdio_imask);
  300. /* Clear all pending interrupts */
  301. mmc_writel(host, REG_RINTR, 0xffffffff);
  302. /* Debug register? undocumented */
  303. mmc_writel(host, REG_DBGC, 0xdeb);
  304. /* Enable CEATA support */
  305. mmc_writel(host, REG_FUNS, SDXC_CEATA_ON);
  306. /* Set DMA descriptor list base address */
  307. mmc_writel(host, REG_DLBA, host->sg_dma);
  308. rval = mmc_readl(host, REG_GCTRL);
  309. rval |= SDXC_INTERRUPT_ENABLE_BIT;
  310. /* Undocumented, but found in Allwinner code */
  311. rval &= ~SDXC_ACCESS_DONE_DIRECT;
  312. mmc_writel(host, REG_GCTRL, rval);
  313. return 0;
  314. }
  315. static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host,
  316. struct mmc_data *data)
  317. {
  318. struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu;
  319. dma_addr_t next_desc = host->sg_dma;
  320. int i, max_len = (1 << host->cfg->idma_des_size_bits);
  321. for (i = 0; i < data->sg_len; i++) {
  322. pdes[i].config = cpu_to_le32(SDXC_IDMAC_DES0_CH |
  323. SDXC_IDMAC_DES0_OWN |
  324. SDXC_IDMAC_DES0_DIC);
  325. if (data->sg[i].length == max_len)
  326. pdes[i].buf_size = 0; /* 0 == max_len */
  327. else
  328. pdes[i].buf_size = cpu_to_le32(data->sg[i].length);
  329. next_desc += sizeof(struct sunxi_idma_des);
  330. pdes[i].buf_addr_ptr1 =
  331. cpu_to_le32(sg_dma_address(&data->sg[i]));
  332. pdes[i].buf_addr_ptr2 = cpu_to_le32((u32)next_desc);
  333. }
  334. pdes[0].config |= cpu_to_le32(SDXC_IDMAC_DES0_FD);
  335. pdes[i - 1].config |= cpu_to_le32(SDXC_IDMAC_DES0_LD |
  336. SDXC_IDMAC_DES0_ER);
  337. pdes[i - 1].config &= cpu_to_le32(~SDXC_IDMAC_DES0_DIC);
  338. pdes[i - 1].buf_addr_ptr2 = 0;
  339. /*
  340. * Avoid the io-store starting the idmac hitting io-mem before the
  341. * descriptors hit the main-mem.
  342. */
  343. wmb();
  344. }
  345. static int sunxi_mmc_map_dma(struct sunxi_mmc_host *host,
  346. struct mmc_data *data)
  347. {
  348. u32 i, dma_len;
  349. struct scatterlist *sg;
  350. dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
  351. mmc_get_dma_dir(data));
  352. if (dma_len == 0) {
  353. dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n");
  354. return -ENOMEM;
  355. }
  356. for_each_sg(data->sg, sg, data->sg_len, i) {
  357. if (sg->offset & 3 || sg->length & 3) {
  358. dev_err(mmc_dev(host->mmc),
  359. "unaligned scatterlist: os %x length %d\n",
  360. sg->offset, sg->length);
  361. return -EINVAL;
  362. }
  363. }
  364. return 0;
  365. }
  366. static void sunxi_mmc_start_dma(struct sunxi_mmc_host *host,
  367. struct mmc_data *data)
  368. {
  369. u32 rval;
  370. sunxi_mmc_init_idma_des(host, data);
  371. rval = mmc_readl(host, REG_GCTRL);
  372. rval |= SDXC_DMA_ENABLE_BIT;
  373. mmc_writel(host, REG_GCTRL, rval);
  374. rval |= SDXC_DMA_RESET;
  375. mmc_writel(host, REG_GCTRL, rval);
  376. mmc_writel(host, REG_DMAC, SDXC_IDMAC_SOFT_RESET);
  377. if (!(data->flags & MMC_DATA_WRITE))
  378. mmc_writel(host, REG_IDIE, SDXC_IDMAC_RECEIVE_INTERRUPT);
  379. mmc_writel(host, REG_DMAC,
  380. SDXC_IDMAC_FIX_BURST | SDXC_IDMAC_IDMA_ON);
  381. }
  382. static void sunxi_mmc_send_manual_stop(struct sunxi_mmc_host *host,
  383. struct mmc_request *req)
  384. {
  385. u32 arg, cmd_val, ri;
  386. unsigned long expire = jiffies + msecs_to_jiffies(1000);
  387. cmd_val = SDXC_START | SDXC_RESP_EXPIRE |
  388. SDXC_STOP_ABORT_CMD | SDXC_CHECK_RESPONSE_CRC;
  389. if (req->cmd->opcode == SD_IO_RW_EXTENDED) {
  390. cmd_val |= SD_IO_RW_DIRECT;
  391. arg = (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
  392. ((req->cmd->arg >> 28) & 0x7);
  393. } else {
  394. cmd_val |= MMC_STOP_TRANSMISSION;
  395. arg = 0;
  396. }
  397. mmc_writel(host, REG_CARG, arg);
  398. mmc_writel(host, REG_CMDR, cmd_val);
  399. do {
  400. ri = mmc_readl(host, REG_RINTR);
  401. } while (!(ri & (SDXC_COMMAND_DONE | SDXC_INTERRUPT_ERROR_BIT)) &&
  402. time_before(jiffies, expire));
  403. if (!(ri & SDXC_COMMAND_DONE) || (ri & SDXC_INTERRUPT_ERROR_BIT)) {
  404. dev_err(mmc_dev(host->mmc), "send stop command failed\n");
  405. if (req->stop)
  406. req->stop->resp[0] = -ETIMEDOUT;
  407. } else {
  408. if (req->stop)
  409. req->stop->resp[0] = mmc_readl(host, REG_RESP0);
  410. }
  411. mmc_writel(host, REG_RINTR, 0xffff);
  412. }
  413. static void sunxi_mmc_dump_errinfo(struct sunxi_mmc_host *host)
  414. {
  415. struct mmc_command *cmd = host->mrq->cmd;
  416. struct mmc_data *data = host->mrq->data;
  417. /* For some cmds timeout is normal with sd/mmc cards */
  418. if ((host->int_sum & SDXC_INTERRUPT_ERROR_BIT) ==
  419. SDXC_RESP_TIMEOUT && (cmd->opcode == SD_IO_SEND_OP_COND ||
  420. cmd->opcode == SD_IO_RW_DIRECT))
  421. return;
  422. dev_dbg(mmc_dev(host->mmc),
  423. "smc %d err, cmd %d,%s%s%s%s%s%s%s%s%s%s !!\n",
  424. host->mmc->index, cmd->opcode,
  425. data ? (data->flags & MMC_DATA_WRITE ? " WR" : " RD") : "",
  426. host->int_sum & SDXC_RESP_ERROR ? " RE" : "",
  427. host->int_sum & SDXC_RESP_CRC_ERROR ? " RCE" : "",
  428. host->int_sum & SDXC_DATA_CRC_ERROR ? " DCE" : "",
  429. host->int_sum & SDXC_RESP_TIMEOUT ? " RTO" : "",
  430. host->int_sum & SDXC_DATA_TIMEOUT ? " DTO" : "",
  431. host->int_sum & SDXC_FIFO_RUN_ERROR ? " FE" : "",
  432. host->int_sum & SDXC_HARD_WARE_LOCKED ? " HL" : "",
  433. host->int_sum & SDXC_START_BIT_ERROR ? " SBE" : "",
  434. host->int_sum & SDXC_END_BIT_ERROR ? " EBE" : ""
  435. );
  436. }
  437. /* Called in interrupt context! */
  438. static irqreturn_t sunxi_mmc_finalize_request(struct sunxi_mmc_host *host)
  439. {
  440. struct mmc_request *mrq = host->mrq;
  441. struct mmc_data *data = mrq->data;
  442. u32 rval;
  443. mmc_writel(host, REG_IMASK, host->sdio_imask);
  444. mmc_writel(host, REG_IDIE, 0);
  445. if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) {
  446. sunxi_mmc_dump_errinfo(host);
  447. mrq->cmd->error = -ETIMEDOUT;
  448. if (data) {
  449. data->error = -ETIMEDOUT;
  450. host->manual_stop_mrq = mrq;
  451. }
  452. if (mrq->stop)
  453. mrq->stop->error = -ETIMEDOUT;
  454. } else {
  455. if (mrq->cmd->flags & MMC_RSP_136) {
  456. mrq->cmd->resp[0] = mmc_readl(host, REG_RESP3);
  457. mrq->cmd->resp[1] = mmc_readl(host, REG_RESP2);
  458. mrq->cmd->resp[2] = mmc_readl(host, REG_RESP1);
  459. mrq->cmd->resp[3] = mmc_readl(host, REG_RESP0);
  460. } else {
  461. mrq->cmd->resp[0] = mmc_readl(host, REG_RESP0);
  462. }
  463. if (data)
  464. data->bytes_xfered = data->blocks * data->blksz;
  465. }
  466. if (data) {
  467. mmc_writel(host, REG_IDST, 0x337);
  468. mmc_writel(host, REG_DMAC, 0);
  469. rval = mmc_readl(host, REG_GCTRL);
  470. rval |= SDXC_DMA_RESET;
  471. mmc_writel(host, REG_GCTRL, rval);
  472. rval &= ~SDXC_DMA_ENABLE_BIT;
  473. mmc_writel(host, REG_GCTRL, rval);
  474. rval |= SDXC_FIFO_RESET;
  475. mmc_writel(host, REG_GCTRL, rval);
  476. dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
  477. mmc_get_dma_dir(data));
  478. }
  479. mmc_writel(host, REG_RINTR, 0xffff);
  480. host->mrq = NULL;
  481. host->int_sum = 0;
  482. host->wait_dma = false;
  483. return host->manual_stop_mrq ? IRQ_WAKE_THREAD : IRQ_HANDLED;
  484. }
  485. static irqreturn_t sunxi_mmc_irq(int irq, void *dev_id)
  486. {
  487. struct sunxi_mmc_host *host = dev_id;
  488. struct mmc_request *mrq;
  489. u32 msk_int, idma_int;
  490. bool finalize = false;
  491. bool sdio_int = false;
  492. irqreturn_t ret = IRQ_HANDLED;
  493. spin_lock(&host->lock);
  494. idma_int = mmc_readl(host, REG_IDST);
  495. msk_int = mmc_readl(host, REG_MISTA);
  496. dev_dbg(mmc_dev(host->mmc), "irq: rq %p mi %08x idi %08x\n",
  497. host->mrq, msk_int, idma_int);
  498. mrq = host->mrq;
  499. if (mrq) {
  500. if (idma_int & SDXC_IDMAC_RECEIVE_INTERRUPT)
  501. host->wait_dma = false;
  502. host->int_sum |= msk_int;
  503. /* Wait for COMMAND_DONE on RESPONSE_TIMEOUT before finalize */
  504. if ((host->int_sum & SDXC_RESP_TIMEOUT) &&
  505. !(host->int_sum & SDXC_COMMAND_DONE))
  506. mmc_writel(host, REG_IMASK,
  507. host->sdio_imask | SDXC_COMMAND_DONE);
  508. /* Don't wait for dma on error */
  509. else if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT)
  510. finalize = true;
  511. else if ((host->int_sum & SDXC_INTERRUPT_DONE_BIT) &&
  512. !host->wait_dma)
  513. finalize = true;
  514. }
  515. if (msk_int & SDXC_SDIO_INTERRUPT)
  516. sdio_int = true;
  517. mmc_writel(host, REG_RINTR, msk_int);
  518. mmc_writel(host, REG_IDST, idma_int);
  519. if (finalize)
  520. ret = sunxi_mmc_finalize_request(host);
  521. spin_unlock(&host->lock);
  522. if (finalize && ret == IRQ_HANDLED)
  523. mmc_request_done(host->mmc, mrq);
  524. if (sdio_int)
  525. mmc_signal_sdio_irq(host->mmc);
  526. return ret;
  527. }
  528. static irqreturn_t sunxi_mmc_handle_manual_stop(int irq, void *dev_id)
  529. {
  530. struct sunxi_mmc_host *host = dev_id;
  531. struct mmc_request *mrq;
  532. unsigned long iflags;
  533. spin_lock_irqsave(&host->lock, iflags);
  534. mrq = host->manual_stop_mrq;
  535. spin_unlock_irqrestore(&host->lock, iflags);
  536. if (!mrq) {
  537. dev_err(mmc_dev(host->mmc), "no request for manual stop\n");
  538. return IRQ_HANDLED;
  539. }
  540. dev_err(mmc_dev(host->mmc), "data error, sending stop command\n");
  541. /*
  542. * We will never have more than one outstanding request,
  543. * and we do not complete the request until after
  544. * we've cleared host->manual_stop_mrq so we do not need to
  545. * spin lock this function.
  546. * Additionally we have wait states within this function
  547. * so having it in a lock is a very bad idea.
  548. */
  549. sunxi_mmc_send_manual_stop(host, mrq);
  550. spin_lock_irqsave(&host->lock, iflags);
  551. host->manual_stop_mrq = NULL;
  552. spin_unlock_irqrestore(&host->lock, iflags);
  553. mmc_request_done(host->mmc, mrq);
  554. return IRQ_HANDLED;
  555. }
  556. static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en)
  557. {
  558. unsigned long expire = jiffies + msecs_to_jiffies(750);
  559. u32 rval;
  560. dev_dbg(mmc_dev(host->mmc), "%sabling the clock\n",
  561. oclk_en ? "en" : "dis");
  562. rval = mmc_readl(host, REG_CLKCR);
  563. rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON | SDXC_MASK_DATA0);
  564. if (oclk_en)
  565. rval |= SDXC_CARD_CLOCK_ON;
  566. if (host->cfg->mask_data0)
  567. rval |= SDXC_MASK_DATA0;
  568. mmc_writel(host, REG_CLKCR, rval);
  569. rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER;
  570. mmc_writel(host, REG_CMDR, rval);
  571. do {
  572. rval = mmc_readl(host, REG_CMDR);
  573. } while (time_before(jiffies, expire) && (rval & SDXC_START));
  574. /* clear irq status bits set by the command */
  575. mmc_writel(host, REG_RINTR,
  576. mmc_readl(host, REG_RINTR) & ~SDXC_SDIO_INTERRUPT);
  577. if (rval & SDXC_START) {
  578. dev_err(mmc_dev(host->mmc), "fatal err update clk timeout\n");
  579. return -EIO;
  580. }
  581. if (host->cfg->mask_data0) {
  582. rval = mmc_readl(host, REG_CLKCR);
  583. mmc_writel(host, REG_CLKCR, rval & ~SDXC_MASK_DATA0);
  584. }
  585. return 0;
  586. }
  587. static int sunxi_mmc_calibrate(struct sunxi_mmc_host *host, int reg_off)
  588. {
  589. if (!host->cfg->can_calibrate)
  590. return 0;
  591. /*
  592. * FIXME:
  593. * This is not clear how the calibration is supposed to work
  594. * yet. The best rate have been obtained by simply setting the
  595. * delay to 0, as Allwinner does in its BSP.
  596. *
  597. * The only mode that doesn't have such a delay is HS400, that
  598. * is in itself a TODO.
  599. */
  600. writel(SDXC_CAL_DL_SW_EN, host->reg_base + reg_off);
  601. return 0;
  602. }
  603. static int sunxi_mmc_clk_set_phase(struct sunxi_mmc_host *host,
  604. struct mmc_ios *ios, u32 rate)
  605. {
  606. int index;
  607. /* clk controller delays not used under new timings mode */
  608. if (host->use_new_timings)
  609. return 0;
  610. /* some old controllers don't support delays */
  611. if (!host->cfg->clk_delays)
  612. return 0;
  613. /* determine delays */
  614. if (rate <= 400000) {
  615. index = SDXC_CLK_400K;
  616. } else if (rate <= 25000000) {
  617. index = SDXC_CLK_25M;
  618. } else if (rate <= 52000000) {
  619. if (ios->timing != MMC_TIMING_UHS_DDR50 &&
  620. ios->timing != MMC_TIMING_MMC_DDR52) {
  621. index = SDXC_CLK_50M;
  622. } else if (ios->bus_width == MMC_BUS_WIDTH_8) {
  623. index = SDXC_CLK_50M_DDR_8BIT;
  624. } else {
  625. index = SDXC_CLK_50M_DDR;
  626. }
  627. } else {
  628. dev_dbg(mmc_dev(host->mmc), "Invalid clock... returning\n");
  629. return -EINVAL;
  630. }
  631. clk_set_phase(host->clk_sample, host->cfg->clk_delays[index].sample);
  632. clk_set_phase(host->clk_output, host->cfg->clk_delays[index].output);
  633. return 0;
  634. }
  635. static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
  636. struct mmc_ios *ios)
  637. {
  638. struct mmc_host *mmc = host->mmc;
  639. long rate;
  640. u32 rval, clock = ios->clock, div = 1;
  641. int ret;
  642. ret = sunxi_mmc_oclk_onoff(host, 0);
  643. if (ret)
  644. return ret;
  645. /* Our clock is gated now */
  646. mmc->actual_clock = 0;
  647. if (!ios->clock)
  648. return 0;
  649. /*
  650. * Under the old timing mode, 8 bit DDR requires the module
  651. * clock to be double the card clock. Under the new timing
  652. * mode, all DDR modes require a doubled module clock.
  653. *
  654. * We currently only support the standard MMC DDR52 mode.
  655. * This block should be updated once support for other DDR
  656. * modes is added.
  657. */
  658. if (ios->timing == MMC_TIMING_MMC_DDR52 &&
  659. (host->use_new_timings ||
  660. ios->bus_width == MMC_BUS_WIDTH_8)) {
  661. div = 2;
  662. clock <<= 1;
  663. }
  664. if (host->use_new_timings && host->cfg->has_timings_switch) {
  665. ret = sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true);
  666. if (ret) {
  667. dev_err(mmc_dev(mmc),
  668. "error setting new timing mode\n");
  669. return ret;
  670. }
  671. }
  672. rate = clk_round_rate(host->clk_mmc, clock);
  673. if (rate < 0) {
  674. dev_err(mmc_dev(mmc), "error rounding clk to %d: %ld\n",
  675. clock, rate);
  676. return rate;
  677. }
  678. dev_dbg(mmc_dev(mmc), "setting clk to %d, rounded %ld\n",
  679. clock, rate);
  680. /* setting clock rate */
  681. ret = clk_set_rate(host->clk_mmc, rate);
  682. if (ret) {
  683. dev_err(mmc_dev(mmc), "error setting clk to %ld: %d\n",
  684. rate, ret);
  685. return ret;
  686. }
  687. /* set internal divider */
  688. rval = mmc_readl(host, REG_CLKCR);
  689. rval &= ~0xff;
  690. rval |= div - 1;
  691. mmc_writel(host, REG_CLKCR, rval);
  692. /* update card clock rate to account for internal divider */
  693. rate /= div;
  694. if (host->use_new_timings) {
  695. /* Don't touch the delay bits */
  696. rval = mmc_readl(host, REG_SD_NTSR);
  697. rval |= SDXC_2X_TIMING_MODE;
  698. mmc_writel(host, REG_SD_NTSR, rval);
  699. }
  700. /* sunxi_mmc_clk_set_phase expects the actual card clock rate */
  701. ret = sunxi_mmc_clk_set_phase(host, ios, rate);
  702. if (ret)
  703. return ret;
  704. ret = sunxi_mmc_calibrate(host, SDXC_REG_SAMP_DL_REG);
  705. if (ret)
  706. return ret;
  707. /*
  708. * FIXME:
  709. *
  710. * In HS400 we'll also need to calibrate the data strobe
  711. * signal. This should only happen on the MMC2 controller (at
  712. * least on the A64).
  713. */
  714. ret = sunxi_mmc_oclk_onoff(host, 1);
  715. if (ret)
  716. return ret;
  717. /* And we just enabled our clock back */
  718. mmc->actual_clock = rate;
  719. return 0;
  720. }
  721. static void sunxi_mmc_set_bus_width(struct sunxi_mmc_host *host,
  722. unsigned char width)
  723. {
  724. switch (width) {
  725. case MMC_BUS_WIDTH_1:
  726. mmc_writel(host, REG_WIDTH, SDXC_WIDTH1);
  727. break;
  728. case MMC_BUS_WIDTH_4:
  729. mmc_writel(host, REG_WIDTH, SDXC_WIDTH4);
  730. break;
  731. case MMC_BUS_WIDTH_8:
  732. mmc_writel(host, REG_WIDTH, SDXC_WIDTH8);
  733. break;
  734. }
  735. }
  736. static void sunxi_mmc_set_clk(struct sunxi_mmc_host *host, struct mmc_ios *ios)
  737. {
  738. u32 rval;
  739. /* set ddr mode */
  740. rval = mmc_readl(host, REG_GCTRL);
  741. if (ios->timing == MMC_TIMING_UHS_DDR50 ||
  742. ios->timing == MMC_TIMING_MMC_DDR52)
  743. rval |= SDXC_DDR_MODE;
  744. else
  745. rval &= ~SDXC_DDR_MODE;
  746. mmc_writel(host, REG_GCTRL, rval);
  747. host->ferror = sunxi_mmc_clk_set_rate(host, ios);
  748. /* Android code had a usleep_range(50000, 55000); here */
  749. }
  750. static void sunxi_mmc_card_power(struct sunxi_mmc_host *host,
  751. struct mmc_ios *ios)
  752. {
  753. struct mmc_host *mmc = host->mmc;
  754. switch (ios->power_mode) {
  755. case MMC_POWER_UP:
  756. dev_dbg(mmc_dev(mmc), "Powering card up\n");
  757. if (!IS_ERR(mmc->supply.vmmc)) {
  758. host->ferror = mmc_regulator_set_ocr(mmc,
  759. mmc->supply.vmmc,
  760. ios->vdd);
  761. if (host->ferror)
  762. return;
  763. }
  764. if (!IS_ERR(mmc->supply.vqmmc)) {
  765. host->ferror = regulator_enable(mmc->supply.vqmmc);
  766. if (host->ferror) {
  767. dev_err(mmc_dev(mmc),
  768. "failed to enable vqmmc\n");
  769. return;
  770. }
  771. host->vqmmc_enabled = true;
  772. }
  773. break;
  774. case MMC_POWER_OFF:
  775. dev_dbg(mmc_dev(mmc), "Powering card off\n");
  776. if (!IS_ERR(mmc->supply.vmmc))
  777. mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
  778. if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled)
  779. regulator_disable(mmc->supply.vqmmc);
  780. host->vqmmc_enabled = false;
  781. break;
  782. default:
  783. dev_dbg(mmc_dev(mmc), "Ignoring unknown card power state\n");
  784. break;
  785. }
  786. }
  787. static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  788. {
  789. struct sunxi_mmc_host *host = mmc_priv(mmc);
  790. sunxi_mmc_card_power(host, ios);
  791. sunxi_mmc_set_bus_width(host, ios->bus_width);
  792. sunxi_mmc_set_clk(host, ios);
  793. }
  794. static int sunxi_mmc_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
  795. {
  796. /* vqmmc regulator is available */
  797. if (!IS_ERR(mmc->supply.vqmmc))
  798. return mmc_regulator_set_vqmmc(mmc, ios);
  799. /* no vqmmc regulator, assume fixed regulator at 3/3.3V */
  800. if (mmc->ios.signal_voltage == MMC_SIGNAL_VOLTAGE_330)
  801. return 0;
  802. return -EINVAL;
  803. }
  804. static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
  805. {
  806. struct sunxi_mmc_host *host = mmc_priv(mmc);
  807. unsigned long flags;
  808. u32 imask;
  809. if (enable)
  810. pm_runtime_get_noresume(host->dev);
  811. spin_lock_irqsave(&host->lock, flags);
  812. imask = mmc_readl(host, REG_IMASK);
  813. if (enable) {
  814. host->sdio_imask = SDXC_SDIO_INTERRUPT;
  815. imask |= SDXC_SDIO_INTERRUPT;
  816. } else {
  817. host->sdio_imask = 0;
  818. imask &= ~SDXC_SDIO_INTERRUPT;
  819. }
  820. mmc_writel(host, REG_IMASK, imask);
  821. spin_unlock_irqrestore(&host->lock, flags);
  822. if (!enable)
  823. pm_runtime_put_noidle(host->mmc->parent);
  824. }
  825. static void sunxi_mmc_hw_reset(struct mmc_host *mmc)
  826. {
  827. struct sunxi_mmc_host *host = mmc_priv(mmc);
  828. mmc_writel(host, REG_HWRST, 0);
  829. udelay(10);
  830. mmc_writel(host, REG_HWRST, 1);
  831. udelay(300);
  832. }
  833. static void sunxi_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
  834. {
  835. struct sunxi_mmc_host *host = mmc_priv(mmc);
  836. struct mmc_command *cmd = mrq->cmd;
  837. struct mmc_data *data = mrq->data;
  838. unsigned long iflags;
  839. u32 imask = SDXC_INTERRUPT_ERROR_BIT;
  840. u32 cmd_val = SDXC_START | (cmd->opcode & 0x3f);
  841. bool wait_dma = host->wait_dma;
  842. int ret;
  843. /* Check for set_ios errors (should never happen) */
  844. if (host->ferror) {
  845. mrq->cmd->error = host->ferror;
  846. mmc_request_done(mmc, mrq);
  847. return;
  848. }
  849. if (data) {
  850. ret = sunxi_mmc_map_dma(host, data);
  851. if (ret < 0) {
  852. dev_err(mmc_dev(mmc), "map DMA failed\n");
  853. cmd->error = ret;
  854. data->error = ret;
  855. mmc_request_done(mmc, mrq);
  856. return;
  857. }
  858. }
  859. if (cmd->opcode == MMC_GO_IDLE_STATE) {
  860. cmd_val |= SDXC_SEND_INIT_SEQUENCE;
  861. imask |= SDXC_COMMAND_DONE;
  862. }
  863. if (cmd->flags & MMC_RSP_PRESENT) {
  864. cmd_val |= SDXC_RESP_EXPIRE;
  865. if (cmd->flags & MMC_RSP_136)
  866. cmd_val |= SDXC_LONG_RESPONSE;
  867. if (cmd->flags & MMC_RSP_CRC)
  868. cmd_val |= SDXC_CHECK_RESPONSE_CRC;
  869. if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) {
  870. cmd_val |= SDXC_DATA_EXPIRE | SDXC_WAIT_PRE_OVER;
  871. if (cmd->data->stop) {
  872. imask |= SDXC_AUTO_COMMAND_DONE;
  873. cmd_val |= SDXC_SEND_AUTO_STOP;
  874. } else {
  875. imask |= SDXC_DATA_OVER;
  876. }
  877. if (cmd->data->flags & MMC_DATA_WRITE)
  878. cmd_val |= SDXC_WRITE;
  879. else
  880. wait_dma = true;
  881. } else {
  882. imask |= SDXC_COMMAND_DONE;
  883. }
  884. } else {
  885. imask |= SDXC_COMMAND_DONE;
  886. }
  887. dev_dbg(mmc_dev(mmc), "cmd %d(%08x) arg %x ie 0x%08x len %d\n",
  888. cmd_val & 0x3f, cmd_val, cmd->arg, imask,
  889. mrq->data ? mrq->data->blksz * mrq->data->blocks : 0);
  890. spin_lock_irqsave(&host->lock, iflags);
  891. if (host->mrq || host->manual_stop_mrq) {
  892. spin_unlock_irqrestore(&host->lock, iflags);
  893. if (data)
  894. dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
  895. mmc_get_dma_dir(data));
  896. dev_err(mmc_dev(mmc), "request already pending\n");
  897. mrq->cmd->error = -EBUSY;
  898. mmc_request_done(mmc, mrq);
  899. return;
  900. }
  901. if (data) {
  902. mmc_writel(host, REG_BLKSZ, data->blksz);
  903. mmc_writel(host, REG_BCNTR, data->blksz * data->blocks);
  904. sunxi_mmc_start_dma(host, data);
  905. }
  906. host->mrq = mrq;
  907. host->wait_dma = wait_dma;
  908. mmc_writel(host, REG_IMASK, host->sdio_imask | imask);
  909. mmc_writel(host, REG_CARG, cmd->arg);
  910. mmc_writel(host, REG_CMDR, cmd_val);
  911. spin_unlock_irqrestore(&host->lock, iflags);
  912. }
  913. static int sunxi_mmc_card_busy(struct mmc_host *mmc)
  914. {
  915. struct sunxi_mmc_host *host = mmc_priv(mmc);
  916. return !!(mmc_readl(host, REG_STAS) & SDXC_CARD_DATA_BUSY);
  917. }
  918. static const struct mmc_host_ops sunxi_mmc_ops = {
  919. .request = sunxi_mmc_request,
  920. .set_ios = sunxi_mmc_set_ios,
  921. .get_ro = mmc_gpio_get_ro,
  922. .get_cd = mmc_gpio_get_cd,
  923. .enable_sdio_irq = sunxi_mmc_enable_sdio_irq,
  924. .start_signal_voltage_switch = sunxi_mmc_volt_switch,
  925. .hw_reset = sunxi_mmc_hw_reset,
  926. .card_busy = sunxi_mmc_card_busy,
  927. };
  928. static const struct sunxi_mmc_clk_delay sunxi_mmc_clk_delays[] = {
  929. [SDXC_CLK_400K] = { .output = 180, .sample = 180 },
  930. [SDXC_CLK_25M] = { .output = 180, .sample = 75 },
  931. [SDXC_CLK_50M] = { .output = 90, .sample = 120 },
  932. [SDXC_CLK_50M_DDR] = { .output = 60, .sample = 120 },
  933. /* Value from A83T "new timing mode". Works but might not be right. */
  934. [SDXC_CLK_50M_DDR_8BIT] = { .output = 90, .sample = 180 },
  935. };
  936. static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = {
  937. [SDXC_CLK_400K] = { .output = 180, .sample = 180 },
  938. [SDXC_CLK_25M] = { .output = 180, .sample = 75 },
  939. [SDXC_CLK_50M] = { .output = 150, .sample = 120 },
  940. [SDXC_CLK_50M_DDR] = { .output = 54, .sample = 36 },
  941. [SDXC_CLK_50M_DDR_8BIT] = { .output = 72, .sample = 72 },
  942. };
  943. static const struct sunxi_mmc_cfg sun4i_a10_cfg = {
  944. .idma_des_size_bits = 13,
  945. .clk_delays = NULL,
  946. .can_calibrate = false,
  947. };
  948. static const struct sunxi_mmc_cfg sun5i_a13_cfg = {
  949. .idma_des_size_bits = 16,
  950. .clk_delays = NULL,
  951. .can_calibrate = false,
  952. };
  953. static const struct sunxi_mmc_cfg sun7i_a20_cfg = {
  954. .idma_des_size_bits = 16,
  955. .clk_delays = sunxi_mmc_clk_delays,
  956. .can_calibrate = false,
  957. };
  958. static const struct sunxi_mmc_cfg sun8i_a83t_emmc_cfg = {
  959. .idma_des_size_bits = 16,
  960. .clk_delays = sunxi_mmc_clk_delays,
  961. .can_calibrate = false,
  962. .has_timings_switch = true,
  963. };
  964. static const struct sunxi_mmc_cfg sun9i_a80_cfg = {
  965. .idma_des_size_bits = 16,
  966. .clk_delays = sun9i_mmc_clk_delays,
  967. .can_calibrate = false,
  968. };
  969. static const struct sunxi_mmc_cfg sun50i_a64_cfg = {
  970. .idma_des_size_bits = 16,
  971. .clk_delays = NULL,
  972. .can_calibrate = true,
  973. .mask_data0 = true,
  974. .needs_new_timings = true,
  975. };
  976. static const struct sunxi_mmc_cfg sun50i_a64_emmc_cfg = {
  977. .idma_des_size_bits = 13,
  978. .clk_delays = NULL,
  979. .can_calibrate = true,
  980. };
  981. static const struct of_device_id sunxi_mmc_of_match[] = {
  982. { .compatible = "allwinner,sun4i-a10-mmc", .data = &sun4i_a10_cfg },
  983. { .compatible = "allwinner,sun5i-a13-mmc", .data = &sun5i_a13_cfg },
  984. { .compatible = "allwinner,sun7i-a20-mmc", .data = &sun7i_a20_cfg },
  985. { .compatible = "allwinner,sun8i-a83t-emmc", .data = &sun8i_a83t_emmc_cfg },
  986. { .compatible = "allwinner,sun9i-a80-mmc", .data = &sun9i_a80_cfg },
  987. { .compatible = "allwinner,sun50i-a64-mmc", .data = &sun50i_a64_cfg },
  988. { .compatible = "allwinner,sun50i-a64-emmc", .data = &sun50i_a64_emmc_cfg },
  989. { /* sentinel */ }
  990. };
  991. MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match);
  992. static int sunxi_mmc_enable(struct sunxi_mmc_host *host)
  993. {
  994. int ret;
  995. if (!IS_ERR(host->reset)) {
  996. ret = reset_control_reset(host->reset);
  997. if (ret) {
  998. dev_err(host->dev, "Couldn't reset the MMC controller (%d)\n",
  999. ret);
  1000. return ret;
  1001. }
  1002. }
  1003. ret = clk_prepare_enable(host->clk_ahb);
  1004. if (ret) {
  1005. dev_err(host->dev, "Couldn't enable the bus clocks (%d)\n", ret);
  1006. goto error_assert_reset;
  1007. }
  1008. ret = clk_prepare_enable(host->clk_mmc);
  1009. if (ret) {
  1010. dev_err(host->dev, "Enable mmc clk err %d\n", ret);
  1011. goto error_disable_clk_ahb;
  1012. }
  1013. ret = clk_prepare_enable(host->clk_output);
  1014. if (ret) {
  1015. dev_err(host->dev, "Enable output clk err %d\n", ret);
  1016. goto error_disable_clk_mmc;
  1017. }
  1018. ret = clk_prepare_enable(host->clk_sample);
  1019. if (ret) {
  1020. dev_err(host->dev, "Enable sample clk err %d\n", ret);
  1021. goto error_disable_clk_output;
  1022. }
  1023. /*
  1024. * Sometimes the controller asserts the irq on boot for some reason,
  1025. * make sure the controller is in a sane state before enabling irqs.
  1026. */
  1027. ret = sunxi_mmc_reset_host(host);
  1028. if (ret)
  1029. goto error_disable_clk_sample;
  1030. return 0;
  1031. error_disable_clk_sample:
  1032. clk_disable_unprepare(host->clk_sample);
  1033. error_disable_clk_output:
  1034. clk_disable_unprepare(host->clk_output);
  1035. error_disable_clk_mmc:
  1036. clk_disable_unprepare(host->clk_mmc);
  1037. error_disable_clk_ahb:
  1038. clk_disable_unprepare(host->clk_ahb);
  1039. error_assert_reset:
  1040. if (!IS_ERR(host->reset))
  1041. reset_control_assert(host->reset);
  1042. return ret;
  1043. }
  1044. static void sunxi_mmc_disable(struct sunxi_mmc_host *host)
  1045. {
  1046. sunxi_mmc_reset_host(host);
  1047. clk_disable_unprepare(host->clk_sample);
  1048. clk_disable_unprepare(host->clk_output);
  1049. clk_disable_unprepare(host->clk_mmc);
  1050. clk_disable_unprepare(host->clk_ahb);
  1051. if (!IS_ERR(host->reset))
  1052. reset_control_assert(host->reset);
  1053. }
  1054. static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,
  1055. struct platform_device *pdev)
  1056. {
  1057. int ret;
  1058. host->cfg = of_device_get_match_data(&pdev->dev);
  1059. if (!host->cfg)
  1060. return -EINVAL;
  1061. ret = mmc_regulator_get_supply(host->mmc);
  1062. if (ret)
  1063. return ret;
  1064. host->reg_base = devm_ioremap_resource(&pdev->dev,
  1065. platform_get_resource(pdev, IORESOURCE_MEM, 0));
  1066. if (IS_ERR(host->reg_base))
  1067. return PTR_ERR(host->reg_base);
  1068. host->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
  1069. if (IS_ERR(host->clk_ahb)) {
  1070. dev_err(&pdev->dev, "Could not get ahb clock\n");
  1071. return PTR_ERR(host->clk_ahb);
  1072. }
  1073. host->clk_mmc = devm_clk_get(&pdev->dev, "mmc");
  1074. if (IS_ERR(host->clk_mmc)) {
  1075. dev_err(&pdev->dev, "Could not get mmc clock\n");
  1076. return PTR_ERR(host->clk_mmc);
  1077. }
  1078. if (host->cfg->clk_delays) {
  1079. host->clk_output = devm_clk_get(&pdev->dev, "output");
  1080. if (IS_ERR(host->clk_output)) {
  1081. dev_err(&pdev->dev, "Could not get output clock\n");
  1082. return PTR_ERR(host->clk_output);
  1083. }
  1084. host->clk_sample = devm_clk_get(&pdev->dev, "sample");
  1085. if (IS_ERR(host->clk_sample)) {
  1086. dev_err(&pdev->dev, "Could not get sample clock\n");
  1087. return PTR_ERR(host->clk_sample);
  1088. }
  1089. }
  1090. host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
  1091. "ahb");
  1092. if (PTR_ERR(host->reset) == -EPROBE_DEFER)
  1093. return PTR_ERR(host->reset);
  1094. ret = sunxi_mmc_enable(host);
  1095. if (ret)
  1096. return ret;
  1097. host->irq = platform_get_irq(pdev, 0);
  1098. if (host->irq <= 0) {
  1099. ret = -EINVAL;
  1100. goto error_disable_mmc;
  1101. }
  1102. return devm_request_threaded_irq(&pdev->dev, host->irq, sunxi_mmc_irq,
  1103. sunxi_mmc_handle_manual_stop, 0, "sunxi-mmc", host);
  1104. error_disable_mmc:
  1105. sunxi_mmc_disable(host);
  1106. return ret;
  1107. }
  1108. static int sunxi_mmc_probe(struct platform_device *pdev)
  1109. {
  1110. struct sunxi_mmc_host *host;
  1111. struct mmc_host *mmc;
  1112. int ret;
  1113. mmc = mmc_alloc_host(sizeof(struct sunxi_mmc_host), &pdev->dev);
  1114. if (!mmc) {
  1115. dev_err(&pdev->dev, "mmc alloc host failed\n");
  1116. return -ENOMEM;
  1117. }
  1118. platform_set_drvdata(pdev, mmc);
  1119. host = mmc_priv(mmc);
  1120. host->dev = &pdev->dev;
  1121. host->mmc = mmc;
  1122. spin_lock_init(&host->lock);
  1123. ret = sunxi_mmc_resource_request(host, pdev);
  1124. if (ret)
  1125. goto error_free_host;
  1126. host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
  1127. &host->sg_dma, GFP_KERNEL);
  1128. if (!host->sg_cpu) {
  1129. dev_err(&pdev->dev, "Failed to allocate DMA descriptor mem\n");
  1130. ret = -ENOMEM;
  1131. goto error_free_host;
  1132. }
  1133. if (host->cfg->has_timings_switch) {
  1134. /*
  1135. * Supports both old and new timing modes.
  1136. * Try setting the clk to new timing mode.
  1137. */
  1138. sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true);
  1139. /* And check the result */
  1140. ret = sunxi_ccu_get_mmc_timing_mode(host->clk_mmc);
  1141. if (ret < 0) {
  1142. /*
  1143. * For whatever reason we were not able to get
  1144. * the current active mode. Default to old mode.
  1145. */
  1146. dev_warn(&pdev->dev, "MMC clk timing mode unknown\n");
  1147. host->use_new_timings = false;
  1148. } else {
  1149. host->use_new_timings = !!ret;
  1150. }
  1151. } else if (host->cfg->needs_new_timings) {
  1152. /* Supports new timing mode only */
  1153. host->use_new_timings = true;
  1154. }
  1155. mmc->ops = &sunxi_mmc_ops;
  1156. mmc->max_blk_count = 8192;
  1157. mmc->max_blk_size = 4096;
  1158. mmc->max_segs = PAGE_SIZE / sizeof(struct sunxi_idma_des);
  1159. mmc->max_seg_size = (1 << host->cfg->idma_des_size_bits);
  1160. mmc->max_req_size = mmc->max_seg_size * mmc->max_segs;
  1161. /* 400kHz ~ 52MHz */
  1162. mmc->f_min = 400000;
  1163. mmc->f_max = 52000000;
  1164. mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
  1165. MMC_CAP_ERASE | MMC_CAP_SDIO_IRQ;
  1166. if (host->cfg->clk_delays || host->use_new_timings)
  1167. mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;
  1168. ret = mmc_of_parse(mmc);
  1169. if (ret)
  1170. goto error_free_dma;
  1171. /*
  1172. * If we don't support delay chains in the SoC, we can't use any
  1173. * of the higher speed modes. Mask them out in case the device
  1174. * tree specifies the properties for them, which gets added to
  1175. * the caps by mmc_of_parse() above.
  1176. */
  1177. if (!(host->cfg->clk_delays || host->use_new_timings)) {
  1178. mmc->caps &= ~(MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR |
  1179. MMC_CAP_1_2V_DDR | MMC_CAP_UHS);
  1180. mmc->caps2 &= ~MMC_CAP2_HS200;
  1181. }
  1182. /* TODO: This driver doesn't support HS400 mode yet */
  1183. mmc->caps2 &= ~MMC_CAP2_HS400;
  1184. ret = sunxi_mmc_init_host(host);
  1185. if (ret)
  1186. goto error_free_dma;
  1187. pm_runtime_set_active(&pdev->dev);
  1188. pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
  1189. pm_runtime_use_autosuspend(&pdev->dev);
  1190. pm_runtime_enable(&pdev->dev);
  1191. ret = mmc_add_host(mmc);
  1192. if (ret)
  1193. goto error_free_dma;
  1194. dev_info(&pdev->dev, "initialized, max. request size: %u KB%s\n",
  1195. mmc->max_req_size >> 10,
  1196. host->use_new_timings ? ", uses new timings mode" : "");
  1197. return 0;
  1198. error_free_dma:
  1199. dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
  1200. error_free_host:
  1201. mmc_free_host(mmc);
  1202. return ret;
  1203. }
  1204. static int sunxi_mmc_remove(struct platform_device *pdev)
  1205. {
  1206. struct mmc_host *mmc = platform_get_drvdata(pdev);
  1207. struct sunxi_mmc_host *host = mmc_priv(mmc);
  1208. mmc_remove_host(mmc);
  1209. pm_runtime_force_suspend(&pdev->dev);
  1210. disable_irq(host->irq);
  1211. sunxi_mmc_disable(host);
  1212. dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
  1213. mmc_free_host(mmc);
  1214. return 0;
  1215. }
  1216. #ifdef CONFIG_PM
  1217. static int sunxi_mmc_runtime_resume(struct device *dev)
  1218. {
  1219. struct mmc_host *mmc = dev_get_drvdata(dev);
  1220. struct sunxi_mmc_host *host = mmc_priv(mmc);
  1221. int ret;
  1222. ret = sunxi_mmc_enable(host);
  1223. if (ret)
  1224. return ret;
  1225. sunxi_mmc_init_host(host);
  1226. sunxi_mmc_set_bus_width(host, mmc->ios.bus_width);
  1227. sunxi_mmc_set_clk(host, &mmc->ios);
  1228. enable_irq(host->irq);
  1229. return 0;
  1230. }
  1231. static int sunxi_mmc_runtime_suspend(struct device *dev)
  1232. {
  1233. struct mmc_host *mmc = dev_get_drvdata(dev);
  1234. struct sunxi_mmc_host *host = mmc_priv(mmc);
  1235. /*
  1236. * When clocks are off, it's possible receiving
  1237. * fake interrupts, which will stall the system.
  1238. * Disabling the irq will prevent this.
  1239. */
  1240. disable_irq(host->irq);
  1241. sunxi_mmc_reset_host(host);
  1242. sunxi_mmc_disable(host);
  1243. return 0;
  1244. }
  1245. #endif
  1246. static const struct dev_pm_ops sunxi_mmc_pm_ops = {
  1247. SET_RUNTIME_PM_OPS(sunxi_mmc_runtime_suspend,
  1248. sunxi_mmc_runtime_resume,
  1249. NULL)
  1250. };
  1251. static struct platform_driver sunxi_mmc_driver = {
  1252. .driver = {
  1253. .name = "sunxi-mmc",
  1254. .of_match_table = of_match_ptr(sunxi_mmc_of_match),
  1255. .pm = &sunxi_mmc_pm_ops,
  1256. },
  1257. .probe = sunxi_mmc_probe,
  1258. .remove = sunxi_mmc_remove,
  1259. };
  1260. module_platform_driver(sunxi_mmc_driver);
  1261. MODULE_DESCRIPTION("Allwinner's SD/MMC Card Controller Driver");
  1262. MODULE_LICENSE("GPL v2");
  1263. MODULE_AUTHOR("David Lanzendörfer <david.lanzendoerfer@o2s.ch>");
  1264. MODULE_ALIAS("platform:sunxi-mmc");