wmt-sdmmc.c 24 KB

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  1. /*
  2. * WM8505/WM8650 SD/MMC Host Controller
  3. *
  4. * Copyright (C) 2010 Tony Prisk
  5. * Copyright (C) 2008 WonderMedia Technologies, Inc.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation
  10. */
  11. #include <linux/init.h>
  12. #include <linux/module.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/ioport.h>
  15. #include <linux/errno.h>
  16. #include <linux/dma-mapping.h>
  17. #include <linux/delay.h>
  18. #include <linux/io.h>
  19. #include <linux/irq.h>
  20. #include <linux/clk.h>
  21. #include <linux/gpio.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/of.h>
  24. #include <linux/of_address.h>
  25. #include <linux/of_irq.h>
  26. #include <linux/of_device.h>
  27. #include <linux/mmc/host.h>
  28. #include <linux/mmc/mmc.h>
  29. #include <linux/mmc/sd.h>
  30. #include <asm/byteorder.h>
  31. #define DRIVER_NAME "wmt-sdhc"
  32. /* MMC/SD controller registers */
  33. #define SDMMC_CTLR 0x00
  34. #define SDMMC_CMD 0x01
  35. #define SDMMC_RSPTYPE 0x02
  36. #define SDMMC_ARG 0x04
  37. #define SDMMC_BUSMODE 0x08
  38. #define SDMMC_BLKLEN 0x0C
  39. #define SDMMC_BLKCNT 0x0E
  40. #define SDMMC_RSP 0x10
  41. #define SDMMC_CBCR 0x20
  42. #define SDMMC_INTMASK0 0x24
  43. #define SDMMC_INTMASK1 0x25
  44. #define SDMMC_STS0 0x28
  45. #define SDMMC_STS1 0x29
  46. #define SDMMC_STS2 0x2A
  47. #define SDMMC_STS3 0x2B
  48. #define SDMMC_RSPTIMEOUT 0x2C
  49. #define SDMMC_CLK 0x30 /* VT8500 only */
  50. #define SDMMC_EXTCTRL 0x34
  51. #define SDMMC_SBLKLEN 0x38
  52. #define SDMMC_DMATIMEOUT 0x3C
  53. /* SDMMC_CTLR bit fields */
  54. #define CTLR_CMD_START 0x01
  55. #define CTLR_CMD_WRITE 0x04
  56. #define CTLR_FIFO_RESET 0x08
  57. /* SDMMC_BUSMODE bit fields */
  58. #define BM_SPI_MODE 0x01
  59. #define BM_FOURBIT_MODE 0x02
  60. #define BM_EIGHTBIT_MODE 0x04
  61. #define BM_SD_OFF 0x10
  62. #define BM_SPI_CS 0x20
  63. #define BM_SD_POWER 0x40
  64. #define BM_SOFT_RESET 0x80
  65. /* SDMMC_BLKLEN bit fields */
  66. #define BLKL_CRCERR_ABORT 0x0800
  67. #define BLKL_CD_POL_HIGH 0x1000
  68. #define BLKL_GPI_CD 0x2000
  69. #define BLKL_DATA3_CD 0x4000
  70. #define BLKL_INT_ENABLE 0x8000
  71. /* SDMMC_INTMASK0 bit fields */
  72. #define INT0_MBLK_TRAN_DONE_INT_EN 0x10
  73. #define INT0_BLK_TRAN_DONE_INT_EN 0x20
  74. #define INT0_CD_INT_EN 0x40
  75. #define INT0_DI_INT_EN 0x80
  76. /* SDMMC_INTMASK1 bit fields */
  77. #define INT1_CMD_RES_TRAN_DONE_INT_EN 0x02
  78. #define INT1_CMD_RES_TOUT_INT_EN 0x04
  79. #define INT1_MBLK_AUTO_STOP_INT_EN 0x08
  80. #define INT1_DATA_TOUT_INT_EN 0x10
  81. #define INT1_RESCRC_ERR_INT_EN 0x20
  82. #define INT1_RCRC_ERR_INT_EN 0x40
  83. #define INT1_WCRC_ERR_INT_EN 0x80
  84. /* SDMMC_STS0 bit fields */
  85. #define STS0_WRITE_PROTECT 0x02
  86. #define STS0_CD_DATA3 0x04
  87. #define STS0_CD_GPI 0x08
  88. #define STS0_MBLK_DONE 0x10
  89. #define STS0_BLK_DONE 0x20
  90. #define STS0_CARD_DETECT 0x40
  91. #define STS0_DEVICE_INS 0x80
  92. /* SDMMC_STS1 bit fields */
  93. #define STS1_SDIO_INT 0x01
  94. #define STS1_CMDRSP_DONE 0x02
  95. #define STS1_RSP_TIMEOUT 0x04
  96. #define STS1_AUTOSTOP_DONE 0x08
  97. #define STS1_DATA_TIMEOUT 0x10
  98. #define STS1_RSP_CRC_ERR 0x20
  99. #define STS1_RCRC_ERR 0x40
  100. #define STS1_WCRC_ERR 0x80
  101. /* SDMMC_STS2 bit fields */
  102. #define STS2_CMD_RES_BUSY 0x10
  103. #define STS2_DATARSP_BUSY 0x20
  104. #define STS2_DIS_FORCECLK 0x80
  105. /* SDMMC_EXTCTRL bit fields */
  106. #define EXT_EIGHTBIT 0x04
  107. /* MMC/SD DMA Controller Registers */
  108. #define SDDMA_GCR 0x100
  109. #define SDDMA_IER 0x104
  110. #define SDDMA_ISR 0x108
  111. #define SDDMA_DESPR 0x10C
  112. #define SDDMA_RBR 0x110
  113. #define SDDMA_DAR 0x114
  114. #define SDDMA_BAR 0x118
  115. #define SDDMA_CPR 0x11C
  116. #define SDDMA_CCR 0x120
  117. /* SDDMA_GCR bit fields */
  118. #define DMA_GCR_DMA_EN 0x00000001
  119. #define DMA_GCR_SOFT_RESET 0x00000100
  120. /* SDDMA_IER bit fields */
  121. #define DMA_IER_INT_EN 0x00000001
  122. /* SDDMA_ISR bit fields */
  123. #define DMA_ISR_INT_STS 0x00000001
  124. /* SDDMA_RBR bit fields */
  125. #define DMA_RBR_FORMAT 0x40000000
  126. #define DMA_RBR_END 0x80000000
  127. /* SDDMA_CCR bit fields */
  128. #define DMA_CCR_RUN 0x00000080
  129. #define DMA_CCR_IF_TO_PERIPHERAL 0x00000000
  130. #define DMA_CCR_PERIPHERAL_TO_IF 0x00400000
  131. /* SDDMA_CCR event status */
  132. #define DMA_CCR_EVT_NO_STATUS 0x00000000
  133. #define DMA_CCR_EVT_UNDERRUN 0x00000001
  134. #define DMA_CCR_EVT_OVERRUN 0x00000002
  135. #define DMA_CCR_EVT_DESP_READ 0x00000003
  136. #define DMA_CCR_EVT_DATA_RW 0x00000004
  137. #define DMA_CCR_EVT_EARLY_END 0x00000005
  138. #define DMA_CCR_EVT_SUCCESS 0x0000000F
  139. #define PDMA_READ 0x00
  140. #define PDMA_WRITE 0x01
  141. #define WMT_SD_POWER_OFF 0
  142. #define WMT_SD_POWER_ON 1
  143. struct wmt_dma_descriptor {
  144. u32 flags;
  145. u32 data_buffer_addr;
  146. u32 branch_addr;
  147. u32 reserved1;
  148. };
  149. struct wmt_mci_caps {
  150. unsigned int f_min;
  151. unsigned int f_max;
  152. u32 ocr_avail;
  153. u32 caps;
  154. u32 max_seg_size;
  155. u32 max_segs;
  156. u32 max_blk_size;
  157. };
  158. struct wmt_mci_priv {
  159. struct mmc_host *mmc;
  160. void __iomem *sdmmc_base;
  161. int irq_regular;
  162. int irq_dma;
  163. void *dma_desc_buffer;
  164. dma_addr_t dma_desc_device_addr;
  165. struct completion cmdcomp;
  166. struct completion datacomp;
  167. struct completion *comp_cmd;
  168. struct completion *comp_dma;
  169. struct mmc_request *req;
  170. struct mmc_command *cmd;
  171. struct clk *clk_sdmmc;
  172. struct device *dev;
  173. u8 power_inverted;
  174. u8 cd_inverted;
  175. };
  176. static void wmt_set_sd_power(struct wmt_mci_priv *priv, int enable)
  177. {
  178. u32 reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE);
  179. if (enable ^ priv->power_inverted)
  180. reg_tmp &= ~BM_SD_OFF;
  181. else
  182. reg_tmp |= BM_SD_OFF;
  183. writeb(reg_tmp, priv->sdmmc_base + SDMMC_BUSMODE);
  184. }
  185. static void wmt_mci_read_response(struct mmc_host *mmc)
  186. {
  187. struct wmt_mci_priv *priv;
  188. int idx1, idx2;
  189. u8 tmp_resp;
  190. u32 response;
  191. priv = mmc_priv(mmc);
  192. for (idx1 = 0; idx1 < 4; idx1++) {
  193. response = 0;
  194. for (idx2 = 0; idx2 < 4; idx2++) {
  195. if ((idx1 == 3) && (idx2 == 3))
  196. tmp_resp = readb(priv->sdmmc_base + SDMMC_RSP);
  197. else
  198. tmp_resp = readb(priv->sdmmc_base + SDMMC_RSP +
  199. (idx1*4) + idx2 + 1);
  200. response |= (tmp_resp << (idx2 * 8));
  201. }
  202. priv->cmd->resp[idx1] = cpu_to_be32(response);
  203. }
  204. }
  205. static void wmt_mci_start_command(struct wmt_mci_priv *priv)
  206. {
  207. u32 reg_tmp;
  208. reg_tmp = readb(priv->sdmmc_base + SDMMC_CTLR);
  209. writeb(reg_tmp | CTLR_CMD_START, priv->sdmmc_base + SDMMC_CTLR);
  210. }
  211. static int wmt_mci_send_command(struct mmc_host *mmc, u8 command, u8 cmdtype,
  212. u32 arg, u8 rsptype)
  213. {
  214. struct wmt_mci_priv *priv;
  215. u32 reg_tmp;
  216. priv = mmc_priv(mmc);
  217. /* write command, arg, resptype registers */
  218. writeb(command, priv->sdmmc_base + SDMMC_CMD);
  219. writel(arg, priv->sdmmc_base + SDMMC_ARG);
  220. writeb(rsptype, priv->sdmmc_base + SDMMC_RSPTYPE);
  221. /* reset response FIFO */
  222. reg_tmp = readb(priv->sdmmc_base + SDMMC_CTLR);
  223. writeb(reg_tmp | CTLR_FIFO_RESET, priv->sdmmc_base + SDMMC_CTLR);
  224. /* ensure clock enabled - VT3465 */
  225. wmt_set_sd_power(priv, WMT_SD_POWER_ON);
  226. /* clear status bits */
  227. writeb(0xFF, priv->sdmmc_base + SDMMC_STS0);
  228. writeb(0xFF, priv->sdmmc_base + SDMMC_STS1);
  229. writeb(0xFF, priv->sdmmc_base + SDMMC_STS2);
  230. writeb(0xFF, priv->sdmmc_base + SDMMC_STS3);
  231. /* set command type */
  232. reg_tmp = readb(priv->sdmmc_base + SDMMC_CTLR);
  233. writeb((reg_tmp & 0x0F) | (cmdtype << 4),
  234. priv->sdmmc_base + SDMMC_CTLR);
  235. return 0;
  236. }
  237. static void wmt_mci_disable_dma(struct wmt_mci_priv *priv)
  238. {
  239. writel(DMA_ISR_INT_STS, priv->sdmmc_base + SDDMA_ISR);
  240. writel(0, priv->sdmmc_base + SDDMA_IER);
  241. }
  242. static void wmt_complete_data_request(struct wmt_mci_priv *priv)
  243. {
  244. struct mmc_request *req;
  245. req = priv->req;
  246. req->data->bytes_xfered = req->data->blksz * req->data->blocks;
  247. /* unmap the DMA pages used for write data */
  248. if (req->data->flags & MMC_DATA_WRITE)
  249. dma_unmap_sg(mmc_dev(priv->mmc), req->data->sg,
  250. req->data->sg_len, DMA_TO_DEVICE);
  251. else
  252. dma_unmap_sg(mmc_dev(priv->mmc), req->data->sg,
  253. req->data->sg_len, DMA_FROM_DEVICE);
  254. /* Check if the DMA ISR returned a data error */
  255. if ((req->cmd->error) || (req->data->error))
  256. mmc_request_done(priv->mmc, req);
  257. else {
  258. wmt_mci_read_response(priv->mmc);
  259. if (!req->data->stop) {
  260. /* single-block read/write requests end here */
  261. mmc_request_done(priv->mmc, req);
  262. } else {
  263. /*
  264. * we change the priv->cmd variable so the response is
  265. * stored in the stop struct rather than the original
  266. * calling command struct
  267. */
  268. priv->comp_cmd = &priv->cmdcomp;
  269. init_completion(priv->comp_cmd);
  270. priv->cmd = req->data->stop;
  271. wmt_mci_send_command(priv->mmc, req->data->stop->opcode,
  272. 7, req->data->stop->arg, 9);
  273. wmt_mci_start_command(priv);
  274. }
  275. }
  276. }
  277. static irqreturn_t wmt_mci_dma_isr(int irq_num, void *data)
  278. {
  279. struct wmt_mci_priv *priv;
  280. int status;
  281. priv = (struct wmt_mci_priv *)data;
  282. status = readl(priv->sdmmc_base + SDDMA_CCR) & 0x0F;
  283. if (status != DMA_CCR_EVT_SUCCESS) {
  284. dev_err(priv->dev, "DMA Error: Status = %d\n", status);
  285. priv->req->data->error = -ETIMEDOUT;
  286. complete(priv->comp_dma);
  287. return IRQ_HANDLED;
  288. }
  289. priv->req->data->error = 0;
  290. wmt_mci_disable_dma(priv);
  291. complete(priv->comp_dma);
  292. if (priv->comp_cmd) {
  293. if (completion_done(priv->comp_cmd)) {
  294. /*
  295. * if the command (regular) interrupt has already
  296. * completed, finish off the request otherwise we wait
  297. * for the command interrupt and finish from there.
  298. */
  299. wmt_complete_data_request(priv);
  300. }
  301. }
  302. return IRQ_HANDLED;
  303. }
  304. static irqreturn_t wmt_mci_regular_isr(int irq_num, void *data)
  305. {
  306. struct wmt_mci_priv *priv;
  307. u32 status0;
  308. u32 status1;
  309. u32 status2;
  310. u32 reg_tmp;
  311. int cmd_done;
  312. priv = (struct wmt_mci_priv *)data;
  313. cmd_done = 0;
  314. status0 = readb(priv->sdmmc_base + SDMMC_STS0);
  315. status1 = readb(priv->sdmmc_base + SDMMC_STS1);
  316. status2 = readb(priv->sdmmc_base + SDMMC_STS2);
  317. /* Check for card insertion */
  318. reg_tmp = readb(priv->sdmmc_base + SDMMC_INTMASK0);
  319. if ((reg_tmp & INT0_DI_INT_EN) && (status0 & STS0_DEVICE_INS)) {
  320. mmc_detect_change(priv->mmc, 0);
  321. if (priv->cmd)
  322. priv->cmd->error = -ETIMEDOUT;
  323. if (priv->comp_cmd)
  324. complete(priv->comp_cmd);
  325. if (priv->comp_dma) {
  326. wmt_mci_disable_dma(priv);
  327. complete(priv->comp_dma);
  328. }
  329. writeb(STS0_DEVICE_INS, priv->sdmmc_base + SDMMC_STS0);
  330. return IRQ_HANDLED;
  331. }
  332. if ((!priv->req->data) ||
  333. ((priv->req->data->stop) && (priv->cmd == priv->req->data->stop))) {
  334. /* handle non-data & stop_transmission requests */
  335. if (status1 & STS1_CMDRSP_DONE) {
  336. priv->cmd->error = 0;
  337. cmd_done = 1;
  338. } else if ((status1 & STS1_RSP_TIMEOUT) ||
  339. (status1 & STS1_DATA_TIMEOUT)) {
  340. priv->cmd->error = -ETIMEDOUT;
  341. cmd_done = 1;
  342. }
  343. if (cmd_done) {
  344. priv->comp_cmd = NULL;
  345. if (!priv->cmd->error)
  346. wmt_mci_read_response(priv->mmc);
  347. priv->cmd = NULL;
  348. mmc_request_done(priv->mmc, priv->req);
  349. }
  350. } else {
  351. /* handle data requests */
  352. if (status1 & STS1_CMDRSP_DONE) {
  353. if (priv->cmd)
  354. priv->cmd->error = 0;
  355. if (priv->comp_cmd)
  356. complete(priv->comp_cmd);
  357. }
  358. if ((status1 & STS1_RSP_TIMEOUT) ||
  359. (status1 & STS1_DATA_TIMEOUT)) {
  360. if (priv->cmd)
  361. priv->cmd->error = -ETIMEDOUT;
  362. if (priv->comp_cmd)
  363. complete(priv->comp_cmd);
  364. if (priv->comp_dma) {
  365. wmt_mci_disable_dma(priv);
  366. complete(priv->comp_dma);
  367. }
  368. }
  369. if (priv->comp_dma) {
  370. /*
  371. * If the dma interrupt has already completed, finish
  372. * off the request; otherwise we wait for the DMA
  373. * interrupt and finish from there.
  374. */
  375. if (completion_done(priv->comp_dma))
  376. wmt_complete_data_request(priv);
  377. }
  378. }
  379. writeb(status0, priv->sdmmc_base + SDMMC_STS0);
  380. writeb(status1, priv->sdmmc_base + SDMMC_STS1);
  381. writeb(status2, priv->sdmmc_base + SDMMC_STS2);
  382. return IRQ_HANDLED;
  383. }
  384. static void wmt_reset_hardware(struct mmc_host *mmc)
  385. {
  386. struct wmt_mci_priv *priv;
  387. u32 reg_tmp;
  388. priv = mmc_priv(mmc);
  389. /* reset controller */
  390. reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE);
  391. writeb(reg_tmp | BM_SOFT_RESET, priv->sdmmc_base + SDMMC_BUSMODE);
  392. /* reset response FIFO */
  393. reg_tmp = readb(priv->sdmmc_base + SDMMC_CTLR);
  394. writeb(reg_tmp | CTLR_FIFO_RESET, priv->sdmmc_base + SDMMC_CTLR);
  395. /* enable GPI pin to detect card */
  396. writew(BLKL_INT_ENABLE | BLKL_GPI_CD, priv->sdmmc_base + SDMMC_BLKLEN);
  397. /* clear interrupt status */
  398. writeb(0xFF, priv->sdmmc_base + SDMMC_STS0);
  399. writeb(0xFF, priv->sdmmc_base + SDMMC_STS1);
  400. /* setup interrupts */
  401. writeb(INT0_CD_INT_EN | INT0_DI_INT_EN, priv->sdmmc_base +
  402. SDMMC_INTMASK0);
  403. writeb(INT1_DATA_TOUT_INT_EN | INT1_CMD_RES_TRAN_DONE_INT_EN |
  404. INT1_CMD_RES_TOUT_INT_EN, priv->sdmmc_base + SDMMC_INTMASK1);
  405. /* set the DMA timeout */
  406. writew(8191, priv->sdmmc_base + SDMMC_DMATIMEOUT);
  407. /* auto clock freezing enable */
  408. reg_tmp = readb(priv->sdmmc_base + SDMMC_STS2);
  409. writeb(reg_tmp | STS2_DIS_FORCECLK, priv->sdmmc_base + SDMMC_STS2);
  410. /* set a default clock speed of 400Khz */
  411. clk_set_rate(priv->clk_sdmmc, 400000);
  412. }
  413. static int wmt_dma_init(struct mmc_host *mmc)
  414. {
  415. struct wmt_mci_priv *priv;
  416. priv = mmc_priv(mmc);
  417. writel(DMA_GCR_SOFT_RESET, priv->sdmmc_base + SDDMA_GCR);
  418. writel(DMA_GCR_DMA_EN, priv->sdmmc_base + SDDMA_GCR);
  419. if ((readl(priv->sdmmc_base + SDDMA_GCR) & DMA_GCR_DMA_EN) != 0)
  420. return 0;
  421. else
  422. return 1;
  423. }
  424. static void wmt_dma_init_descriptor(struct wmt_dma_descriptor *desc,
  425. u16 req_count, u32 buffer_addr, u32 branch_addr, int end)
  426. {
  427. desc->flags = 0x40000000 | req_count;
  428. if (end)
  429. desc->flags |= 0x80000000;
  430. desc->data_buffer_addr = buffer_addr;
  431. desc->branch_addr = branch_addr;
  432. }
  433. static void wmt_dma_config(struct mmc_host *mmc, u32 descaddr, u8 dir)
  434. {
  435. struct wmt_mci_priv *priv;
  436. u32 reg_tmp;
  437. priv = mmc_priv(mmc);
  438. /* Enable DMA Interrupts */
  439. writel(DMA_IER_INT_EN, priv->sdmmc_base + SDDMA_IER);
  440. /* Write DMA Descriptor Pointer Register */
  441. writel(descaddr, priv->sdmmc_base + SDDMA_DESPR);
  442. writel(0x00, priv->sdmmc_base + SDDMA_CCR);
  443. if (dir == PDMA_WRITE) {
  444. reg_tmp = readl(priv->sdmmc_base + SDDMA_CCR);
  445. writel(reg_tmp & DMA_CCR_IF_TO_PERIPHERAL, priv->sdmmc_base +
  446. SDDMA_CCR);
  447. } else {
  448. reg_tmp = readl(priv->sdmmc_base + SDDMA_CCR);
  449. writel(reg_tmp | DMA_CCR_PERIPHERAL_TO_IF, priv->sdmmc_base +
  450. SDDMA_CCR);
  451. }
  452. }
  453. static void wmt_dma_start(struct wmt_mci_priv *priv)
  454. {
  455. u32 reg_tmp;
  456. reg_tmp = readl(priv->sdmmc_base + SDDMA_CCR);
  457. writel(reg_tmp | DMA_CCR_RUN, priv->sdmmc_base + SDDMA_CCR);
  458. }
  459. static void wmt_mci_request(struct mmc_host *mmc, struct mmc_request *req)
  460. {
  461. struct wmt_mci_priv *priv;
  462. struct wmt_dma_descriptor *desc;
  463. u8 command;
  464. u8 cmdtype;
  465. u32 arg;
  466. u8 rsptype;
  467. u32 reg_tmp;
  468. struct scatterlist *sg;
  469. int i;
  470. int sg_cnt;
  471. int offset;
  472. u32 dma_address;
  473. int desc_cnt;
  474. priv = mmc_priv(mmc);
  475. priv->req = req;
  476. /*
  477. * Use the cmd variable to pass a pointer to the resp[] structure
  478. * This is required on multi-block requests to pass the pointer to the
  479. * stop command
  480. */
  481. priv->cmd = req->cmd;
  482. command = req->cmd->opcode;
  483. arg = req->cmd->arg;
  484. rsptype = mmc_resp_type(req->cmd);
  485. cmdtype = 0;
  486. /* rsptype=7 only valid for SPI commands - should be =2 for SD */
  487. if (rsptype == 7)
  488. rsptype = 2;
  489. /* rsptype=21 is R1B, convert for controller */
  490. if (rsptype == 21)
  491. rsptype = 9;
  492. if (!req->data) {
  493. wmt_mci_send_command(mmc, command, cmdtype, arg, rsptype);
  494. wmt_mci_start_command(priv);
  495. /* completion is now handled in the regular_isr() */
  496. }
  497. if (req->data) {
  498. priv->comp_cmd = &priv->cmdcomp;
  499. init_completion(priv->comp_cmd);
  500. wmt_dma_init(mmc);
  501. /* set controller data length */
  502. reg_tmp = readw(priv->sdmmc_base + SDMMC_BLKLEN);
  503. writew((reg_tmp & 0xF800) | (req->data->blksz - 1),
  504. priv->sdmmc_base + SDMMC_BLKLEN);
  505. /* set controller block count */
  506. writew(req->data->blocks, priv->sdmmc_base + SDMMC_BLKCNT);
  507. desc = (struct wmt_dma_descriptor *)priv->dma_desc_buffer;
  508. if (req->data->flags & MMC_DATA_WRITE) {
  509. sg_cnt = dma_map_sg(mmc_dev(mmc), req->data->sg,
  510. req->data->sg_len, DMA_TO_DEVICE);
  511. cmdtype = 1;
  512. if (req->data->blocks > 1)
  513. cmdtype = 3;
  514. } else {
  515. sg_cnt = dma_map_sg(mmc_dev(mmc), req->data->sg,
  516. req->data->sg_len, DMA_FROM_DEVICE);
  517. cmdtype = 2;
  518. if (req->data->blocks > 1)
  519. cmdtype = 4;
  520. }
  521. dma_address = priv->dma_desc_device_addr + 16;
  522. desc_cnt = 0;
  523. for_each_sg(req->data->sg, sg, sg_cnt, i) {
  524. offset = 0;
  525. while (offset < sg_dma_len(sg)) {
  526. wmt_dma_init_descriptor(desc, req->data->blksz,
  527. sg_dma_address(sg)+offset,
  528. dma_address, 0);
  529. desc++;
  530. desc_cnt++;
  531. offset += req->data->blksz;
  532. dma_address += 16;
  533. if (desc_cnt == req->data->blocks)
  534. break;
  535. }
  536. }
  537. desc--;
  538. desc->flags |= 0x80000000;
  539. if (req->data->flags & MMC_DATA_WRITE)
  540. wmt_dma_config(mmc, priv->dma_desc_device_addr,
  541. PDMA_WRITE);
  542. else
  543. wmt_dma_config(mmc, priv->dma_desc_device_addr,
  544. PDMA_READ);
  545. wmt_mci_send_command(mmc, command, cmdtype, arg, rsptype);
  546. priv->comp_dma = &priv->datacomp;
  547. init_completion(priv->comp_dma);
  548. wmt_dma_start(priv);
  549. wmt_mci_start_command(priv);
  550. }
  551. }
  552. static void wmt_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  553. {
  554. struct wmt_mci_priv *priv;
  555. u32 busmode, extctrl;
  556. priv = mmc_priv(mmc);
  557. if (ios->power_mode == MMC_POWER_UP) {
  558. wmt_reset_hardware(mmc);
  559. wmt_set_sd_power(priv, WMT_SD_POWER_ON);
  560. }
  561. if (ios->power_mode == MMC_POWER_OFF)
  562. wmt_set_sd_power(priv, WMT_SD_POWER_OFF);
  563. if (ios->clock != 0)
  564. clk_set_rate(priv->clk_sdmmc, ios->clock);
  565. busmode = readb(priv->sdmmc_base + SDMMC_BUSMODE);
  566. extctrl = readb(priv->sdmmc_base + SDMMC_EXTCTRL);
  567. busmode &= ~(BM_EIGHTBIT_MODE | BM_FOURBIT_MODE);
  568. extctrl &= ~EXT_EIGHTBIT;
  569. switch (ios->bus_width) {
  570. case MMC_BUS_WIDTH_8:
  571. busmode |= BM_EIGHTBIT_MODE;
  572. extctrl |= EXT_EIGHTBIT;
  573. break;
  574. case MMC_BUS_WIDTH_4:
  575. busmode |= BM_FOURBIT_MODE;
  576. break;
  577. case MMC_BUS_WIDTH_1:
  578. break;
  579. }
  580. writeb(busmode, priv->sdmmc_base + SDMMC_BUSMODE);
  581. writeb(extctrl, priv->sdmmc_base + SDMMC_EXTCTRL);
  582. }
  583. static int wmt_mci_get_ro(struct mmc_host *mmc)
  584. {
  585. struct wmt_mci_priv *priv = mmc_priv(mmc);
  586. return !(readb(priv->sdmmc_base + SDMMC_STS0) & STS0_WRITE_PROTECT);
  587. }
  588. static int wmt_mci_get_cd(struct mmc_host *mmc)
  589. {
  590. struct wmt_mci_priv *priv = mmc_priv(mmc);
  591. u32 cd = (readb(priv->sdmmc_base + SDMMC_STS0) & STS0_CD_GPI) >> 3;
  592. return !(cd ^ priv->cd_inverted);
  593. }
  594. static const struct mmc_host_ops wmt_mci_ops = {
  595. .request = wmt_mci_request,
  596. .set_ios = wmt_mci_set_ios,
  597. .get_ro = wmt_mci_get_ro,
  598. .get_cd = wmt_mci_get_cd,
  599. };
  600. /* Controller capabilities */
  601. static struct wmt_mci_caps wm8505_caps = {
  602. .f_min = 390425,
  603. .f_max = 50000000,
  604. .ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34,
  605. .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED |
  606. MMC_CAP_SD_HIGHSPEED,
  607. .max_seg_size = 65024,
  608. .max_segs = 128,
  609. .max_blk_size = 2048,
  610. };
  611. static const struct of_device_id wmt_mci_dt_ids[] = {
  612. { .compatible = "wm,wm8505-sdhc", .data = &wm8505_caps },
  613. { /* Sentinel */ },
  614. };
  615. static int wmt_mci_probe(struct platform_device *pdev)
  616. {
  617. struct mmc_host *mmc;
  618. struct wmt_mci_priv *priv;
  619. struct device_node *np = pdev->dev.of_node;
  620. const struct of_device_id *of_id =
  621. of_match_device(wmt_mci_dt_ids, &pdev->dev);
  622. const struct wmt_mci_caps *wmt_caps;
  623. int ret;
  624. int regular_irq, dma_irq;
  625. if (!of_id || !of_id->data) {
  626. dev_err(&pdev->dev, "Controller capabilities data missing\n");
  627. return -EFAULT;
  628. }
  629. wmt_caps = of_id->data;
  630. if (!np) {
  631. dev_err(&pdev->dev, "Missing SDMMC description in devicetree\n");
  632. return -EFAULT;
  633. }
  634. regular_irq = irq_of_parse_and_map(np, 0);
  635. dma_irq = irq_of_parse_and_map(np, 1);
  636. if (!regular_irq || !dma_irq) {
  637. dev_err(&pdev->dev, "Getting IRQs failed!\n");
  638. ret = -ENXIO;
  639. goto fail1;
  640. }
  641. mmc = mmc_alloc_host(sizeof(struct wmt_mci_priv), &pdev->dev);
  642. if (!mmc) {
  643. dev_err(&pdev->dev, "Failed to allocate mmc_host\n");
  644. ret = -ENOMEM;
  645. goto fail1;
  646. }
  647. mmc->ops = &wmt_mci_ops;
  648. mmc->f_min = wmt_caps->f_min;
  649. mmc->f_max = wmt_caps->f_max;
  650. mmc->ocr_avail = wmt_caps->ocr_avail;
  651. mmc->caps = wmt_caps->caps;
  652. mmc->max_seg_size = wmt_caps->max_seg_size;
  653. mmc->max_segs = wmt_caps->max_segs;
  654. mmc->max_blk_size = wmt_caps->max_blk_size;
  655. mmc->max_req_size = (16*512*mmc->max_segs);
  656. mmc->max_blk_count = mmc->max_req_size / 512;
  657. priv = mmc_priv(mmc);
  658. priv->mmc = mmc;
  659. priv->dev = &pdev->dev;
  660. priv->power_inverted = 0;
  661. priv->cd_inverted = 0;
  662. if (of_get_property(np, "sdon-inverted", NULL))
  663. priv->power_inverted = 1;
  664. if (of_get_property(np, "cd-inverted", NULL))
  665. priv->cd_inverted = 1;
  666. priv->sdmmc_base = of_iomap(np, 0);
  667. if (!priv->sdmmc_base) {
  668. dev_err(&pdev->dev, "Failed to map IO space\n");
  669. ret = -ENOMEM;
  670. goto fail2;
  671. }
  672. priv->irq_regular = regular_irq;
  673. priv->irq_dma = dma_irq;
  674. ret = request_irq(regular_irq, wmt_mci_regular_isr, 0, "sdmmc", priv);
  675. if (ret) {
  676. dev_err(&pdev->dev, "Register regular IRQ fail\n");
  677. goto fail3;
  678. }
  679. ret = request_irq(dma_irq, wmt_mci_dma_isr, 0, "sdmmc", priv);
  680. if (ret) {
  681. dev_err(&pdev->dev, "Register DMA IRQ fail\n");
  682. goto fail4;
  683. }
  684. /* alloc some DMA buffers for descriptors/transfers */
  685. priv->dma_desc_buffer = dma_alloc_coherent(&pdev->dev,
  686. mmc->max_blk_count * 16,
  687. &priv->dma_desc_device_addr,
  688. GFP_KERNEL);
  689. if (!priv->dma_desc_buffer) {
  690. dev_err(&pdev->dev, "DMA alloc fail\n");
  691. ret = -EPERM;
  692. goto fail5;
  693. }
  694. platform_set_drvdata(pdev, mmc);
  695. priv->clk_sdmmc = of_clk_get(np, 0);
  696. if (IS_ERR(priv->clk_sdmmc)) {
  697. dev_err(&pdev->dev, "Error getting clock\n");
  698. ret = PTR_ERR(priv->clk_sdmmc);
  699. goto fail5;
  700. }
  701. ret = clk_prepare_enable(priv->clk_sdmmc);
  702. if (ret)
  703. goto fail6;
  704. /* configure the controller to a known 'ready' state */
  705. wmt_reset_hardware(mmc);
  706. mmc_add_host(mmc);
  707. dev_info(&pdev->dev, "WMT SDHC Controller initialized\n");
  708. return 0;
  709. fail6:
  710. clk_put(priv->clk_sdmmc);
  711. fail5:
  712. free_irq(dma_irq, priv);
  713. fail4:
  714. free_irq(regular_irq, priv);
  715. fail3:
  716. iounmap(priv->sdmmc_base);
  717. fail2:
  718. mmc_free_host(mmc);
  719. fail1:
  720. return ret;
  721. }
  722. static int wmt_mci_remove(struct platform_device *pdev)
  723. {
  724. struct mmc_host *mmc;
  725. struct wmt_mci_priv *priv;
  726. struct resource *res;
  727. u32 reg_tmp;
  728. mmc = platform_get_drvdata(pdev);
  729. priv = mmc_priv(mmc);
  730. /* reset SD controller */
  731. reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE);
  732. writel(reg_tmp | BM_SOFT_RESET, priv->sdmmc_base + SDMMC_BUSMODE);
  733. reg_tmp = readw(priv->sdmmc_base + SDMMC_BLKLEN);
  734. writew(reg_tmp & ~(0xA000), priv->sdmmc_base + SDMMC_BLKLEN);
  735. writeb(0xFF, priv->sdmmc_base + SDMMC_STS0);
  736. writeb(0xFF, priv->sdmmc_base + SDMMC_STS1);
  737. /* release the dma buffers */
  738. dma_free_coherent(&pdev->dev, priv->mmc->max_blk_count * 16,
  739. priv->dma_desc_buffer, priv->dma_desc_device_addr);
  740. mmc_remove_host(mmc);
  741. free_irq(priv->irq_regular, priv);
  742. free_irq(priv->irq_dma, priv);
  743. iounmap(priv->sdmmc_base);
  744. clk_disable_unprepare(priv->clk_sdmmc);
  745. clk_put(priv->clk_sdmmc);
  746. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  747. release_mem_region(res->start, resource_size(res));
  748. mmc_free_host(mmc);
  749. dev_info(&pdev->dev, "WMT MCI device removed\n");
  750. return 0;
  751. }
  752. #ifdef CONFIG_PM
  753. static int wmt_mci_suspend(struct device *dev)
  754. {
  755. u32 reg_tmp;
  756. struct mmc_host *mmc = dev_get_drvdata(dev);
  757. struct wmt_mci_priv *priv;
  758. if (!mmc)
  759. return 0;
  760. priv = mmc_priv(mmc);
  761. reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE);
  762. writeb(reg_tmp | BM_SOFT_RESET, priv->sdmmc_base +
  763. SDMMC_BUSMODE);
  764. reg_tmp = readw(priv->sdmmc_base + SDMMC_BLKLEN);
  765. writew(reg_tmp & 0x5FFF, priv->sdmmc_base + SDMMC_BLKLEN);
  766. writeb(0xFF, priv->sdmmc_base + SDMMC_STS0);
  767. writeb(0xFF, priv->sdmmc_base + SDMMC_STS1);
  768. clk_disable(priv->clk_sdmmc);
  769. return 0;
  770. }
  771. static int wmt_mci_resume(struct device *dev)
  772. {
  773. u32 reg_tmp;
  774. struct mmc_host *mmc = dev_get_drvdata(dev);
  775. struct wmt_mci_priv *priv;
  776. if (mmc) {
  777. priv = mmc_priv(mmc);
  778. clk_enable(priv->clk_sdmmc);
  779. reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE);
  780. writeb(reg_tmp | BM_SOFT_RESET, priv->sdmmc_base +
  781. SDMMC_BUSMODE);
  782. reg_tmp = readw(priv->sdmmc_base + SDMMC_BLKLEN);
  783. writew(reg_tmp | (BLKL_GPI_CD | BLKL_INT_ENABLE),
  784. priv->sdmmc_base + SDMMC_BLKLEN);
  785. reg_tmp = readb(priv->sdmmc_base + SDMMC_INTMASK0);
  786. writeb(reg_tmp | INT0_DI_INT_EN, priv->sdmmc_base +
  787. SDMMC_INTMASK0);
  788. }
  789. return 0;
  790. }
  791. static const struct dev_pm_ops wmt_mci_pm = {
  792. .suspend = wmt_mci_suspend,
  793. .resume = wmt_mci_resume,
  794. };
  795. #define wmt_mci_pm_ops (&wmt_mci_pm)
  796. #else /* !CONFIG_PM */
  797. #define wmt_mci_pm_ops NULL
  798. #endif
  799. static struct platform_driver wmt_mci_driver = {
  800. .probe = wmt_mci_probe,
  801. .remove = wmt_mci_remove,
  802. .driver = {
  803. .name = DRIVER_NAME,
  804. .pm = wmt_mci_pm_ops,
  805. .of_match_table = wmt_mci_dt_ids,
  806. },
  807. };
  808. module_platform_driver(wmt_mci_driver);
  809. MODULE_DESCRIPTION("Wondermedia MMC/SD Driver");
  810. MODULE_AUTHOR("Tony Prisk");
  811. MODULE_LICENSE("GPL v2");
  812. MODULE_DEVICE_TABLE(of, wmt_mci_dt_ids);