pci.c 70 KB

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  1. /*
  2. * NVM Express device driver
  3. * Copyright (c) 2011-2014, Intel Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms and conditions of the GNU General Public License,
  7. * version 2, as published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. */
  14. #include <linux/aer.h>
  15. #include <linux/async.h>
  16. #include <linux/blkdev.h>
  17. #include <linux/blk-mq.h>
  18. #include <linux/blk-mq-pci.h>
  19. #include <linux/dmi.h>
  20. #include <linux/init.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/io.h>
  23. #include <linux/mm.h>
  24. #include <linux/module.h>
  25. #include <linux/mutex.h>
  26. #include <linux/once.h>
  27. #include <linux/pci.h>
  28. #include <linux/t10-pi.h>
  29. #include <linux/types.h>
  30. #include <linux/io-64-nonatomic-lo-hi.h>
  31. #include <linux/sed-opal.h>
  32. #include "nvme.h"
  33. #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
  34. #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
  35. #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
  36. /*
  37. * These can be higher, but we need to ensure that any command doesn't
  38. * require an sg allocation that needs more than a page of data.
  39. */
  40. #define NVME_MAX_KB_SZ 4096
  41. #define NVME_MAX_SEGS 127
  42. static int use_threaded_interrupts;
  43. module_param(use_threaded_interrupts, int, 0);
  44. static bool use_cmb_sqes = true;
  45. module_param(use_cmb_sqes, bool, 0444);
  46. MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
  47. static unsigned int max_host_mem_size_mb = 128;
  48. module_param(max_host_mem_size_mb, uint, 0444);
  49. MODULE_PARM_DESC(max_host_mem_size_mb,
  50. "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
  51. static unsigned int sgl_threshold = SZ_32K;
  52. module_param(sgl_threshold, uint, 0644);
  53. MODULE_PARM_DESC(sgl_threshold,
  54. "Use SGLs when average request segment size is larger or equal to "
  55. "this size. Use 0 to disable SGLs.");
  56. static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
  57. static const struct kernel_param_ops io_queue_depth_ops = {
  58. .set = io_queue_depth_set,
  59. .get = param_get_int,
  60. };
  61. static int io_queue_depth = 1024;
  62. module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
  63. MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
  64. struct nvme_dev;
  65. struct nvme_queue;
  66. static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
  67. /*
  68. * Represents an NVM Express device. Each nvme_dev is a PCI function.
  69. */
  70. struct nvme_dev {
  71. struct nvme_queue *queues;
  72. struct blk_mq_tag_set tagset;
  73. struct blk_mq_tag_set admin_tagset;
  74. u32 __iomem *dbs;
  75. struct device *dev;
  76. struct dma_pool *prp_page_pool;
  77. struct dma_pool *prp_small_pool;
  78. unsigned online_queues;
  79. unsigned max_qid;
  80. unsigned int num_vecs;
  81. int q_depth;
  82. u32 db_stride;
  83. void __iomem *bar;
  84. unsigned long bar_mapped_size;
  85. struct work_struct remove_work;
  86. struct mutex shutdown_lock;
  87. bool subsystem;
  88. void __iomem *cmb;
  89. pci_bus_addr_t cmb_bus_addr;
  90. u64 cmb_size;
  91. u32 cmbsz;
  92. u32 cmbloc;
  93. struct nvme_ctrl ctrl;
  94. struct completion ioq_wait;
  95. mempool_t *iod_mempool;
  96. /* shadow doorbell buffer support: */
  97. u32 *dbbuf_dbs;
  98. dma_addr_t dbbuf_dbs_dma_addr;
  99. u32 *dbbuf_eis;
  100. dma_addr_t dbbuf_eis_dma_addr;
  101. /* host memory buffer support: */
  102. u64 host_mem_size;
  103. u32 nr_host_mem_descs;
  104. dma_addr_t host_mem_descs_dma;
  105. struct nvme_host_mem_buf_desc *host_mem_descs;
  106. void **host_mem_desc_bufs;
  107. };
  108. static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
  109. {
  110. int n = 0, ret;
  111. ret = kstrtoint(val, 10, &n);
  112. if (ret != 0 || n < 2)
  113. return -EINVAL;
  114. return param_set_int(val, kp);
  115. }
  116. static inline unsigned int sq_idx(unsigned int qid, u32 stride)
  117. {
  118. return qid * 2 * stride;
  119. }
  120. static inline unsigned int cq_idx(unsigned int qid, u32 stride)
  121. {
  122. return (qid * 2 + 1) * stride;
  123. }
  124. static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
  125. {
  126. return container_of(ctrl, struct nvme_dev, ctrl);
  127. }
  128. /*
  129. * An NVM Express queue. Each device has at least two (one for admin
  130. * commands and one for I/O commands).
  131. */
  132. struct nvme_queue {
  133. struct device *q_dmadev;
  134. struct nvme_dev *dev;
  135. spinlock_t sq_lock;
  136. struct nvme_command *sq_cmds;
  137. struct nvme_command __iomem *sq_cmds_io;
  138. spinlock_t cq_lock ____cacheline_aligned_in_smp;
  139. volatile struct nvme_completion *cqes;
  140. struct blk_mq_tags **tags;
  141. dma_addr_t sq_dma_addr;
  142. dma_addr_t cq_dma_addr;
  143. u32 __iomem *q_db;
  144. u16 q_depth;
  145. s16 cq_vector;
  146. u16 sq_tail;
  147. u16 cq_head;
  148. u16 last_cq_head;
  149. u16 qid;
  150. u8 cq_phase;
  151. u32 *dbbuf_sq_db;
  152. u32 *dbbuf_cq_db;
  153. u32 *dbbuf_sq_ei;
  154. u32 *dbbuf_cq_ei;
  155. };
  156. /*
  157. * The nvme_iod describes the data in an I/O, including the list of PRP
  158. * entries. You can't see it in this data structure because C doesn't let
  159. * me express that. Use nvme_init_iod to ensure there's enough space
  160. * allocated to store the PRP list.
  161. */
  162. struct nvme_iod {
  163. struct nvme_request req;
  164. struct nvme_queue *nvmeq;
  165. bool use_sgl;
  166. int aborted;
  167. int npages; /* In the PRP list. 0 means small pool in use */
  168. int nents; /* Used in scatterlist */
  169. int length; /* Of data, in bytes */
  170. dma_addr_t first_dma;
  171. struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
  172. struct scatterlist *sg;
  173. struct scatterlist inline_sg[0];
  174. };
  175. /*
  176. * Check we didin't inadvertently grow the command struct
  177. */
  178. static inline void _nvme_check_size(void)
  179. {
  180. BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
  181. BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
  182. BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
  183. BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
  184. BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
  185. BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
  186. BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
  187. BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
  188. BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
  189. BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
  190. BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
  191. BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
  192. BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
  193. }
  194. static inline unsigned int nvme_dbbuf_size(u32 stride)
  195. {
  196. return ((num_possible_cpus() + 1) * 8 * stride);
  197. }
  198. static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
  199. {
  200. unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
  201. if (dev->dbbuf_dbs)
  202. return 0;
  203. dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
  204. &dev->dbbuf_dbs_dma_addr,
  205. GFP_KERNEL);
  206. if (!dev->dbbuf_dbs)
  207. return -ENOMEM;
  208. dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
  209. &dev->dbbuf_eis_dma_addr,
  210. GFP_KERNEL);
  211. if (!dev->dbbuf_eis) {
  212. dma_free_coherent(dev->dev, mem_size,
  213. dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
  214. dev->dbbuf_dbs = NULL;
  215. return -ENOMEM;
  216. }
  217. return 0;
  218. }
  219. static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
  220. {
  221. unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
  222. if (dev->dbbuf_dbs) {
  223. dma_free_coherent(dev->dev, mem_size,
  224. dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
  225. dev->dbbuf_dbs = NULL;
  226. }
  227. if (dev->dbbuf_eis) {
  228. dma_free_coherent(dev->dev, mem_size,
  229. dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
  230. dev->dbbuf_eis = NULL;
  231. }
  232. }
  233. static void nvme_dbbuf_init(struct nvme_dev *dev,
  234. struct nvme_queue *nvmeq, int qid)
  235. {
  236. if (!dev->dbbuf_dbs || !qid)
  237. return;
  238. nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
  239. nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
  240. nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
  241. nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
  242. }
  243. static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
  244. {
  245. if (!nvmeq->qid)
  246. return;
  247. nvmeq->dbbuf_sq_db = NULL;
  248. nvmeq->dbbuf_cq_db = NULL;
  249. nvmeq->dbbuf_sq_ei = NULL;
  250. nvmeq->dbbuf_cq_ei = NULL;
  251. }
  252. static void nvme_dbbuf_set(struct nvme_dev *dev)
  253. {
  254. struct nvme_command c;
  255. unsigned int i;
  256. if (!dev->dbbuf_dbs)
  257. return;
  258. memset(&c, 0, sizeof(c));
  259. c.dbbuf.opcode = nvme_admin_dbbuf;
  260. c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
  261. c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
  262. if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
  263. dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
  264. /* Free memory and continue on */
  265. nvme_dbbuf_dma_free(dev);
  266. for (i = 1; i <= dev->online_queues; i++)
  267. nvme_dbbuf_free(&dev->queues[i]);
  268. }
  269. }
  270. static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
  271. {
  272. return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
  273. }
  274. /* Update dbbuf and return true if an MMIO is required */
  275. static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
  276. volatile u32 *dbbuf_ei)
  277. {
  278. if (dbbuf_db) {
  279. u16 old_value;
  280. /*
  281. * Ensure that the queue is written before updating
  282. * the doorbell in memory
  283. */
  284. wmb();
  285. old_value = *dbbuf_db;
  286. *dbbuf_db = value;
  287. /*
  288. * Ensure that the doorbell is updated before reading the event
  289. * index from memory. The controller needs to provide similar
  290. * ordering to ensure the envent index is updated before reading
  291. * the doorbell.
  292. */
  293. mb();
  294. if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
  295. return false;
  296. }
  297. return true;
  298. }
  299. /*
  300. * Max size of iod being embedded in the request payload
  301. */
  302. #define NVME_INT_PAGES 2
  303. #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
  304. /*
  305. * Will slightly overestimate the number of pages needed. This is OK
  306. * as it only leads to a small amount of wasted memory for the lifetime of
  307. * the I/O.
  308. */
  309. static int nvme_npages(unsigned size, struct nvme_dev *dev)
  310. {
  311. unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
  312. dev->ctrl.page_size);
  313. return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
  314. }
  315. /*
  316. * Calculates the number of pages needed for the SGL segments. For example a 4k
  317. * page can accommodate 256 SGL descriptors.
  318. */
  319. static int nvme_pci_npages_sgl(unsigned int num_seg)
  320. {
  321. return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
  322. }
  323. static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
  324. unsigned int size, unsigned int nseg, bool use_sgl)
  325. {
  326. size_t alloc_size;
  327. if (use_sgl)
  328. alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
  329. else
  330. alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
  331. return alloc_size + sizeof(struct scatterlist) * nseg;
  332. }
  333. static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl)
  334. {
  335. unsigned int alloc_size = nvme_pci_iod_alloc_size(dev,
  336. NVME_INT_BYTES(dev), NVME_INT_PAGES,
  337. use_sgl);
  338. return sizeof(struct nvme_iod) + alloc_size;
  339. }
  340. static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
  341. unsigned int hctx_idx)
  342. {
  343. struct nvme_dev *dev = data;
  344. struct nvme_queue *nvmeq = &dev->queues[0];
  345. WARN_ON(hctx_idx != 0);
  346. WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
  347. WARN_ON(nvmeq->tags);
  348. hctx->driver_data = nvmeq;
  349. nvmeq->tags = &dev->admin_tagset.tags[0];
  350. return 0;
  351. }
  352. static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
  353. {
  354. struct nvme_queue *nvmeq = hctx->driver_data;
  355. nvmeq->tags = NULL;
  356. }
  357. static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
  358. unsigned int hctx_idx)
  359. {
  360. struct nvme_dev *dev = data;
  361. struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
  362. if (!nvmeq->tags)
  363. nvmeq->tags = &dev->tagset.tags[hctx_idx];
  364. WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
  365. hctx->driver_data = nvmeq;
  366. return 0;
  367. }
  368. static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
  369. unsigned int hctx_idx, unsigned int numa_node)
  370. {
  371. struct nvme_dev *dev = set->driver_data;
  372. struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
  373. int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
  374. struct nvme_queue *nvmeq = &dev->queues[queue_idx];
  375. BUG_ON(!nvmeq);
  376. iod->nvmeq = nvmeq;
  377. nvme_req(req)->ctrl = &dev->ctrl;
  378. return 0;
  379. }
  380. static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
  381. {
  382. struct nvme_dev *dev = set->driver_data;
  383. return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev),
  384. dev->num_vecs > 1 ? 1 /* admin queue */ : 0);
  385. }
  386. /**
  387. * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
  388. * @nvmeq: The queue to use
  389. * @cmd: The command to send
  390. */
  391. static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
  392. {
  393. spin_lock(&nvmeq->sq_lock);
  394. if (nvmeq->sq_cmds_io)
  395. memcpy_toio(&nvmeq->sq_cmds_io[nvmeq->sq_tail], cmd,
  396. sizeof(*cmd));
  397. else
  398. memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd));
  399. if (++nvmeq->sq_tail == nvmeq->q_depth)
  400. nvmeq->sq_tail = 0;
  401. if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
  402. nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
  403. writel(nvmeq->sq_tail, nvmeq->q_db);
  404. spin_unlock(&nvmeq->sq_lock);
  405. }
  406. static void **nvme_pci_iod_list(struct request *req)
  407. {
  408. struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
  409. return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
  410. }
  411. static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
  412. {
  413. struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
  414. int nseg = blk_rq_nr_phys_segments(req);
  415. unsigned int avg_seg_size;
  416. if (nseg == 0)
  417. return false;
  418. avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
  419. if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
  420. return false;
  421. if (!iod->nvmeq->qid)
  422. return false;
  423. if (!sgl_threshold || avg_seg_size < sgl_threshold)
  424. return false;
  425. return true;
  426. }
  427. static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev)
  428. {
  429. struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
  430. int nseg = blk_rq_nr_phys_segments(rq);
  431. unsigned int size = blk_rq_payload_bytes(rq);
  432. iod->use_sgl = nvme_pci_use_sgls(dev, rq);
  433. if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
  434. iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
  435. if (!iod->sg)
  436. return BLK_STS_RESOURCE;
  437. } else {
  438. iod->sg = iod->inline_sg;
  439. }
  440. iod->aborted = 0;
  441. iod->npages = -1;
  442. iod->nents = 0;
  443. iod->length = size;
  444. return BLK_STS_OK;
  445. }
  446. static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
  447. {
  448. struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
  449. const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
  450. dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
  451. int i;
  452. if (iod->npages == 0)
  453. dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
  454. dma_addr);
  455. for (i = 0; i < iod->npages; i++) {
  456. void *addr = nvme_pci_iod_list(req)[i];
  457. if (iod->use_sgl) {
  458. struct nvme_sgl_desc *sg_list = addr;
  459. next_dma_addr =
  460. le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
  461. } else {
  462. __le64 *prp_list = addr;
  463. next_dma_addr = le64_to_cpu(prp_list[last_prp]);
  464. }
  465. dma_pool_free(dev->prp_page_pool, addr, dma_addr);
  466. dma_addr = next_dma_addr;
  467. }
  468. if (iod->sg != iod->inline_sg)
  469. mempool_free(iod->sg, dev->iod_mempool);
  470. }
  471. static void nvme_print_sgl(struct scatterlist *sgl, int nents)
  472. {
  473. int i;
  474. struct scatterlist *sg;
  475. for_each_sg(sgl, sg, nents, i) {
  476. dma_addr_t phys = sg_phys(sg);
  477. pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
  478. "dma_address:%pad dma_length:%d\n",
  479. i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
  480. sg_dma_len(sg));
  481. }
  482. }
  483. static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
  484. struct request *req, struct nvme_rw_command *cmnd)
  485. {
  486. struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
  487. struct dma_pool *pool;
  488. int length = blk_rq_payload_bytes(req);
  489. struct scatterlist *sg = iod->sg;
  490. int dma_len = sg_dma_len(sg);
  491. u64 dma_addr = sg_dma_address(sg);
  492. u32 page_size = dev->ctrl.page_size;
  493. int offset = dma_addr & (page_size - 1);
  494. __le64 *prp_list;
  495. void **list = nvme_pci_iod_list(req);
  496. dma_addr_t prp_dma;
  497. int nprps, i;
  498. length -= (page_size - offset);
  499. if (length <= 0) {
  500. iod->first_dma = 0;
  501. goto done;
  502. }
  503. dma_len -= (page_size - offset);
  504. if (dma_len) {
  505. dma_addr += (page_size - offset);
  506. } else {
  507. sg = sg_next(sg);
  508. dma_addr = sg_dma_address(sg);
  509. dma_len = sg_dma_len(sg);
  510. }
  511. if (length <= page_size) {
  512. iod->first_dma = dma_addr;
  513. goto done;
  514. }
  515. nprps = DIV_ROUND_UP(length, page_size);
  516. if (nprps <= (256 / 8)) {
  517. pool = dev->prp_small_pool;
  518. iod->npages = 0;
  519. } else {
  520. pool = dev->prp_page_pool;
  521. iod->npages = 1;
  522. }
  523. prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
  524. if (!prp_list) {
  525. iod->first_dma = dma_addr;
  526. iod->npages = -1;
  527. return BLK_STS_RESOURCE;
  528. }
  529. list[0] = prp_list;
  530. iod->first_dma = prp_dma;
  531. i = 0;
  532. for (;;) {
  533. if (i == page_size >> 3) {
  534. __le64 *old_prp_list = prp_list;
  535. prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
  536. if (!prp_list)
  537. return BLK_STS_RESOURCE;
  538. list[iod->npages++] = prp_list;
  539. prp_list[0] = old_prp_list[i - 1];
  540. old_prp_list[i - 1] = cpu_to_le64(prp_dma);
  541. i = 1;
  542. }
  543. prp_list[i++] = cpu_to_le64(dma_addr);
  544. dma_len -= page_size;
  545. dma_addr += page_size;
  546. length -= page_size;
  547. if (length <= 0)
  548. break;
  549. if (dma_len > 0)
  550. continue;
  551. if (unlikely(dma_len < 0))
  552. goto bad_sgl;
  553. sg = sg_next(sg);
  554. dma_addr = sg_dma_address(sg);
  555. dma_len = sg_dma_len(sg);
  556. }
  557. done:
  558. cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
  559. cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
  560. return BLK_STS_OK;
  561. bad_sgl:
  562. WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
  563. "Invalid SGL for payload:%d nents:%d\n",
  564. blk_rq_payload_bytes(req), iod->nents);
  565. return BLK_STS_IOERR;
  566. }
  567. static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
  568. struct scatterlist *sg)
  569. {
  570. sge->addr = cpu_to_le64(sg_dma_address(sg));
  571. sge->length = cpu_to_le32(sg_dma_len(sg));
  572. sge->type = NVME_SGL_FMT_DATA_DESC << 4;
  573. }
  574. static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
  575. dma_addr_t dma_addr, int entries)
  576. {
  577. sge->addr = cpu_to_le64(dma_addr);
  578. if (entries < SGES_PER_PAGE) {
  579. sge->length = cpu_to_le32(entries * sizeof(*sge));
  580. sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
  581. } else {
  582. sge->length = cpu_to_le32(PAGE_SIZE);
  583. sge->type = NVME_SGL_FMT_SEG_DESC << 4;
  584. }
  585. }
  586. static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
  587. struct request *req, struct nvme_rw_command *cmd, int entries)
  588. {
  589. struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
  590. struct dma_pool *pool;
  591. struct nvme_sgl_desc *sg_list;
  592. struct scatterlist *sg = iod->sg;
  593. dma_addr_t sgl_dma;
  594. int i = 0;
  595. /* setting the transfer type as SGL */
  596. cmd->flags = NVME_CMD_SGL_METABUF;
  597. if (entries == 1) {
  598. nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
  599. return BLK_STS_OK;
  600. }
  601. if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
  602. pool = dev->prp_small_pool;
  603. iod->npages = 0;
  604. } else {
  605. pool = dev->prp_page_pool;
  606. iod->npages = 1;
  607. }
  608. sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
  609. if (!sg_list) {
  610. iod->npages = -1;
  611. return BLK_STS_RESOURCE;
  612. }
  613. nvme_pci_iod_list(req)[0] = sg_list;
  614. iod->first_dma = sgl_dma;
  615. nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
  616. do {
  617. if (i == SGES_PER_PAGE) {
  618. struct nvme_sgl_desc *old_sg_desc = sg_list;
  619. struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
  620. sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
  621. if (!sg_list)
  622. return BLK_STS_RESOURCE;
  623. i = 0;
  624. nvme_pci_iod_list(req)[iod->npages++] = sg_list;
  625. sg_list[i++] = *link;
  626. nvme_pci_sgl_set_seg(link, sgl_dma, entries);
  627. }
  628. nvme_pci_sgl_set_data(&sg_list[i++], sg);
  629. sg = sg_next(sg);
  630. } while (--entries > 0);
  631. return BLK_STS_OK;
  632. }
  633. static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
  634. struct nvme_command *cmnd)
  635. {
  636. struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
  637. struct request_queue *q = req->q;
  638. enum dma_data_direction dma_dir = rq_data_dir(req) ?
  639. DMA_TO_DEVICE : DMA_FROM_DEVICE;
  640. blk_status_t ret = BLK_STS_IOERR;
  641. int nr_mapped;
  642. sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
  643. iod->nents = blk_rq_map_sg(q, req, iod->sg);
  644. if (!iod->nents)
  645. goto out;
  646. ret = BLK_STS_RESOURCE;
  647. nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir,
  648. DMA_ATTR_NO_WARN);
  649. if (!nr_mapped)
  650. goto out;
  651. if (iod->use_sgl)
  652. ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
  653. else
  654. ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
  655. if (ret != BLK_STS_OK)
  656. goto out_unmap;
  657. ret = BLK_STS_IOERR;
  658. if (blk_integrity_rq(req)) {
  659. if (blk_rq_count_integrity_sg(q, req->bio) != 1)
  660. goto out_unmap;
  661. sg_init_table(&iod->meta_sg, 1);
  662. if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
  663. goto out_unmap;
  664. if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
  665. goto out_unmap;
  666. }
  667. if (blk_integrity_rq(req))
  668. cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
  669. return BLK_STS_OK;
  670. out_unmap:
  671. dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
  672. out:
  673. return ret;
  674. }
  675. static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
  676. {
  677. struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
  678. enum dma_data_direction dma_dir = rq_data_dir(req) ?
  679. DMA_TO_DEVICE : DMA_FROM_DEVICE;
  680. if (iod->nents) {
  681. dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
  682. if (blk_integrity_rq(req))
  683. dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
  684. }
  685. nvme_cleanup_cmd(req);
  686. nvme_free_iod(dev, req);
  687. }
  688. /*
  689. * NOTE: ns is NULL when called on the admin queue.
  690. */
  691. static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
  692. const struct blk_mq_queue_data *bd)
  693. {
  694. struct nvme_ns *ns = hctx->queue->queuedata;
  695. struct nvme_queue *nvmeq = hctx->driver_data;
  696. struct nvme_dev *dev = nvmeq->dev;
  697. struct request *req = bd->rq;
  698. struct nvme_command cmnd;
  699. blk_status_t ret;
  700. /*
  701. * We should not need to do this, but we're still using this to
  702. * ensure we can drain requests on a dying queue.
  703. */
  704. if (unlikely(nvmeq->cq_vector < 0))
  705. return BLK_STS_IOERR;
  706. ret = nvme_setup_cmd(ns, req, &cmnd);
  707. if (ret)
  708. return ret;
  709. ret = nvme_init_iod(req, dev);
  710. if (ret)
  711. goto out_free_cmd;
  712. if (blk_rq_nr_phys_segments(req)) {
  713. ret = nvme_map_data(dev, req, &cmnd);
  714. if (ret)
  715. goto out_cleanup_iod;
  716. }
  717. blk_mq_start_request(req);
  718. nvme_submit_cmd(nvmeq, &cmnd);
  719. return BLK_STS_OK;
  720. out_cleanup_iod:
  721. nvme_free_iod(dev, req);
  722. out_free_cmd:
  723. nvme_cleanup_cmd(req);
  724. return ret;
  725. }
  726. static void nvme_pci_complete_rq(struct request *req)
  727. {
  728. struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
  729. nvme_unmap_data(iod->nvmeq->dev, req);
  730. nvme_complete_rq(req);
  731. }
  732. /* We read the CQE phase first to check if the rest of the entry is valid */
  733. static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
  734. {
  735. return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
  736. nvmeq->cq_phase;
  737. }
  738. static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
  739. {
  740. u16 head = nvmeq->cq_head;
  741. if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
  742. nvmeq->dbbuf_cq_ei))
  743. writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
  744. }
  745. static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
  746. {
  747. volatile struct nvme_completion *cqe = &nvmeq->cqes[idx];
  748. struct request *req;
  749. if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
  750. dev_warn(nvmeq->dev->ctrl.device,
  751. "invalid id %d completed on queue %d\n",
  752. cqe->command_id, le16_to_cpu(cqe->sq_id));
  753. return;
  754. }
  755. /*
  756. * AEN requests are special as they don't time out and can
  757. * survive any kind of queue freeze and often don't respond to
  758. * aborts. We don't even bother to allocate a struct request
  759. * for them but rather special case them here.
  760. */
  761. if (unlikely(nvmeq->qid == 0 &&
  762. cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) {
  763. nvme_complete_async_event(&nvmeq->dev->ctrl,
  764. cqe->status, &cqe->result);
  765. return;
  766. }
  767. req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
  768. nvme_end_request(req, cqe->status, cqe->result);
  769. }
  770. static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end)
  771. {
  772. while (start != end) {
  773. nvme_handle_cqe(nvmeq, start);
  774. if (++start == nvmeq->q_depth)
  775. start = 0;
  776. }
  777. }
  778. static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
  779. {
  780. if (nvmeq->cq_head == nvmeq->q_depth - 1) {
  781. nvmeq->cq_head = 0;
  782. nvmeq->cq_phase = !nvmeq->cq_phase;
  783. } else {
  784. nvmeq->cq_head++;
  785. }
  786. }
  787. static inline bool nvme_process_cq(struct nvme_queue *nvmeq, u16 *start,
  788. u16 *end, int tag)
  789. {
  790. bool found = false;
  791. *start = nvmeq->cq_head;
  792. while (!found && nvme_cqe_pending(nvmeq)) {
  793. if (nvmeq->cqes[nvmeq->cq_head].command_id == tag)
  794. found = true;
  795. nvme_update_cq_head(nvmeq);
  796. }
  797. *end = nvmeq->cq_head;
  798. if (*start != *end)
  799. nvme_ring_cq_doorbell(nvmeq);
  800. return found;
  801. }
  802. static irqreturn_t nvme_irq(int irq, void *data)
  803. {
  804. struct nvme_queue *nvmeq = data;
  805. irqreturn_t ret = IRQ_NONE;
  806. u16 start, end;
  807. spin_lock(&nvmeq->cq_lock);
  808. if (nvmeq->cq_head != nvmeq->last_cq_head)
  809. ret = IRQ_HANDLED;
  810. nvme_process_cq(nvmeq, &start, &end, -1);
  811. nvmeq->last_cq_head = nvmeq->cq_head;
  812. spin_unlock(&nvmeq->cq_lock);
  813. if (start != end) {
  814. nvme_complete_cqes(nvmeq, start, end);
  815. return IRQ_HANDLED;
  816. }
  817. return ret;
  818. }
  819. static irqreturn_t nvme_irq_check(int irq, void *data)
  820. {
  821. struct nvme_queue *nvmeq = data;
  822. if (nvme_cqe_pending(nvmeq))
  823. return IRQ_WAKE_THREAD;
  824. return IRQ_NONE;
  825. }
  826. static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag)
  827. {
  828. u16 start, end;
  829. bool found;
  830. if (!nvme_cqe_pending(nvmeq))
  831. return 0;
  832. spin_lock_irq(&nvmeq->cq_lock);
  833. found = nvme_process_cq(nvmeq, &start, &end, tag);
  834. spin_unlock_irq(&nvmeq->cq_lock);
  835. nvme_complete_cqes(nvmeq, start, end);
  836. return found;
  837. }
  838. static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
  839. {
  840. struct nvme_queue *nvmeq = hctx->driver_data;
  841. return __nvme_poll(nvmeq, tag);
  842. }
  843. static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
  844. {
  845. struct nvme_dev *dev = to_nvme_dev(ctrl);
  846. struct nvme_queue *nvmeq = &dev->queues[0];
  847. struct nvme_command c;
  848. memset(&c, 0, sizeof(c));
  849. c.common.opcode = nvme_admin_async_event;
  850. c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
  851. nvme_submit_cmd(nvmeq, &c);
  852. }
  853. static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
  854. {
  855. struct nvme_command c;
  856. memset(&c, 0, sizeof(c));
  857. c.delete_queue.opcode = opcode;
  858. c.delete_queue.qid = cpu_to_le16(id);
  859. return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
  860. }
  861. static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
  862. struct nvme_queue *nvmeq, s16 vector)
  863. {
  864. struct nvme_command c;
  865. int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
  866. /*
  867. * Note: we (ab)use the fact that the prp fields survive if no data
  868. * is attached to the request.
  869. */
  870. memset(&c, 0, sizeof(c));
  871. c.create_cq.opcode = nvme_admin_create_cq;
  872. c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
  873. c.create_cq.cqid = cpu_to_le16(qid);
  874. c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
  875. c.create_cq.cq_flags = cpu_to_le16(flags);
  876. c.create_cq.irq_vector = cpu_to_le16(vector);
  877. return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
  878. }
  879. static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
  880. struct nvme_queue *nvmeq)
  881. {
  882. struct nvme_ctrl *ctrl = &dev->ctrl;
  883. struct nvme_command c;
  884. int flags = NVME_QUEUE_PHYS_CONTIG;
  885. /*
  886. * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
  887. * set. Since URGENT priority is zeroes, it makes all queues
  888. * URGENT.
  889. */
  890. if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
  891. flags |= NVME_SQ_PRIO_MEDIUM;
  892. /*
  893. * Note: we (ab)use the fact that the prp fields survive if no data
  894. * is attached to the request.
  895. */
  896. memset(&c, 0, sizeof(c));
  897. c.create_sq.opcode = nvme_admin_create_sq;
  898. c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
  899. c.create_sq.sqid = cpu_to_le16(qid);
  900. c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
  901. c.create_sq.sq_flags = cpu_to_le16(flags);
  902. c.create_sq.cqid = cpu_to_le16(qid);
  903. return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
  904. }
  905. static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
  906. {
  907. return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
  908. }
  909. static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
  910. {
  911. return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
  912. }
  913. static void abort_endio(struct request *req, blk_status_t error)
  914. {
  915. struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
  916. struct nvme_queue *nvmeq = iod->nvmeq;
  917. dev_warn(nvmeq->dev->ctrl.device,
  918. "Abort status: 0x%x", nvme_req(req)->status);
  919. atomic_inc(&nvmeq->dev->ctrl.abort_limit);
  920. blk_mq_free_request(req);
  921. }
  922. static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
  923. {
  924. /* If true, indicates loss of adapter communication, possibly by a
  925. * NVMe Subsystem reset.
  926. */
  927. bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
  928. /* If there is a reset/reinit ongoing, we shouldn't reset again. */
  929. switch (dev->ctrl.state) {
  930. case NVME_CTRL_RESETTING:
  931. case NVME_CTRL_CONNECTING:
  932. return false;
  933. default:
  934. break;
  935. }
  936. /* We shouldn't reset unless the controller is on fatal error state
  937. * _or_ if we lost the communication with it.
  938. */
  939. if (!(csts & NVME_CSTS_CFS) && !nssro)
  940. return false;
  941. return true;
  942. }
  943. static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
  944. {
  945. /* Read a config register to help see what died. */
  946. u16 pci_status;
  947. int result;
  948. result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
  949. &pci_status);
  950. if (result == PCIBIOS_SUCCESSFUL)
  951. dev_warn(dev->ctrl.device,
  952. "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
  953. csts, pci_status);
  954. else
  955. dev_warn(dev->ctrl.device,
  956. "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
  957. csts, result);
  958. }
  959. static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
  960. {
  961. struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
  962. struct nvme_queue *nvmeq = iod->nvmeq;
  963. struct nvme_dev *dev = nvmeq->dev;
  964. struct request *abort_req;
  965. struct nvme_command cmd;
  966. bool shutdown = false;
  967. u32 csts = readl(dev->bar + NVME_REG_CSTS);
  968. /* If PCI error recovery process is happening, we cannot reset or
  969. * the recovery mechanism will surely fail.
  970. */
  971. mb();
  972. if (pci_channel_offline(to_pci_dev(dev->dev)))
  973. return BLK_EH_RESET_TIMER;
  974. /*
  975. * Reset immediately if the controller is failed
  976. */
  977. if (nvme_should_reset(dev, csts)) {
  978. nvme_warn_reset(dev, csts);
  979. nvme_dev_disable(dev, false);
  980. nvme_reset_ctrl(&dev->ctrl);
  981. return BLK_EH_DONE;
  982. }
  983. /*
  984. * Did we miss an interrupt?
  985. */
  986. if (__nvme_poll(nvmeq, req->tag)) {
  987. dev_warn(dev->ctrl.device,
  988. "I/O %d QID %d timeout, completion polled\n",
  989. req->tag, nvmeq->qid);
  990. return BLK_EH_DONE;
  991. }
  992. /*
  993. * Shutdown immediately if controller times out while starting. The
  994. * reset work will see the pci device disabled when it gets the forced
  995. * cancellation error. All outstanding requests are completed on
  996. * shutdown, so we return BLK_EH_DONE.
  997. */
  998. switch (dev->ctrl.state) {
  999. case NVME_CTRL_DELETING:
  1000. shutdown = true;
  1001. case NVME_CTRL_CONNECTING:
  1002. case NVME_CTRL_RESETTING:
  1003. dev_warn_ratelimited(dev->ctrl.device,
  1004. "I/O %d QID %d timeout, disable controller\n",
  1005. req->tag, nvmeq->qid);
  1006. nvme_dev_disable(dev, shutdown);
  1007. nvme_req(req)->flags |= NVME_REQ_CANCELLED;
  1008. return BLK_EH_DONE;
  1009. default:
  1010. break;
  1011. }
  1012. /*
  1013. * Shutdown the controller immediately and schedule a reset if the
  1014. * command was already aborted once before and still hasn't been
  1015. * returned to the driver, or if this is the admin queue.
  1016. */
  1017. if (!nvmeq->qid || iod->aborted) {
  1018. dev_warn(dev->ctrl.device,
  1019. "I/O %d QID %d timeout, reset controller\n",
  1020. req->tag, nvmeq->qid);
  1021. nvme_dev_disable(dev, false);
  1022. nvme_reset_ctrl(&dev->ctrl);
  1023. nvme_req(req)->flags |= NVME_REQ_CANCELLED;
  1024. return BLK_EH_DONE;
  1025. }
  1026. if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
  1027. atomic_inc(&dev->ctrl.abort_limit);
  1028. return BLK_EH_RESET_TIMER;
  1029. }
  1030. iod->aborted = 1;
  1031. memset(&cmd, 0, sizeof(cmd));
  1032. cmd.abort.opcode = nvme_admin_abort_cmd;
  1033. cmd.abort.cid = req->tag;
  1034. cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
  1035. dev_warn(nvmeq->dev->ctrl.device,
  1036. "I/O %d QID %d timeout, aborting\n",
  1037. req->tag, nvmeq->qid);
  1038. abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
  1039. BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
  1040. if (IS_ERR(abort_req)) {
  1041. atomic_inc(&dev->ctrl.abort_limit);
  1042. return BLK_EH_RESET_TIMER;
  1043. }
  1044. abort_req->timeout = ADMIN_TIMEOUT;
  1045. abort_req->end_io_data = NULL;
  1046. blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
  1047. /*
  1048. * The aborted req will be completed on receiving the abort req.
  1049. * We enable the timer again. If hit twice, it'll cause a device reset,
  1050. * as the device then is in a faulty state.
  1051. */
  1052. return BLK_EH_RESET_TIMER;
  1053. }
  1054. static void nvme_free_queue(struct nvme_queue *nvmeq)
  1055. {
  1056. dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
  1057. (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
  1058. if (nvmeq->sq_cmds)
  1059. dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
  1060. nvmeq->sq_cmds, nvmeq->sq_dma_addr);
  1061. }
  1062. static void nvme_free_queues(struct nvme_dev *dev, int lowest)
  1063. {
  1064. int i;
  1065. for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
  1066. dev->ctrl.queue_count--;
  1067. nvme_free_queue(&dev->queues[i]);
  1068. }
  1069. }
  1070. /**
  1071. * nvme_suspend_queue - put queue into suspended state
  1072. * @nvmeq - queue to suspend
  1073. */
  1074. static int nvme_suspend_queue(struct nvme_queue *nvmeq)
  1075. {
  1076. int vector;
  1077. spin_lock_irq(&nvmeq->cq_lock);
  1078. if (nvmeq->cq_vector == -1) {
  1079. spin_unlock_irq(&nvmeq->cq_lock);
  1080. return 1;
  1081. }
  1082. vector = nvmeq->cq_vector;
  1083. nvmeq->dev->online_queues--;
  1084. nvmeq->cq_vector = -1;
  1085. spin_unlock_irq(&nvmeq->cq_lock);
  1086. /*
  1087. * Ensure that nvme_queue_rq() sees it ->cq_vector == -1 without
  1088. * having to grab the lock.
  1089. */
  1090. mb();
  1091. if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
  1092. blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
  1093. pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq);
  1094. return 0;
  1095. }
  1096. static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
  1097. {
  1098. struct nvme_queue *nvmeq = &dev->queues[0];
  1099. u16 start, end;
  1100. if (shutdown)
  1101. nvme_shutdown_ctrl(&dev->ctrl);
  1102. else
  1103. nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
  1104. spin_lock_irq(&nvmeq->cq_lock);
  1105. nvme_process_cq(nvmeq, &start, &end, -1);
  1106. spin_unlock_irq(&nvmeq->cq_lock);
  1107. nvme_complete_cqes(nvmeq, start, end);
  1108. }
  1109. static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
  1110. int entry_size)
  1111. {
  1112. int q_depth = dev->q_depth;
  1113. unsigned q_size_aligned = roundup(q_depth * entry_size,
  1114. dev->ctrl.page_size);
  1115. if (q_size_aligned * nr_io_queues > dev->cmb_size) {
  1116. u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
  1117. mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
  1118. q_depth = div_u64(mem_per_q, entry_size);
  1119. /*
  1120. * Ensure the reduced q_depth is above some threshold where it
  1121. * would be better to map queues in system memory with the
  1122. * original depth
  1123. */
  1124. if (q_depth < 64)
  1125. return -ENOMEM;
  1126. }
  1127. return q_depth;
  1128. }
  1129. static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
  1130. int qid, int depth)
  1131. {
  1132. /* CMB SQEs will be mapped before creation */
  1133. if (qid && dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS))
  1134. return 0;
  1135. nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
  1136. &nvmeq->sq_dma_addr, GFP_KERNEL);
  1137. if (!nvmeq->sq_cmds)
  1138. return -ENOMEM;
  1139. return 0;
  1140. }
  1141. static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
  1142. {
  1143. struct nvme_queue *nvmeq = &dev->queues[qid];
  1144. if (dev->ctrl.queue_count > qid)
  1145. return 0;
  1146. nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
  1147. &nvmeq->cq_dma_addr, GFP_KERNEL);
  1148. if (!nvmeq->cqes)
  1149. goto free_nvmeq;
  1150. if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
  1151. goto free_cqdma;
  1152. nvmeq->q_dmadev = dev->dev;
  1153. nvmeq->dev = dev;
  1154. spin_lock_init(&nvmeq->sq_lock);
  1155. spin_lock_init(&nvmeq->cq_lock);
  1156. nvmeq->cq_head = 0;
  1157. nvmeq->cq_phase = 1;
  1158. nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
  1159. nvmeq->q_depth = depth;
  1160. nvmeq->qid = qid;
  1161. nvmeq->cq_vector = -1;
  1162. dev->ctrl.queue_count++;
  1163. return 0;
  1164. free_cqdma:
  1165. dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
  1166. nvmeq->cq_dma_addr);
  1167. free_nvmeq:
  1168. return -ENOMEM;
  1169. }
  1170. static int queue_request_irq(struct nvme_queue *nvmeq)
  1171. {
  1172. struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
  1173. int nr = nvmeq->dev->ctrl.instance;
  1174. if (use_threaded_interrupts) {
  1175. return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
  1176. nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
  1177. } else {
  1178. return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
  1179. NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
  1180. }
  1181. }
  1182. static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
  1183. {
  1184. struct nvme_dev *dev = nvmeq->dev;
  1185. spin_lock_irq(&nvmeq->cq_lock);
  1186. nvmeq->sq_tail = 0;
  1187. nvmeq->cq_head = 0;
  1188. nvmeq->cq_phase = 1;
  1189. nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
  1190. memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
  1191. nvme_dbbuf_init(dev, nvmeq, qid);
  1192. dev->online_queues++;
  1193. spin_unlock_irq(&nvmeq->cq_lock);
  1194. }
  1195. static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
  1196. {
  1197. struct nvme_dev *dev = nvmeq->dev;
  1198. int result;
  1199. s16 vector;
  1200. if (dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
  1201. unsigned offset = (qid - 1) * roundup(SQ_SIZE(nvmeq->q_depth),
  1202. dev->ctrl.page_size);
  1203. nvmeq->sq_dma_addr = dev->cmb_bus_addr + offset;
  1204. nvmeq->sq_cmds_io = dev->cmb + offset;
  1205. }
  1206. /*
  1207. * A queue's vector matches the queue identifier unless the controller
  1208. * has only one vector available.
  1209. */
  1210. vector = dev->num_vecs == 1 ? 0 : qid;
  1211. result = adapter_alloc_cq(dev, qid, nvmeq, vector);
  1212. if (result)
  1213. return result;
  1214. result = adapter_alloc_sq(dev, qid, nvmeq);
  1215. if (result < 0)
  1216. return result;
  1217. else if (result)
  1218. goto release_cq;
  1219. /*
  1220. * Set cq_vector after alloc cq/sq, otherwise nvme_suspend_queue will
  1221. * invoke free_irq for it and cause a 'Trying to free already-free IRQ
  1222. * xxx' warning if the create CQ/SQ command times out.
  1223. */
  1224. nvmeq->cq_vector = vector;
  1225. nvme_init_queue(nvmeq, qid);
  1226. result = queue_request_irq(nvmeq);
  1227. if (result < 0)
  1228. goto release_sq;
  1229. return result;
  1230. release_sq:
  1231. nvmeq->cq_vector = -1;
  1232. dev->online_queues--;
  1233. adapter_delete_sq(dev, qid);
  1234. release_cq:
  1235. adapter_delete_cq(dev, qid);
  1236. return result;
  1237. }
  1238. static const struct blk_mq_ops nvme_mq_admin_ops = {
  1239. .queue_rq = nvme_queue_rq,
  1240. .complete = nvme_pci_complete_rq,
  1241. .init_hctx = nvme_admin_init_hctx,
  1242. .exit_hctx = nvme_admin_exit_hctx,
  1243. .init_request = nvme_init_request,
  1244. .timeout = nvme_timeout,
  1245. };
  1246. static const struct blk_mq_ops nvme_mq_ops = {
  1247. .queue_rq = nvme_queue_rq,
  1248. .complete = nvme_pci_complete_rq,
  1249. .init_hctx = nvme_init_hctx,
  1250. .init_request = nvme_init_request,
  1251. .map_queues = nvme_pci_map_queues,
  1252. .timeout = nvme_timeout,
  1253. .poll = nvme_poll,
  1254. };
  1255. static void nvme_dev_remove_admin(struct nvme_dev *dev)
  1256. {
  1257. if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
  1258. /*
  1259. * If the controller was reset during removal, it's possible
  1260. * user requests may be waiting on a stopped queue. Start the
  1261. * queue to flush these to completion.
  1262. */
  1263. blk_mq_unquiesce_queue(dev->ctrl.admin_q);
  1264. blk_cleanup_queue(dev->ctrl.admin_q);
  1265. blk_mq_free_tag_set(&dev->admin_tagset);
  1266. }
  1267. }
  1268. static int nvme_alloc_admin_tags(struct nvme_dev *dev)
  1269. {
  1270. if (!dev->ctrl.admin_q) {
  1271. dev->admin_tagset.ops = &nvme_mq_admin_ops;
  1272. dev->admin_tagset.nr_hw_queues = 1;
  1273. dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
  1274. dev->admin_tagset.timeout = ADMIN_TIMEOUT;
  1275. dev->admin_tagset.numa_node = dev_to_node(dev->dev);
  1276. dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false);
  1277. dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
  1278. dev->admin_tagset.driver_data = dev;
  1279. if (blk_mq_alloc_tag_set(&dev->admin_tagset))
  1280. return -ENOMEM;
  1281. dev->ctrl.admin_tagset = &dev->admin_tagset;
  1282. dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
  1283. if (IS_ERR(dev->ctrl.admin_q)) {
  1284. blk_mq_free_tag_set(&dev->admin_tagset);
  1285. return -ENOMEM;
  1286. }
  1287. if (!blk_get_queue(dev->ctrl.admin_q)) {
  1288. nvme_dev_remove_admin(dev);
  1289. dev->ctrl.admin_q = NULL;
  1290. return -ENODEV;
  1291. }
  1292. } else
  1293. blk_mq_unquiesce_queue(dev->ctrl.admin_q);
  1294. return 0;
  1295. }
  1296. static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
  1297. {
  1298. return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
  1299. }
  1300. static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
  1301. {
  1302. struct pci_dev *pdev = to_pci_dev(dev->dev);
  1303. if (size <= dev->bar_mapped_size)
  1304. return 0;
  1305. if (size > pci_resource_len(pdev, 0))
  1306. return -ENOMEM;
  1307. if (dev->bar)
  1308. iounmap(dev->bar);
  1309. dev->bar = ioremap(pci_resource_start(pdev, 0), size);
  1310. if (!dev->bar) {
  1311. dev->bar_mapped_size = 0;
  1312. return -ENOMEM;
  1313. }
  1314. dev->bar_mapped_size = size;
  1315. dev->dbs = dev->bar + NVME_REG_DBS;
  1316. return 0;
  1317. }
  1318. static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
  1319. {
  1320. int result;
  1321. u32 aqa;
  1322. struct nvme_queue *nvmeq;
  1323. result = nvme_remap_bar(dev, db_bar_size(dev, 0));
  1324. if (result < 0)
  1325. return result;
  1326. dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
  1327. NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
  1328. if (dev->subsystem &&
  1329. (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
  1330. writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
  1331. result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
  1332. if (result < 0)
  1333. return result;
  1334. result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
  1335. if (result)
  1336. return result;
  1337. nvmeq = &dev->queues[0];
  1338. aqa = nvmeq->q_depth - 1;
  1339. aqa |= aqa << 16;
  1340. writel(aqa, dev->bar + NVME_REG_AQA);
  1341. lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
  1342. lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
  1343. result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap);
  1344. if (result)
  1345. return result;
  1346. nvmeq->cq_vector = 0;
  1347. nvme_init_queue(nvmeq, 0);
  1348. result = queue_request_irq(nvmeq);
  1349. if (result) {
  1350. nvmeq->cq_vector = -1;
  1351. return result;
  1352. }
  1353. return result;
  1354. }
  1355. static int nvme_create_io_queues(struct nvme_dev *dev)
  1356. {
  1357. unsigned i, max;
  1358. int ret = 0;
  1359. for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
  1360. if (nvme_alloc_queue(dev, i, dev->q_depth)) {
  1361. ret = -ENOMEM;
  1362. break;
  1363. }
  1364. }
  1365. max = min(dev->max_qid, dev->ctrl.queue_count - 1);
  1366. for (i = dev->online_queues; i <= max; i++) {
  1367. ret = nvme_create_queue(&dev->queues[i], i);
  1368. if (ret)
  1369. break;
  1370. }
  1371. /*
  1372. * Ignore failing Create SQ/CQ commands, we can continue with less
  1373. * than the desired amount of queues, and even a controller without
  1374. * I/O queues can still be used to issue admin commands. This might
  1375. * be useful to upgrade a buggy firmware for example.
  1376. */
  1377. return ret >= 0 ? 0 : ret;
  1378. }
  1379. static ssize_t nvme_cmb_show(struct device *dev,
  1380. struct device_attribute *attr,
  1381. char *buf)
  1382. {
  1383. struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
  1384. return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
  1385. ndev->cmbloc, ndev->cmbsz);
  1386. }
  1387. static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
  1388. static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
  1389. {
  1390. u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
  1391. return 1ULL << (12 + 4 * szu);
  1392. }
  1393. static u32 nvme_cmb_size(struct nvme_dev *dev)
  1394. {
  1395. return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
  1396. }
  1397. static void nvme_map_cmb(struct nvme_dev *dev)
  1398. {
  1399. u64 size, offset;
  1400. resource_size_t bar_size;
  1401. struct pci_dev *pdev = to_pci_dev(dev->dev);
  1402. int bar;
  1403. if (dev->cmb_size)
  1404. return;
  1405. dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
  1406. if (!dev->cmbsz)
  1407. return;
  1408. dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
  1409. if (!use_cmb_sqes)
  1410. return;
  1411. size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
  1412. offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
  1413. bar = NVME_CMB_BIR(dev->cmbloc);
  1414. bar_size = pci_resource_len(pdev, bar);
  1415. if (offset > bar_size)
  1416. return;
  1417. /*
  1418. * Controllers may support a CMB size larger than their BAR,
  1419. * for example, due to being behind a bridge. Reduce the CMB to
  1420. * the reported size of the BAR
  1421. */
  1422. if (size > bar_size - offset)
  1423. size = bar_size - offset;
  1424. dev->cmb = ioremap_wc(pci_resource_start(pdev, bar) + offset, size);
  1425. if (!dev->cmb)
  1426. return;
  1427. dev->cmb_bus_addr = pci_bus_address(pdev, bar) + offset;
  1428. dev->cmb_size = size;
  1429. if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
  1430. &dev_attr_cmb.attr, NULL))
  1431. dev_warn(dev->ctrl.device,
  1432. "failed to add sysfs attribute for CMB\n");
  1433. }
  1434. static inline void nvme_release_cmb(struct nvme_dev *dev)
  1435. {
  1436. if (dev->cmb) {
  1437. iounmap(dev->cmb);
  1438. dev->cmb = NULL;
  1439. sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
  1440. &dev_attr_cmb.attr, NULL);
  1441. dev->cmbsz = 0;
  1442. }
  1443. }
  1444. static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
  1445. {
  1446. u64 dma_addr = dev->host_mem_descs_dma;
  1447. struct nvme_command c;
  1448. int ret;
  1449. memset(&c, 0, sizeof(c));
  1450. c.features.opcode = nvme_admin_set_features;
  1451. c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
  1452. c.features.dword11 = cpu_to_le32(bits);
  1453. c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
  1454. ilog2(dev->ctrl.page_size));
  1455. c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
  1456. c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
  1457. c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
  1458. ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
  1459. if (ret) {
  1460. dev_warn(dev->ctrl.device,
  1461. "failed to set host mem (err %d, flags %#x).\n",
  1462. ret, bits);
  1463. }
  1464. return ret;
  1465. }
  1466. static void nvme_free_host_mem(struct nvme_dev *dev)
  1467. {
  1468. int i;
  1469. for (i = 0; i < dev->nr_host_mem_descs; i++) {
  1470. struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
  1471. size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
  1472. dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
  1473. le64_to_cpu(desc->addr),
  1474. DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
  1475. }
  1476. kfree(dev->host_mem_desc_bufs);
  1477. dev->host_mem_desc_bufs = NULL;
  1478. dma_free_coherent(dev->dev,
  1479. dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
  1480. dev->host_mem_descs, dev->host_mem_descs_dma);
  1481. dev->host_mem_descs = NULL;
  1482. dev->nr_host_mem_descs = 0;
  1483. }
  1484. static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
  1485. u32 chunk_size)
  1486. {
  1487. struct nvme_host_mem_buf_desc *descs;
  1488. u32 max_entries, len;
  1489. dma_addr_t descs_dma;
  1490. int i = 0;
  1491. void **bufs;
  1492. u64 size, tmp;
  1493. tmp = (preferred + chunk_size - 1);
  1494. do_div(tmp, chunk_size);
  1495. max_entries = tmp;
  1496. if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
  1497. max_entries = dev->ctrl.hmmaxd;
  1498. descs = dma_zalloc_coherent(dev->dev, max_entries * sizeof(*descs),
  1499. &descs_dma, GFP_KERNEL);
  1500. if (!descs)
  1501. goto out;
  1502. bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
  1503. if (!bufs)
  1504. goto out_free_descs;
  1505. for (size = 0; size < preferred && i < max_entries; size += len) {
  1506. dma_addr_t dma_addr;
  1507. len = min_t(u64, chunk_size, preferred - size);
  1508. bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
  1509. DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
  1510. if (!bufs[i])
  1511. break;
  1512. descs[i].addr = cpu_to_le64(dma_addr);
  1513. descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
  1514. i++;
  1515. }
  1516. if (!size)
  1517. goto out_free_bufs;
  1518. dev->nr_host_mem_descs = i;
  1519. dev->host_mem_size = size;
  1520. dev->host_mem_descs = descs;
  1521. dev->host_mem_descs_dma = descs_dma;
  1522. dev->host_mem_desc_bufs = bufs;
  1523. return 0;
  1524. out_free_bufs:
  1525. while (--i >= 0) {
  1526. size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
  1527. dma_free_attrs(dev->dev, size, bufs[i],
  1528. le64_to_cpu(descs[i].addr),
  1529. DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
  1530. }
  1531. kfree(bufs);
  1532. out_free_descs:
  1533. dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
  1534. descs_dma);
  1535. out:
  1536. dev->host_mem_descs = NULL;
  1537. return -ENOMEM;
  1538. }
  1539. static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
  1540. {
  1541. u32 chunk_size;
  1542. /* start big and work our way down */
  1543. for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
  1544. chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
  1545. chunk_size /= 2) {
  1546. if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
  1547. if (!min || dev->host_mem_size >= min)
  1548. return 0;
  1549. nvme_free_host_mem(dev);
  1550. }
  1551. }
  1552. return -ENOMEM;
  1553. }
  1554. static int nvme_setup_host_mem(struct nvme_dev *dev)
  1555. {
  1556. u64 max = (u64)max_host_mem_size_mb * SZ_1M;
  1557. u64 preferred = (u64)dev->ctrl.hmpre * 4096;
  1558. u64 min = (u64)dev->ctrl.hmmin * 4096;
  1559. u32 enable_bits = NVME_HOST_MEM_ENABLE;
  1560. int ret;
  1561. preferred = min(preferred, max);
  1562. if (min > max) {
  1563. dev_warn(dev->ctrl.device,
  1564. "min host memory (%lld MiB) above limit (%d MiB).\n",
  1565. min >> ilog2(SZ_1M), max_host_mem_size_mb);
  1566. nvme_free_host_mem(dev);
  1567. return 0;
  1568. }
  1569. /*
  1570. * If we already have a buffer allocated check if we can reuse it.
  1571. */
  1572. if (dev->host_mem_descs) {
  1573. if (dev->host_mem_size >= min)
  1574. enable_bits |= NVME_HOST_MEM_RETURN;
  1575. else
  1576. nvme_free_host_mem(dev);
  1577. }
  1578. if (!dev->host_mem_descs) {
  1579. if (nvme_alloc_host_mem(dev, min, preferred)) {
  1580. dev_warn(dev->ctrl.device,
  1581. "failed to allocate host memory buffer.\n");
  1582. return 0; /* controller must work without HMB */
  1583. }
  1584. dev_info(dev->ctrl.device,
  1585. "allocated %lld MiB host memory buffer.\n",
  1586. dev->host_mem_size >> ilog2(SZ_1M));
  1587. }
  1588. ret = nvme_set_host_mem(dev, enable_bits);
  1589. if (ret)
  1590. nvme_free_host_mem(dev);
  1591. return ret;
  1592. }
  1593. static int nvme_setup_io_queues(struct nvme_dev *dev)
  1594. {
  1595. struct nvme_queue *adminq = &dev->queues[0];
  1596. struct pci_dev *pdev = to_pci_dev(dev->dev);
  1597. int result, nr_io_queues;
  1598. unsigned long size;
  1599. struct irq_affinity affd = {
  1600. .pre_vectors = 1
  1601. };
  1602. nr_io_queues = num_possible_cpus();
  1603. result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
  1604. if (result < 0)
  1605. return result;
  1606. if (nr_io_queues == 0)
  1607. return 0;
  1608. if (dev->cmb && (dev->cmbsz & NVME_CMBSZ_SQS)) {
  1609. result = nvme_cmb_qdepth(dev, nr_io_queues,
  1610. sizeof(struct nvme_command));
  1611. if (result > 0)
  1612. dev->q_depth = result;
  1613. else
  1614. nvme_release_cmb(dev);
  1615. }
  1616. do {
  1617. size = db_bar_size(dev, nr_io_queues);
  1618. result = nvme_remap_bar(dev, size);
  1619. if (!result)
  1620. break;
  1621. if (!--nr_io_queues)
  1622. return -ENOMEM;
  1623. } while (1);
  1624. adminq->q_db = dev->dbs;
  1625. /* Deregister the admin queue's interrupt */
  1626. pci_free_irq(pdev, 0, adminq);
  1627. /*
  1628. * If we enable msix early due to not intx, disable it again before
  1629. * setting up the full range we need.
  1630. */
  1631. pci_free_irq_vectors(pdev);
  1632. result = pci_alloc_irq_vectors_affinity(pdev, 1, nr_io_queues + 1,
  1633. PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
  1634. if (result <= 0)
  1635. return -EIO;
  1636. dev->num_vecs = result;
  1637. dev->max_qid = max(result - 1, 1);
  1638. /*
  1639. * Should investigate if there's a performance win from allocating
  1640. * more queues than interrupt vectors; it might allow the submission
  1641. * path to scale better, even if the receive path is limited by the
  1642. * number of interrupts.
  1643. */
  1644. result = queue_request_irq(adminq);
  1645. if (result) {
  1646. adminq->cq_vector = -1;
  1647. return result;
  1648. }
  1649. return nvme_create_io_queues(dev);
  1650. }
  1651. static void nvme_del_queue_end(struct request *req, blk_status_t error)
  1652. {
  1653. struct nvme_queue *nvmeq = req->end_io_data;
  1654. blk_mq_free_request(req);
  1655. complete(&nvmeq->dev->ioq_wait);
  1656. }
  1657. static void nvme_del_cq_end(struct request *req, blk_status_t error)
  1658. {
  1659. struct nvme_queue *nvmeq = req->end_io_data;
  1660. u16 start, end;
  1661. if (!error) {
  1662. unsigned long flags;
  1663. spin_lock_irqsave(&nvmeq->cq_lock, flags);
  1664. nvme_process_cq(nvmeq, &start, &end, -1);
  1665. spin_unlock_irqrestore(&nvmeq->cq_lock, flags);
  1666. nvme_complete_cqes(nvmeq, start, end);
  1667. }
  1668. nvme_del_queue_end(req, error);
  1669. }
  1670. static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
  1671. {
  1672. struct request_queue *q = nvmeq->dev->ctrl.admin_q;
  1673. struct request *req;
  1674. struct nvme_command cmd;
  1675. memset(&cmd, 0, sizeof(cmd));
  1676. cmd.delete_queue.opcode = opcode;
  1677. cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
  1678. req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
  1679. if (IS_ERR(req))
  1680. return PTR_ERR(req);
  1681. req->timeout = ADMIN_TIMEOUT;
  1682. req->end_io_data = nvmeq;
  1683. blk_execute_rq_nowait(q, NULL, req, false,
  1684. opcode == nvme_admin_delete_cq ?
  1685. nvme_del_cq_end : nvme_del_queue_end);
  1686. return 0;
  1687. }
  1688. static void nvme_disable_io_queues(struct nvme_dev *dev)
  1689. {
  1690. int pass, queues = dev->online_queues - 1;
  1691. unsigned long timeout;
  1692. u8 opcode = nvme_admin_delete_sq;
  1693. for (pass = 0; pass < 2; pass++) {
  1694. int sent = 0, i = queues;
  1695. reinit_completion(&dev->ioq_wait);
  1696. retry:
  1697. timeout = ADMIN_TIMEOUT;
  1698. for (; i > 0; i--, sent++)
  1699. if (nvme_delete_queue(&dev->queues[i], opcode))
  1700. break;
  1701. while (sent--) {
  1702. timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
  1703. if (timeout == 0)
  1704. return;
  1705. if (i)
  1706. goto retry;
  1707. }
  1708. opcode = nvme_admin_delete_cq;
  1709. }
  1710. }
  1711. /*
  1712. * return error value only when tagset allocation failed
  1713. */
  1714. static int nvme_dev_add(struct nvme_dev *dev)
  1715. {
  1716. int ret;
  1717. if (!dev->ctrl.tagset) {
  1718. dev->tagset.ops = &nvme_mq_ops;
  1719. dev->tagset.nr_hw_queues = dev->online_queues - 1;
  1720. dev->tagset.timeout = NVME_IO_TIMEOUT;
  1721. dev->tagset.numa_node = dev_to_node(dev->dev);
  1722. dev->tagset.queue_depth =
  1723. min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
  1724. dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false);
  1725. if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) {
  1726. dev->tagset.cmd_size = max(dev->tagset.cmd_size,
  1727. nvme_pci_cmd_size(dev, true));
  1728. }
  1729. dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
  1730. dev->tagset.driver_data = dev;
  1731. ret = blk_mq_alloc_tag_set(&dev->tagset);
  1732. if (ret) {
  1733. dev_warn(dev->ctrl.device,
  1734. "IO queues tagset allocation failed %d\n", ret);
  1735. return ret;
  1736. }
  1737. dev->ctrl.tagset = &dev->tagset;
  1738. nvme_dbbuf_set(dev);
  1739. } else {
  1740. blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
  1741. /* Free previously allocated queues that are no longer usable */
  1742. nvme_free_queues(dev, dev->online_queues);
  1743. }
  1744. return 0;
  1745. }
  1746. static int nvme_pci_enable(struct nvme_dev *dev)
  1747. {
  1748. int result = -ENOMEM;
  1749. struct pci_dev *pdev = to_pci_dev(dev->dev);
  1750. if (pci_enable_device_mem(pdev))
  1751. return result;
  1752. pci_set_master(pdev);
  1753. if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
  1754. dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
  1755. goto disable;
  1756. if (readl(dev->bar + NVME_REG_CSTS) == -1) {
  1757. result = -ENODEV;
  1758. goto disable;
  1759. }
  1760. /*
  1761. * Some devices and/or platforms don't advertise or work with INTx
  1762. * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
  1763. * adjust this later.
  1764. */
  1765. result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
  1766. if (result < 0)
  1767. return result;
  1768. dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
  1769. dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
  1770. io_queue_depth);
  1771. dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
  1772. dev->dbs = dev->bar + 4096;
  1773. /*
  1774. * Temporary fix for the Apple controller found in the MacBook8,1 and
  1775. * some MacBook7,1 to avoid controller resets and data loss.
  1776. */
  1777. if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
  1778. dev->q_depth = 2;
  1779. dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
  1780. "set queue depth=%u to work around controller resets\n",
  1781. dev->q_depth);
  1782. } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
  1783. (pdev->device == 0xa821 || pdev->device == 0xa822) &&
  1784. NVME_CAP_MQES(dev->ctrl.cap) == 0) {
  1785. dev->q_depth = 64;
  1786. dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
  1787. "set queue depth=%u\n", dev->q_depth);
  1788. }
  1789. nvme_map_cmb(dev);
  1790. pci_enable_pcie_error_reporting(pdev);
  1791. pci_save_state(pdev);
  1792. return 0;
  1793. disable:
  1794. pci_disable_device(pdev);
  1795. return result;
  1796. }
  1797. static void nvme_dev_unmap(struct nvme_dev *dev)
  1798. {
  1799. if (dev->bar)
  1800. iounmap(dev->bar);
  1801. pci_release_mem_regions(to_pci_dev(dev->dev));
  1802. }
  1803. static void nvme_pci_disable(struct nvme_dev *dev)
  1804. {
  1805. struct pci_dev *pdev = to_pci_dev(dev->dev);
  1806. pci_free_irq_vectors(pdev);
  1807. if (pci_is_enabled(pdev)) {
  1808. pci_disable_pcie_error_reporting(pdev);
  1809. pci_disable_device(pdev);
  1810. }
  1811. }
  1812. static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
  1813. {
  1814. int i;
  1815. bool dead = true;
  1816. struct pci_dev *pdev = to_pci_dev(dev->dev);
  1817. mutex_lock(&dev->shutdown_lock);
  1818. if (pci_is_enabled(pdev)) {
  1819. u32 csts = readl(dev->bar + NVME_REG_CSTS);
  1820. if (dev->ctrl.state == NVME_CTRL_LIVE ||
  1821. dev->ctrl.state == NVME_CTRL_RESETTING)
  1822. nvme_start_freeze(&dev->ctrl);
  1823. dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
  1824. pdev->error_state != pci_channel_io_normal);
  1825. }
  1826. /*
  1827. * Give the controller a chance to complete all entered requests if
  1828. * doing a safe shutdown.
  1829. */
  1830. if (!dead) {
  1831. if (shutdown)
  1832. nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
  1833. }
  1834. nvme_stop_queues(&dev->ctrl);
  1835. if (!dead && dev->ctrl.queue_count > 0) {
  1836. nvme_disable_io_queues(dev);
  1837. nvme_disable_admin_queue(dev, shutdown);
  1838. }
  1839. for (i = dev->ctrl.queue_count - 1; i >= 0; i--)
  1840. nvme_suspend_queue(&dev->queues[i]);
  1841. nvme_pci_disable(dev);
  1842. blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
  1843. blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
  1844. /*
  1845. * The driver will not be starting up queues again if shutting down so
  1846. * must flush all entered requests to their failed completion to avoid
  1847. * deadlocking blk-mq hot-cpu notifier.
  1848. */
  1849. if (shutdown) {
  1850. nvme_start_queues(&dev->ctrl);
  1851. if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
  1852. blk_mq_unquiesce_queue(dev->ctrl.admin_q);
  1853. }
  1854. mutex_unlock(&dev->shutdown_lock);
  1855. }
  1856. static int nvme_setup_prp_pools(struct nvme_dev *dev)
  1857. {
  1858. dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
  1859. PAGE_SIZE, PAGE_SIZE, 0);
  1860. if (!dev->prp_page_pool)
  1861. return -ENOMEM;
  1862. /* Optimisation for I/Os between 4k and 128k */
  1863. dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
  1864. 256, 256, 0);
  1865. if (!dev->prp_small_pool) {
  1866. dma_pool_destroy(dev->prp_page_pool);
  1867. return -ENOMEM;
  1868. }
  1869. return 0;
  1870. }
  1871. static void nvme_release_prp_pools(struct nvme_dev *dev)
  1872. {
  1873. dma_pool_destroy(dev->prp_page_pool);
  1874. dma_pool_destroy(dev->prp_small_pool);
  1875. }
  1876. static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
  1877. {
  1878. struct nvme_dev *dev = to_nvme_dev(ctrl);
  1879. nvme_dbbuf_dma_free(dev);
  1880. put_device(dev->dev);
  1881. if (dev->tagset.tags)
  1882. blk_mq_free_tag_set(&dev->tagset);
  1883. if (dev->ctrl.admin_q)
  1884. blk_put_queue(dev->ctrl.admin_q);
  1885. kfree(dev->queues);
  1886. free_opal_dev(dev->ctrl.opal_dev);
  1887. mempool_destroy(dev->iod_mempool);
  1888. kfree(dev);
  1889. }
  1890. static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
  1891. {
  1892. dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
  1893. nvme_get_ctrl(&dev->ctrl);
  1894. nvme_dev_disable(dev, false);
  1895. nvme_kill_queues(&dev->ctrl);
  1896. if (!queue_work(nvme_wq, &dev->remove_work))
  1897. nvme_put_ctrl(&dev->ctrl);
  1898. }
  1899. static void nvme_reset_work(struct work_struct *work)
  1900. {
  1901. struct nvme_dev *dev =
  1902. container_of(work, struct nvme_dev, ctrl.reset_work);
  1903. bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
  1904. int result;
  1905. enum nvme_ctrl_state new_state = NVME_CTRL_LIVE;
  1906. if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) {
  1907. result = -ENODEV;
  1908. goto out;
  1909. }
  1910. /*
  1911. * If we're called to reset a live controller first shut it down before
  1912. * moving on.
  1913. */
  1914. if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
  1915. nvme_dev_disable(dev, false);
  1916. mutex_lock(&dev->shutdown_lock);
  1917. result = nvme_pci_enable(dev);
  1918. if (result)
  1919. goto out_unlock;
  1920. result = nvme_pci_configure_admin_queue(dev);
  1921. if (result)
  1922. goto out_unlock;
  1923. result = nvme_alloc_admin_tags(dev);
  1924. if (result)
  1925. goto out_unlock;
  1926. /*
  1927. * Limit the max command size to prevent iod->sg allocations going
  1928. * over a single page.
  1929. */
  1930. dev->ctrl.max_hw_sectors = NVME_MAX_KB_SZ << 1;
  1931. dev->ctrl.max_segments = NVME_MAX_SEGS;
  1932. mutex_unlock(&dev->shutdown_lock);
  1933. /*
  1934. * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
  1935. * initializing procedure here.
  1936. */
  1937. if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
  1938. dev_warn(dev->ctrl.device,
  1939. "failed to mark controller CONNECTING\n");
  1940. result = -EBUSY;
  1941. goto out;
  1942. }
  1943. result = nvme_init_identify(&dev->ctrl);
  1944. if (result)
  1945. goto out;
  1946. if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
  1947. if (!dev->ctrl.opal_dev)
  1948. dev->ctrl.opal_dev =
  1949. init_opal_dev(&dev->ctrl, &nvme_sec_submit);
  1950. else if (was_suspend)
  1951. opal_unlock_from_suspend(dev->ctrl.opal_dev);
  1952. } else {
  1953. free_opal_dev(dev->ctrl.opal_dev);
  1954. dev->ctrl.opal_dev = NULL;
  1955. }
  1956. if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
  1957. result = nvme_dbbuf_dma_alloc(dev);
  1958. if (result)
  1959. dev_warn(dev->dev,
  1960. "unable to allocate dma for dbbuf\n");
  1961. }
  1962. if (dev->ctrl.hmpre) {
  1963. result = nvme_setup_host_mem(dev);
  1964. if (result < 0)
  1965. goto out;
  1966. }
  1967. result = nvme_setup_io_queues(dev);
  1968. if (result)
  1969. goto out;
  1970. /*
  1971. * Keep the controller around but remove all namespaces if we don't have
  1972. * any working I/O queue.
  1973. */
  1974. if (dev->online_queues < 2) {
  1975. dev_warn(dev->ctrl.device, "IO queues not created\n");
  1976. nvme_kill_queues(&dev->ctrl);
  1977. nvme_remove_namespaces(&dev->ctrl);
  1978. new_state = NVME_CTRL_ADMIN_ONLY;
  1979. } else {
  1980. nvme_start_queues(&dev->ctrl);
  1981. nvme_wait_freeze(&dev->ctrl);
  1982. /* hit this only when allocate tagset fails */
  1983. if (nvme_dev_add(dev))
  1984. new_state = NVME_CTRL_ADMIN_ONLY;
  1985. nvme_unfreeze(&dev->ctrl);
  1986. }
  1987. /*
  1988. * If only admin queue live, keep it to do further investigation or
  1989. * recovery.
  1990. */
  1991. if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) {
  1992. dev_warn(dev->ctrl.device,
  1993. "failed to mark controller state %d\n", new_state);
  1994. result = -ENODEV;
  1995. goto out;
  1996. }
  1997. nvme_start_ctrl(&dev->ctrl);
  1998. return;
  1999. out_unlock:
  2000. mutex_unlock(&dev->shutdown_lock);
  2001. out:
  2002. nvme_remove_dead_ctrl(dev, result);
  2003. }
  2004. static void nvme_remove_dead_ctrl_work(struct work_struct *work)
  2005. {
  2006. struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
  2007. struct pci_dev *pdev = to_pci_dev(dev->dev);
  2008. if (pci_get_drvdata(pdev))
  2009. device_release_driver(&pdev->dev);
  2010. nvme_put_ctrl(&dev->ctrl);
  2011. }
  2012. static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
  2013. {
  2014. *val = readl(to_nvme_dev(ctrl)->bar + off);
  2015. return 0;
  2016. }
  2017. static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
  2018. {
  2019. writel(val, to_nvme_dev(ctrl)->bar + off);
  2020. return 0;
  2021. }
  2022. static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
  2023. {
  2024. *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
  2025. return 0;
  2026. }
  2027. static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
  2028. {
  2029. struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
  2030. return snprintf(buf, size, "%s", dev_name(&pdev->dev));
  2031. }
  2032. static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
  2033. .name = "pcie",
  2034. .module = THIS_MODULE,
  2035. .flags = NVME_F_METADATA_SUPPORTED,
  2036. .reg_read32 = nvme_pci_reg_read32,
  2037. .reg_write32 = nvme_pci_reg_write32,
  2038. .reg_read64 = nvme_pci_reg_read64,
  2039. .free_ctrl = nvme_pci_free_ctrl,
  2040. .submit_async_event = nvme_pci_submit_async_event,
  2041. .get_address = nvme_pci_get_address,
  2042. };
  2043. static int nvme_dev_map(struct nvme_dev *dev)
  2044. {
  2045. struct pci_dev *pdev = to_pci_dev(dev->dev);
  2046. if (pci_request_mem_regions(pdev, "nvme"))
  2047. return -ENODEV;
  2048. if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
  2049. goto release;
  2050. return 0;
  2051. release:
  2052. pci_release_mem_regions(pdev);
  2053. return -ENODEV;
  2054. }
  2055. static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
  2056. {
  2057. if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
  2058. /*
  2059. * Several Samsung devices seem to drop off the PCIe bus
  2060. * randomly when APST is on and uses the deepest sleep state.
  2061. * This has been observed on a Samsung "SM951 NVMe SAMSUNG
  2062. * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
  2063. * 950 PRO 256GB", but it seems to be restricted to two Dell
  2064. * laptops.
  2065. */
  2066. if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
  2067. (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
  2068. dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
  2069. return NVME_QUIRK_NO_DEEPEST_PS;
  2070. } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
  2071. /*
  2072. * Samsung SSD 960 EVO drops off the PCIe bus after system
  2073. * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
  2074. * within few minutes after bootup on a Coffee Lake board -
  2075. * ASUS PRIME Z370-A
  2076. */
  2077. if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
  2078. (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
  2079. dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
  2080. return NVME_QUIRK_NO_APST;
  2081. }
  2082. return 0;
  2083. }
  2084. static void nvme_async_probe(void *data, async_cookie_t cookie)
  2085. {
  2086. struct nvme_dev *dev = data;
  2087. flush_work(&dev->ctrl.reset_work);
  2088. flush_work(&dev->ctrl.scan_work);
  2089. nvme_put_ctrl(&dev->ctrl);
  2090. }
  2091. static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  2092. {
  2093. int node, result = -ENOMEM;
  2094. struct nvme_dev *dev;
  2095. unsigned long quirks = id->driver_data;
  2096. size_t alloc_size;
  2097. node = dev_to_node(&pdev->dev);
  2098. if (node == NUMA_NO_NODE)
  2099. set_dev_node(&pdev->dev, first_memory_node);
  2100. dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
  2101. if (!dev)
  2102. return -ENOMEM;
  2103. dev->queues = kcalloc_node(num_possible_cpus() + 1,
  2104. sizeof(struct nvme_queue), GFP_KERNEL, node);
  2105. if (!dev->queues)
  2106. goto free;
  2107. dev->dev = get_device(&pdev->dev);
  2108. pci_set_drvdata(pdev, dev);
  2109. result = nvme_dev_map(dev);
  2110. if (result)
  2111. goto put_pci;
  2112. INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
  2113. INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
  2114. mutex_init(&dev->shutdown_lock);
  2115. init_completion(&dev->ioq_wait);
  2116. result = nvme_setup_prp_pools(dev);
  2117. if (result)
  2118. goto unmap;
  2119. quirks |= check_vendor_combination_bug(pdev);
  2120. /*
  2121. * Double check that our mempool alloc size will cover the biggest
  2122. * command we support.
  2123. */
  2124. alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ,
  2125. NVME_MAX_SEGS, true);
  2126. WARN_ON_ONCE(alloc_size > PAGE_SIZE);
  2127. dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
  2128. mempool_kfree,
  2129. (void *) alloc_size,
  2130. GFP_KERNEL, node);
  2131. if (!dev->iod_mempool) {
  2132. result = -ENOMEM;
  2133. goto release_pools;
  2134. }
  2135. result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
  2136. quirks);
  2137. if (result)
  2138. goto release_mempool;
  2139. dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
  2140. nvme_reset_ctrl(&dev->ctrl);
  2141. nvme_get_ctrl(&dev->ctrl);
  2142. async_schedule(nvme_async_probe, dev);
  2143. return 0;
  2144. release_mempool:
  2145. mempool_destroy(dev->iod_mempool);
  2146. release_pools:
  2147. nvme_release_prp_pools(dev);
  2148. unmap:
  2149. nvme_dev_unmap(dev);
  2150. put_pci:
  2151. put_device(dev->dev);
  2152. free:
  2153. kfree(dev->queues);
  2154. kfree(dev);
  2155. return result;
  2156. }
  2157. static void nvme_reset_prepare(struct pci_dev *pdev)
  2158. {
  2159. struct nvme_dev *dev = pci_get_drvdata(pdev);
  2160. nvme_dev_disable(dev, false);
  2161. }
  2162. static void nvme_reset_done(struct pci_dev *pdev)
  2163. {
  2164. struct nvme_dev *dev = pci_get_drvdata(pdev);
  2165. nvme_reset_ctrl_sync(&dev->ctrl);
  2166. }
  2167. static void nvme_shutdown(struct pci_dev *pdev)
  2168. {
  2169. struct nvme_dev *dev = pci_get_drvdata(pdev);
  2170. nvme_dev_disable(dev, true);
  2171. }
  2172. /*
  2173. * The driver's remove may be called on a device in a partially initialized
  2174. * state. This function must not have any dependencies on the device state in
  2175. * order to proceed.
  2176. */
  2177. static void nvme_remove(struct pci_dev *pdev)
  2178. {
  2179. struct nvme_dev *dev = pci_get_drvdata(pdev);
  2180. nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
  2181. pci_set_drvdata(pdev, NULL);
  2182. if (!pci_device_is_present(pdev)) {
  2183. nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
  2184. nvme_dev_disable(dev, true);
  2185. nvme_dev_remove_admin(dev);
  2186. }
  2187. flush_work(&dev->ctrl.reset_work);
  2188. nvme_stop_ctrl(&dev->ctrl);
  2189. nvme_remove_namespaces(&dev->ctrl);
  2190. nvme_dev_disable(dev, true);
  2191. nvme_release_cmb(dev);
  2192. nvme_free_host_mem(dev);
  2193. nvme_dev_remove_admin(dev);
  2194. nvme_free_queues(dev, 0);
  2195. nvme_uninit_ctrl(&dev->ctrl);
  2196. nvme_release_prp_pools(dev);
  2197. nvme_dev_unmap(dev);
  2198. nvme_put_ctrl(&dev->ctrl);
  2199. }
  2200. #ifdef CONFIG_PM_SLEEP
  2201. static int nvme_suspend(struct device *dev)
  2202. {
  2203. struct pci_dev *pdev = to_pci_dev(dev);
  2204. struct nvme_dev *ndev = pci_get_drvdata(pdev);
  2205. nvme_dev_disable(ndev, true);
  2206. return 0;
  2207. }
  2208. static int nvme_resume(struct device *dev)
  2209. {
  2210. struct pci_dev *pdev = to_pci_dev(dev);
  2211. struct nvme_dev *ndev = pci_get_drvdata(pdev);
  2212. nvme_reset_ctrl(&ndev->ctrl);
  2213. return 0;
  2214. }
  2215. #endif
  2216. static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
  2217. static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
  2218. pci_channel_state_t state)
  2219. {
  2220. struct nvme_dev *dev = pci_get_drvdata(pdev);
  2221. /*
  2222. * A frozen channel requires a reset. When detected, this method will
  2223. * shutdown the controller to quiesce. The controller will be restarted
  2224. * after the slot reset through driver's slot_reset callback.
  2225. */
  2226. switch (state) {
  2227. case pci_channel_io_normal:
  2228. return PCI_ERS_RESULT_CAN_RECOVER;
  2229. case pci_channel_io_frozen:
  2230. dev_warn(dev->ctrl.device,
  2231. "frozen state error detected, reset controller\n");
  2232. nvme_dev_disable(dev, false);
  2233. return PCI_ERS_RESULT_NEED_RESET;
  2234. case pci_channel_io_perm_failure:
  2235. dev_warn(dev->ctrl.device,
  2236. "failure state error detected, request disconnect\n");
  2237. return PCI_ERS_RESULT_DISCONNECT;
  2238. }
  2239. return PCI_ERS_RESULT_NEED_RESET;
  2240. }
  2241. static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
  2242. {
  2243. struct nvme_dev *dev = pci_get_drvdata(pdev);
  2244. dev_info(dev->ctrl.device, "restart after slot reset\n");
  2245. pci_restore_state(pdev);
  2246. nvme_reset_ctrl(&dev->ctrl);
  2247. return PCI_ERS_RESULT_RECOVERED;
  2248. }
  2249. static void nvme_error_resume(struct pci_dev *pdev)
  2250. {
  2251. struct nvme_dev *dev = pci_get_drvdata(pdev);
  2252. flush_work(&dev->ctrl.reset_work);
  2253. pci_cleanup_aer_uncorrect_error_status(pdev);
  2254. }
  2255. static const struct pci_error_handlers nvme_err_handler = {
  2256. .error_detected = nvme_error_detected,
  2257. .slot_reset = nvme_slot_reset,
  2258. .resume = nvme_error_resume,
  2259. .reset_prepare = nvme_reset_prepare,
  2260. .reset_done = nvme_reset_done,
  2261. };
  2262. static const struct pci_device_id nvme_id_table[] = {
  2263. { PCI_VDEVICE(INTEL, 0x0953),
  2264. .driver_data = NVME_QUIRK_STRIPE_SIZE |
  2265. NVME_QUIRK_DEALLOCATE_ZEROES, },
  2266. { PCI_VDEVICE(INTEL, 0x0a53),
  2267. .driver_data = NVME_QUIRK_STRIPE_SIZE |
  2268. NVME_QUIRK_DEALLOCATE_ZEROES, },
  2269. { PCI_VDEVICE(INTEL, 0x0a54),
  2270. .driver_data = NVME_QUIRK_STRIPE_SIZE |
  2271. NVME_QUIRK_DEALLOCATE_ZEROES, },
  2272. { PCI_VDEVICE(INTEL, 0x0a55),
  2273. .driver_data = NVME_QUIRK_STRIPE_SIZE |
  2274. NVME_QUIRK_DEALLOCATE_ZEROES, },
  2275. { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
  2276. .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
  2277. NVME_QUIRK_MEDIUM_PRIO_SQ },
  2278. { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
  2279. .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
  2280. { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
  2281. .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
  2282. { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
  2283. .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
  2284. { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
  2285. .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
  2286. { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
  2287. .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
  2288. { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
  2289. .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
  2290. { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
  2291. .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
  2292. { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
  2293. .driver_data = NVME_QUIRK_LIGHTNVM, },
  2294. { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
  2295. .driver_data = NVME_QUIRK_LIGHTNVM, },
  2296. { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
  2297. .driver_data = NVME_QUIRK_LIGHTNVM, },
  2298. { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
  2299. { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */
  2300. .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
  2301. { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
  2302. { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
  2303. { 0, }
  2304. };
  2305. MODULE_DEVICE_TABLE(pci, nvme_id_table);
  2306. static struct pci_driver nvme_driver = {
  2307. .name = "nvme",
  2308. .id_table = nvme_id_table,
  2309. .probe = nvme_probe,
  2310. .remove = nvme_remove,
  2311. .shutdown = nvme_shutdown,
  2312. .driver = {
  2313. .pm = &nvme_dev_pm_ops,
  2314. },
  2315. .sriov_configure = pci_sriov_configure_simple,
  2316. .err_handler = &nvme_err_handler,
  2317. };
  2318. static int __init nvme_init(void)
  2319. {
  2320. return pci_register_driver(&nvme_driver);
  2321. }
  2322. static void __exit nvme_exit(void)
  2323. {
  2324. pci_unregister_driver(&nvme_driver);
  2325. flush_workqueue(nvme_wq);
  2326. _nvme_check_size();
  2327. }
  2328. MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
  2329. MODULE_LICENSE("GPL");
  2330. MODULE_VERSION("1.0");
  2331. module_init(nvme_init);
  2332. module_exit(nvme_exit);