pci-epc-core.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /**
  3. * PCI Endpoint *Controller* (EPC) library
  4. *
  5. * Copyright (C) 2017 Texas Instruments
  6. * Author: Kishon Vijay Abraham I <kishon@ti.com>
  7. */
  8. #include <linux/device.h>
  9. #include <linux/slab.h>
  10. #include <linux/module.h>
  11. #include <linux/of_device.h>
  12. #include <linux/pci-epc.h>
  13. #include <linux/pci-epf.h>
  14. #include <linux/pci-ep-cfs.h>
  15. static struct class *pci_epc_class;
  16. static void devm_pci_epc_release(struct device *dev, void *res)
  17. {
  18. struct pci_epc *epc = *(struct pci_epc **)res;
  19. pci_epc_destroy(epc);
  20. }
  21. static int devm_pci_epc_match(struct device *dev, void *res, void *match_data)
  22. {
  23. struct pci_epc **epc = res;
  24. return *epc == match_data;
  25. }
  26. /**
  27. * pci_epc_put() - release the PCI endpoint controller
  28. * @epc: epc returned by pci_epc_get()
  29. *
  30. * release the refcount the caller obtained by invoking pci_epc_get()
  31. */
  32. void pci_epc_put(struct pci_epc *epc)
  33. {
  34. if (!epc || IS_ERR(epc))
  35. return;
  36. module_put(epc->ops->owner);
  37. put_device(&epc->dev);
  38. }
  39. EXPORT_SYMBOL_GPL(pci_epc_put);
  40. /**
  41. * pci_epc_get() - get the PCI endpoint controller
  42. * @epc_name: device name of the endpoint controller
  43. *
  44. * Invoke to get struct pci_epc * corresponding to the device name of the
  45. * endpoint controller
  46. */
  47. struct pci_epc *pci_epc_get(const char *epc_name)
  48. {
  49. int ret = -EINVAL;
  50. struct pci_epc *epc;
  51. struct device *dev;
  52. struct class_dev_iter iter;
  53. class_dev_iter_init(&iter, pci_epc_class, NULL, NULL);
  54. while ((dev = class_dev_iter_next(&iter))) {
  55. if (strcmp(epc_name, dev_name(dev)))
  56. continue;
  57. epc = to_pci_epc(dev);
  58. if (!try_module_get(epc->ops->owner)) {
  59. ret = -EINVAL;
  60. goto err;
  61. }
  62. class_dev_iter_exit(&iter);
  63. get_device(&epc->dev);
  64. return epc;
  65. }
  66. err:
  67. class_dev_iter_exit(&iter);
  68. return ERR_PTR(ret);
  69. }
  70. EXPORT_SYMBOL_GPL(pci_epc_get);
  71. /**
  72. * pci_epc_stop() - stop the PCI link
  73. * @epc: the link of the EPC device that has to be stopped
  74. *
  75. * Invoke to stop the PCI link
  76. */
  77. void pci_epc_stop(struct pci_epc *epc)
  78. {
  79. unsigned long flags;
  80. if (IS_ERR(epc) || !epc->ops->stop)
  81. return;
  82. spin_lock_irqsave(&epc->lock, flags);
  83. epc->ops->stop(epc);
  84. spin_unlock_irqrestore(&epc->lock, flags);
  85. }
  86. EXPORT_SYMBOL_GPL(pci_epc_stop);
  87. /**
  88. * pci_epc_start() - start the PCI link
  89. * @epc: the link of *this* EPC device has to be started
  90. *
  91. * Invoke to start the PCI link
  92. */
  93. int pci_epc_start(struct pci_epc *epc)
  94. {
  95. int ret;
  96. unsigned long flags;
  97. if (IS_ERR(epc))
  98. return -EINVAL;
  99. if (!epc->ops->start)
  100. return 0;
  101. spin_lock_irqsave(&epc->lock, flags);
  102. ret = epc->ops->start(epc);
  103. spin_unlock_irqrestore(&epc->lock, flags);
  104. return ret;
  105. }
  106. EXPORT_SYMBOL_GPL(pci_epc_start);
  107. /**
  108. * pci_epc_raise_irq() - interrupt the host system
  109. * @epc: the EPC device which has to interrupt the host
  110. * @func_no: the endpoint function number in the EPC device
  111. * @type: specify the type of interrupt; legacy, MSI or MSI-X
  112. * @interrupt_num: the MSI or MSI-X interrupt number
  113. *
  114. * Invoke to raise an legacy, MSI or MSI-X interrupt
  115. */
  116. int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no,
  117. enum pci_epc_irq_type type, u16 interrupt_num)
  118. {
  119. int ret;
  120. unsigned long flags;
  121. if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
  122. return -EINVAL;
  123. if (!epc->ops->raise_irq)
  124. return 0;
  125. spin_lock_irqsave(&epc->lock, flags);
  126. ret = epc->ops->raise_irq(epc, func_no, type, interrupt_num);
  127. spin_unlock_irqrestore(&epc->lock, flags);
  128. return ret;
  129. }
  130. EXPORT_SYMBOL_GPL(pci_epc_raise_irq);
  131. /**
  132. * pci_epc_get_msi() - get the number of MSI interrupt numbers allocated
  133. * @epc: the EPC device to which MSI interrupts was requested
  134. * @func_no: the endpoint function number in the EPC device
  135. *
  136. * Invoke to get the number of MSI interrupts allocated by the RC
  137. */
  138. int pci_epc_get_msi(struct pci_epc *epc, u8 func_no)
  139. {
  140. int interrupt;
  141. unsigned long flags;
  142. if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
  143. return 0;
  144. if (!epc->ops->get_msi)
  145. return 0;
  146. spin_lock_irqsave(&epc->lock, flags);
  147. interrupt = epc->ops->get_msi(epc, func_no);
  148. spin_unlock_irqrestore(&epc->lock, flags);
  149. if (interrupt < 0)
  150. return 0;
  151. interrupt = 1 << interrupt;
  152. return interrupt;
  153. }
  154. EXPORT_SYMBOL_GPL(pci_epc_get_msi);
  155. /**
  156. * pci_epc_set_msi() - set the number of MSI interrupt numbers required
  157. * @epc: the EPC device on which MSI has to be configured
  158. * @func_no: the endpoint function number in the EPC device
  159. * @interrupts: number of MSI interrupts required by the EPF
  160. *
  161. * Invoke to set the required number of MSI interrupts.
  162. */
  163. int pci_epc_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts)
  164. {
  165. int ret;
  166. u8 encode_int;
  167. unsigned long flags;
  168. if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions ||
  169. interrupts > 32)
  170. return -EINVAL;
  171. if (!epc->ops->set_msi)
  172. return 0;
  173. encode_int = order_base_2(interrupts);
  174. spin_lock_irqsave(&epc->lock, flags);
  175. ret = epc->ops->set_msi(epc, func_no, encode_int);
  176. spin_unlock_irqrestore(&epc->lock, flags);
  177. return ret;
  178. }
  179. EXPORT_SYMBOL_GPL(pci_epc_set_msi);
  180. /**
  181. * pci_epc_get_msix() - get the number of MSI-X interrupt numbers allocated
  182. * @epc: the EPC device to which MSI-X interrupts was requested
  183. * @func_no: the endpoint function number in the EPC device
  184. *
  185. * Invoke to get the number of MSI-X interrupts allocated by the RC
  186. */
  187. int pci_epc_get_msix(struct pci_epc *epc, u8 func_no)
  188. {
  189. int interrupt;
  190. unsigned long flags;
  191. if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
  192. return 0;
  193. if (!epc->ops->get_msix)
  194. return 0;
  195. spin_lock_irqsave(&epc->lock, flags);
  196. interrupt = epc->ops->get_msix(epc, func_no);
  197. spin_unlock_irqrestore(&epc->lock, flags);
  198. if (interrupt < 0)
  199. return 0;
  200. return interrupt + 1;
  201. }
  202. EXPORT_SYMBOL_GPL(pci_epc_get_msix);
  203. /**
  204. * pci_epc_set_msix() - set the number of MSI-X interrupt numbers required
  205. * @epc: the EPC device on which MSI-X has to be configured
  206. * @func_no: the endpoint function number in the EPC device
  207. * @interrupts: number of MSI-X interrupts required by the EPF
  208. *
  209. * Invoke to set the required number of MSI-X interrupts.
  210. */
  211. int pci_epc_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts)
  212. {
  213. int ret;
  214. unsigned long flags;
  215. if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions ||
  216. interrupts < 1 || interrupts > 2048)
  217. return -EINVAL;
  218. if (!epc->ops->set_msix)
  219. return 0;
  220. spin_lock_irqsave(&epc->lock, flags);
  221. ret = epc->ops->set_msix(epc, func_no, interrupts - 1);
  222. spin_unlock_irqrestore(&epc->lock, flags);
  223. return ret;
  224. }
  225. EXPORT_SYMBOL_GPL(pci_epc_set_msix);
  226. /**
  227. * pci_epc_unmap_addr() - unmap CPU address from PCI address
  228. * @epc: the EPC device on which address is allocated
  229. * @func_no: the endpoint function number in the EPC device
  230. * @phys_addr: physical address of the local system
  231. *
  232. * Invoke to unmap the CPU address from PCI address.
  233. */
  234. void pci_epc_unmap_addr(struct pci_epc *epc, u8 func_no,
  235. phys_addr_t phys_addr)
  236. {
  237. unsigned long flags;
  238. if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
  239. return;
  240. if (!epc->ops->unmap_addr)
  241. return;
  242. spin_lock_irqsave(&epc->lock, flags);
  243. epc->ops->unmap_addr(epc, func_no, phys_addr);
  244. spin_unlock_irqrestore(&epc->lock, flags);
  245. }
  246. EXPORT_SYMBOL_GPL(pci_epc_unmap_addr);
  247. /**
  248. * pci_epc_map_addr() - map CPU address to PCI address
  249. * @epc: the EPC device on which address is allocated
  250. * @func_no: the endpoint function number in the EPC device
  251. * @phys_addr: physical address of the local system
  252. * @pci_addr: PCI address to which the physical address should be mapped
  253. * @size: the size of the allocation
  254. *
  255. * Invoke to map CPU address with PCI address.
  256. */
  257. int pci_epc_map_addr(struct pci_epc *epc, u8 func_no,
  258. phys_addr_t phys_addr, u64 pci_addr, size_t size)
  259. {
  260. int ret;
  261. unsigned long flags;
  262. if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
  263. return -EINVAL;
  264. if (!epc->ops->map_addr)
  265. return 0;
  266. spin_lock_irqsave(&epc->lock, flags);
  267. ret = epc->ops->map_addr(epc, func_no, phys_addr, pci_addr, size);
  268. spin_unlock_irqrestore(&epc->lock, flags);
  269. return ret;
  270. }
  271. EXPORT_SYMBOL_GPL(pci_epc_map_addr);
  272. /**
  273. * pci_epc_clear_bar() - reset the BAR
  274. * @epc: the EPC device for which the BAR has to be cleared
  275. * @func_no: the endpoint function number in the EPC device
  276. * @epf_bar: the struct epf_bar that contains the BAR information
  277. *
  278. * Invoke to reset the BAR of the endpoint device.
  279. */
  280. void pci_epc_clear_bar(struct pci_epc *epc, u8 func_no,
  281. struct pci_epf_bar *epf_bar)
  282. {
  283. unsigned long flags;
  284. if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions ||
  285. (epf_bar->barno == BAR_5 &&
  286. epf_bar->flags & PCI_BASE_ADDRESS_MEM_TYPE_64))
  287. return;
  288. if (!epc->ops->clear_bar)
  289. return;
  290. spin_lock_irqsave(&epc->lock, flags);
  291. epc->ops->clear_bar(epc, func_no, epf_bar);
  292. spin_unlock_irqrestore(&epc->lock, flags);
  293. }
  294. EXPORT_SYMBOL_GPL(pci_epc_clear_bar);
  295. /**
  296. * pci_epc_set_bar() - configure BAR in order for host to assign PCI addr space
  297. * @epc: the EPC device on which BAR has to be configured
  298. * @func_no: the endpoint function number in the EPC device
  299. * @epf_bar: the struct epf_bar that contains the BAR information
  300. *
  301. * Invoke to configure the BAR of the endpoint device.
  302. */
  303. int pci_epc_set_bar(struct pci_epc *epc, u8 func_no,
  304. struct pci_epf_bar *epf_bar)
  305. {
  306. int ret;
  307. unsigned long irq_flags;
  308. int flags = epf_bar->flags;
  309. if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions ||
  310. (epf_bar->barno == BAR_5 &&
  311. flags & PCI_BASE_ADDRESS_MEM_TYPE_64) ||
  312. (flags & PCI_BASE_ADDRESS_SPACE_IO &&
  313. flags & PCI_BASE_ADDRESS_IO_MASK) ||
  314. (upper_32_bits(epf_bar->size) &&
  315. !(flags & PCI_BASE_ADDRESS_MEM_TYPE_64)))
  316. return -EINVAL;
  317. if (!epc->ops->set_bar)
  318. return 0;
  319. spin_lock_irqsave(&epc->lock, irq_flags);
  320. ret = epc->ops->set_bar(epc, func_no, epf_bar);
  321. spin_unlock_irqrestore(&epc->lock, irq_flags);
  322. return ret;
  323. }
  324. EXPORT_SYMBOL_GPL(pci_epc_set_bar);
  325. /**
  326. * pci_epc_write_header() - write standard configuration header
  327. * @epc: the EPC device to which the configuration header should be written
  328. * @func_no: the endpoint function number in the EPC device
  329. * @header: standard configuration header fields
  330. *
  331. * Invoke to write the configuration header to the endpoint controller. Every
  332. * endpoint controller will have a dedicated location to which the standard
  333. * configuration header would be written. The callback function should write
  334. * the header fields to this dedicated location.
  335. */
  336. int pci_epc_write_header(struct pci_epc *epc, u8 func_no,
  337. struct pci_epf_header *header)
  338. {
  339. int ret;
  340. unsigned long flags;
  341. if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
  342. return -EINVAL;
  343. if (!epc->ops->write_header)
  344. return 0;
  345. spin_lock_irqsave(&epc->lock, flags);
  346. ret = epc->ops->write_header(epc, func_no, header);
  347. spin_unlock_irqrestore(&epc->lock, flags);
  348. return ret;
  349. }
  350. EXPORT_SYMBOL_GPL(pci_epc_write_header);
  351. /**
  352. * pci_epc_add_epf() - bind PCI endpoint function to an endpoint controller
  353. * @epc: the EPC device to which the endpoint function should be added
  354. * @epf: the endpoint function to be added
  355. *
  356. * A PCI endpoint device can have one or more functions. In the case of PCIe,
  357. * the specification allows up to 8 PCIe endpoint functions. Invoke
  358. * pci_epc_add_epf() to add a PCI endpoint function to an endpoint controller.
  359. */
  360. int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf)
  361. {
  362. unsigned long flags;
  363. if (epf->epc)
  364. return -EBUSY;
  365. if (IS_ERR(epc))
  366. return -EINVAL;
  367. if (epf->func_no > epc->max_functions - 1)
  368. return -EINVAL;
  369. epf->epc = epc;
  370. spin_lock_irqsave(&epc->lock, flags);
  371. list_add_tail(&epf->list, &epc->pci_epf);
  372. spin_unlock_irqrestore(&epc->lock, flags);
  373. return 0;
  374. }
  375. EXPORT_SYMBOL_GPL(pci_epc_add_epf);
  376. /**
  377. * pci_epc_remove_epf() - remove PCI endpoint function from endpoint controller
  378. * @epc: the EPC device from which the endpoint function should be removed
  379. * @epf: the endpoint function to be removed
  380. *
  381. * Invoke to remove PCI endpoint function from the endpoint controller.
  382. */
  383. void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf)
  384. {
  385. unsigned long flags;
  386. if (!epc || IS_ERR(epc))
  387. return;
  388. spin_lock_irqsave(&epc->lock, flags);
  389. list_del(&epf->list);
  390. spin_unlock_irqrestore(&epc->lock, flags);
  391. }
  392. EXPORT_SYMBOL_GPL(pci_epc_remove_epf);
  393. /**
  394. * pci_epc_linkup() - Notify the EPF device that EPC device has established a
  395. * connection with the Root Complex.
  396. * @epc: the EPC device which has established link with the host
  397. *
  398. * Invoke to Notify the EPF device that the EPC device has established a
  399. * connection with the Root Complex.
  400. */
  401. void pci_epc_linkup(struct pci_epc *epc)
  402. {
  403. unsigned long flags;
  404. struct pci_epf *epf;
  405. if (!epc || IS_ERR(epc))
  406. return;
  407. spin_lock_irqsave(&epc->lock, flags);
  408. list_for_each_entry(epf, &epc->pci_epf, list)
  409. pci_epf_linkup(epf);
  410. spin_unlock_irqrestore(&epc->lock, flags);
  411. }
  412. EXPORT_SYMBOL_GPL(pci_epc_linkup);
  413. /**
  414. * pci_epc_destroy() - destroy the EPC device
  415. * @epc: the EPC device that has to be destroyed
  416. *
  417. * Invoke to destroy the PCI EPC device
  418. */
  419. void pci_epc_destroy(struct pci_epc *epc)
  420. {
  421. pci_ep_cfs_remove_epc_group(epc->group);
  422. device_unregister(&epc->dev);
  423. kfree(epc);
  424. }
  425. EXPORT_SYMBOL_GPL(pci_epc_destroy);
  426. /**
  427. * devm_pci_epc_destroy() - destroy the EPC device
  428. * @dev: device that wants to destroy the EPC
  429. * @epc: the EPC device that has to be destroyed
  430. *
  431. * Invoke to destroy the devres associated with this
  432. * pci_epc and destroy the EPC device.
  433. */
  434. void devm_pci_epc_destroy(struct device *dev, struct pci_epc *epc)
  435. {
  436. int r;
  437. r = devres_destroy(dev, devm_pci_epc_release, devm_pci_epc_match,
  438. epc);
  439. dev_WARN_ONCE(dev, r, "couldn't find PCI EPC resource\n");
  440. }
  441. EXPORT_SYMBOL_GPL(devm_pci_epc_destroy);
  442. /**
  443. * __pci_epc_create() - create a new endpoint controller (EPC) device
  444. * @dev: device that is creating the new EPC
  445. * @ops: function pointers for performing EPC operations
  446. * @owner: the owner of the module that creates the EPC device
  447. *
  448. * Invoke to create a new EPC device and add it to pci_epc class.
  449. */
  450. struct pci_epc *
  451. __pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
  452. struct module *owner)
  453. {
  454. int ret;
  455. struct pci_epc *epc;
  456. if (WARN_ON(!dev)) {
  457. ret = -EINVAL;
  458. goto err_ret;
  459. }
  460. epc = kzalloc(sizeof(*epc), GFP_KERNEL);
  461. if (!epc) {
  462. ret = -ENOMEM;
  463. goto err_ret;
  464. }
  465. spin_lock_init(&epc->lock);
  466. INIT_LIST_HEAD(&epc->pci_epf);
  467. device_initialize(&epc->dev);
  468. epc->dev.class = pci_epc_class;
  469. epc->dev.parent = dev;
  470. epc->ops = ops;
  471. ret = dev_set_name(&epc->dev, "%s", dev_name(dev));
  472. if (ret)
  473. goto put_dev;
  474. ret = device_add(&epc->dev);
  475. if (ret)
  476. goto put_dev;
  477. epc->group = pci_ep_cfs_add_epc_group(dev_name(dev));
  478. return epc;
  479. put_dev:
  480. put_device(&epc->dev);
  481. kfree(epc);
  482. err_ret:
  483. return ERR_PTR(ret);
  484. }
  485. EXPORT_SYMBOL_GPL(__pci_epc_create);
  486. /**
  487. * __devm_pci_epc_create() - create a new endpoint controller (EPC) device
  488. * @dev: device that is creating the new EPC
  489. * @ops: function pointers for performing EPC operations
  490. * @owner: the owner of the module that creates the EPC device
  491. *
  492. * Invoke to create a new EPC device and add it to pci_epc class.
  493. * While at that, it also associates the device with the pci_epc using devres.
  494. * On driver detach, release function is invoked on the devres data,
  495. * then, devres data is freed.
  496. */
  497. struct pci_epc *
  498. __devm_pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
  499. struct module *owner)
  500. {
  501. struct pci_epc **ptr, *epc;
  502. ptr = devres_alloc(devm_pci_epc_release, sizeof(*ptr), GFP_KERNEL);
  503. if (!ptr)
  504. return ERR_PTR(-ENOMEM);
  505. epc = __pci_epc_create(dev, ops, owner);
  506. if (!IS_ERR(epc)) {
  507. *ptr = epc;
  508. devres_add(dev, ptr);
  509. } else {
  510. devres_free(ptr);
  511. }
  512. return epc;
  513. }
  514. EXPORT_SYMBOL_GPL(__devm_pci_epc_create);
  515. static int __init pci_epc_init(void)
  516. {
  517. pci_epc_class = class_create(THIS_MODULE, "pci_epc");
  518. if (IS_ERR(pci_epc_class)) {
  519. pr_err("failed to create pci epc class --> %ld\n",
  520. PTR_ERR(pci_epc_class));
  521. return PTR_ERR(pci_epc_class);
  522. }
  523. return 0;
  524. }
  525. module_init(pci_epc_init);
  526. static void __exit pci_epc_exit(void)
  527. {
  528. class_destroy(pci_epc_class);
  529. }
  530. module_exit(pci_epc_exit);
  531. MODULE_DESCRIPTION("PCI EPC Library");
  532. MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
  533. MODULE_LICENSE("GPL v2");