Kconfig 3.3 KB

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  1. # SPDX-License-Identifier: GPL-2.0
  2. # Intel pin control drivers
  3. if (X86 || COMPILE_TEST)
  4. config PINCTRL_BAYTRAIL
  5. bool "Intel Baytrail GPIO pin control"
  6. depends on ACPI
  7. select GPIOLIB
  8. select GPIOLIB_IRQCHIP
  9. select PINMUX
  10. select PINCONF
  11. select GENERIC_PINCONF
  12. help
  13. driver for memory mapped GPIO functionality on Intel Baytrail
  14. platforms. Supports 3 banks with 102, 28 and 44 gpios.
  15. Most pins are usually muxed to some other functionality by firmware,
  16. so only a small amount is available for gpio use.
  17. Requires ACPI device enumeration code to set up a platform device.
  18. config PINCTRL_CHERRYVIEW
  19. tristate "Intel Cherryview/Braswell pinctrl and GPIO driver"
  20. depends on ACPI
  21. select PINMUX
  22. select PINCONF
  23. select GENERIC_PINCONF
  24. select GPIOLIB
  25. select GPIOLIB_IRQCHIP
  26. help
  27. Cherryview/Braswell pinctrl driver provides an interface that
  28. allows configuring of SoC pins and using them as GPIOs.
  29. config PINCTRL_MERRIFIELD
  30. tristate "Intel Merrifield pinctrl driver"
  31. depends on X86_INTEL_MID
  32. select PINMUX
  33. select PINCONF
  34. select GENERIC_PINCONF
  35. help
  36. Merrifield Family-Level Interface Shim (FLIS) driver provides an
  37. interface that allows configuring of SoC pins and using them as
  38. GPIOs.
  39. config PINCTRL_INTEL
  40. tristate
  41. select PINMUX
  42. select PINCONF
  43. select GENERIC_PINCONF
  44. select GPIOLIB
  45. select GPIOLIB_IRQCHIP
  46. config PINCTRL_BROXTON
  47. tristate "Intel Broxton pinctrl and GPIO driver"
  48. depends on ACPI
  49. select PINCTRL_INTEL
  50. help
  51. Broxton pinctrl driver provides an interface that allows
  52. configuring of SoC pins and using them as GPIOs.
  53. config PINCTRL_CANNONLAKE
  54. tristate "Intel Cannon Lake PCH pinctrl and GPIO driver"
  55. depends on ACPI
  56. select PINCTRL_INTEL
  57. help
  58. This pinctrl driver provides an interface that allows configuring
  59. of Intel Cannon Lake PCH pins and using them as GPIOs.
  60. config PINCTRL_CEDARFORK
  61. tristate "Intel Cedar Fork pinctrl and GPIO driver"
  62. depends on ACPI
  63. select PINCTRL_INTEL
  64. help
  65. This pinctrl driver provides an interface that allows configuring
  66. of Intel Cedar Fork PCH pins and using them as GPIOs.
  67. config PINCTRL_DENVERTON
  68. tristate "Intel Denverton pinctrl and GPIO driver"
  69. depends on ACPI
  70. select PINCTRL_INTEL
  71. help
  72. This pinctrl driver provides an interface that allows configuring
  73. of Intel Denverton SoC pins and using them as GPIOs.
  74. config PINCTRL_GEMINILAKE
  75. tristate "Intel Gemini Lake SoC pinctrl and GPIO driver"
  76. depends on ACPI
  77. select PINCTRL_INTEL
  78. help
  79. This pinctrl driver provides an interface that allows configuring
  80. of Intel Gemini Lake SoC pins and using them as GPIOs.
  81. config PINCTRL_ICELAKE
  82. tristate "Intel Ice Lake PCH pinctrl and GPIO driver"
  83. depends on ACPI
  84. select PINCTRL_INTEL
  85. help
  86. This pinctrl driver provides an interface that allows configuring
  87. of Intel Ice Lake PCH pins and using them as GPIOs.
  88. config PINCTRL_LEWISBURG
  89. tristate "Intel Lewisburg pinctrl and GPIO driver"
  90. depends on ACPI
  91. select PINCTRL_INTEL
  92. help
  93. This pinctrl driver provides an interface that allows configuring
  94. of Intel Lewisburg pins and using them as GPIOs.
  95. config PINCTRL_SUNRISEPOINT
  96. tristate "Intel Sunrisepoint pinctrl and GPIO driver"
  97. depends on ACPI
  98. select PINCTRL_INTEL
  99. help
  100. Sunrisepoint is the PCH of Intel Skylake. This pinctrl driver
  101. provides an interface that allows configuring of PCH pins and
  102. using them as GPIOs.
  103. endif