pinctrl-intel.c 39 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Intel pinctrl/GPIO core driver.
  4. *
  5. * Copyright (C) 2015, Intel Corporation
  6. * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
  7. * Mika Westerberg <mika.westerberg@linux.intel.com>
  8. */
  9. #include <linux/module.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/gpio/driver.h>
  12. #include <linux/log2.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/pinctrl/pinctrl.h>
  15. #include <linux/pinctrl/pinmux.h>
  16. #include <linux/pinctrl/pinconf.h>
  17. #include <linux/pinctrl/pinconf-generic.h>
  18. #include "../core.h"
  19. #include "pinctrl-intel.h"
  20. /* Offset from regs */
  21. #define REVID 0x000
  22. #define REVID_SHIFT 16
  23. #define REVID_MASK GENMASK(31, 16)
  24. #define PADBAR 0x00c
  25. #define GPI_IS 0x100
  26. #define PADOWN_BITS 4
  27. #define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS)
  28. #define PADOWN_MASK(p) (0xf << PADOWN_SHIFT(p))
  29. #define PADOWN_GPP(p) ((p) / 8)
  30. /* Offset from pad_regs */
  31. #define PADCFG0 0x000
  32. #define PADCFG0_RXEVCFG_SHIFT 25
  33. #define PADCFG0_RXEVCFG_MASK (3 << PADCFG0_RXEVCFG_SHIFT)
  34. #define PADCFG0_RXEVCFG_LEVEL 0
  35. #define PADCFG0_RXEVCFG_EDGE 1
  36. #define PADCFG0_RXEVCFG_DISABLED 2
  37. #define PADCFG0_RXEVCFG_EDGE_BOTH 3
  38. #define PADCFG0_PREGFRXSEL BIT(24)
  39. #define PADCFG0_RXINV BIT(23)
  40. #define PADCFG0_GPIROUTIOXAPIC BIT(20)
  41. #define PADCFG0_GPIROUTSCI BIT(19)
  42. #define PADCFG0_GPIROUTSMI BIT(18)
  43. #define PADCFG0_GPIROUTNMI BIT(17)
  44. #define PADCFG0_PMODE_SHIFT 10
  45. #define PADCFG0_PMODE_MASK (0xf << PADCFG0_PMODE_SHIFT)
  46. #define PADCFG0_PMODE_GPIO 0
  47. #define PADCFG0_GPIORXDIS BIT(9)
  48. #define PADCFG0_GPIOTXDIS BIT(8)
  49. #define PADCFG0_GPIORXSTATE BIT(1)
  50. #define PADCFG0_GPIOTXSTATE BIT(0)
  51. #define PADCFG1 0x004
  52. #define PADCFG1_TERM_UP BIT(13)
  53. #define PADCFG1_TERM_SHIFT 10
  54. #define PADCFG1_TERM_MASK (7 << PADCFG1_TERM_SHIFT)
  55. #define PADCFG1_TERM_20K 4
  56. #define PADCFG1_TERM_2K 3
  57. #define PADCFG1_TERM_5K 2
  58. #define PADCFG1_TERM_1K 1
  59. #define PADCFG2 0x008
  60. #define PADCFG2_DEBEN BIT(0)
  61. #define PADCFG2_DEBOUNCE_SHIFT 1
  62. #define PADCFG2_DEBOUNCE_MASK GENMASK(4, 1)
  63. #define DEBOUNCE_PERIOD 31250 /* ns */
  64. struct intel_pad_context {
  65. u32 padcfg0;
  66. u32 padcfg1;
  67. u32 padcfg2;
  68. };
  69. struct intel_community_context {
  70. u32 *intmask;
  71. };
  72. struct intel_pinctrl_context {
  73. struct intel_pad_context *pads;
  74. struct intel_community_context *communities;
  75. };
  76. /**
  77. * struct intel_pinctrl - Intel pinctrl private structure
  78. * @dev: Pointer to the device structure
  79. * @lock: Lock to serialize register access
  80. * @pctldesc: Pin controller description
  81. * @pctldev: Pointer to the pin controller device
  82. * @chip: GPIO chip in this pin controller
  83. * @soc: SoC/PCH specific pin configuration data
  84. * @communities: All communities in this pin controller
  85. * @ncommunities: Number of communities in this pin controller
  86. * @context: Configuration saved over system sleep
  87. * @irq: pinctrl/GPIO chip irq number
  88. */
  89. struct intel_pinctrl {
  90. struct device *dev;
  91. raw_spinlock_t lock;
  92. struct pinctrl_desc pctldesc;
  93. struct pinctrl_dev *pctldev;
  94. struct gpio_chip chip;
  95. const struct intel_pinctrl_soc_data *soc;
  96. struct intel_community *communities;
  97. size_t ncommunities;
  98. struct intel_pinctrl_context context;
  99. int irq;
  100. };
  101. #define pin_to_padno(c, p) ((p) - (c)->pin_base)
  102. #define padgroup_offset(g, p) ((p) - (g)->base)
  103. static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl,
  104. unsigned pin)
  105. {
  106. struct intel_community *community;
  107. int i;
  108. for (i = 0; i < pctrl->ncommunities; i++) {
  109. community = &pctrl->communities[i];
  110. if (pin >= community->pin_base &&
  111. pin < community->pin_base + community->npins)
  112. return community;
  113. }
  114. dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin);
  115. return NULL;
  116. }
  117. static const struct intel_padgroup *
  118. intel_community_get_padgroup(const struct intel_community *community,
  119. unsigned pin)
  120. {
  121. int i;
  122. for (i = 0; i < community->ngpps; i++) {
  123. const struct intel_padgroup *padgrp = &community->gpps[i];
  124. if (pin >= padgrp->base && pin < padgrp->base + padgrp->size)
  125. return padgrp;
  126. }
  127. return NULL;
  128. }
  129. static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin,
  130. unsigned reg)
  131. {
  132. const struct intel_community *community;
  133. unsigned padno;
  134. size_t nregs;
  135. community = intel_get_community(pctrl, pin);
  136. if (!community)
  137. return NULL;
  138. padno = pin_to_padno(community, pin);
  139. nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2;
  140. if (reg == PADCFG2 && !(community->features & PINCTRL_FEATURE_DEBOUNCE))
  141. return NULL;
  142. return community->pad_regs + reg + padno * nregs * 4;
  143. }
  144. static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin)
  145. {
  146. const struct intel_community *community;
  147. const struct intel_padgroup *padgrp;
  148. unsigned gpp, offset, gpp_offset;
  149. void __iomem *padown;
  150. community = intel_get_community(pctrl, pin);
  151. if (!community)
  152. return false;
  153. if (!community->padown_offset)
  154. return true;
  155. padgrp = intel_community_get_padgroup(community, pin);
  156. if (!padgrp)
  157. return false;
  158. gpp_offset = padgroup_offset(padgrp, pin);
  159. gpp = PADOWN_GPP(gpp_offset);
  160. offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4;
  161. padown = community->regs + offset;
  162. return !(readl(padown) & PADOWN_MASK(gpp_offset));
  163. }
  164. static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin)
  165. {
  166. const struct intel_community *community;
  167. const struct intel_padgroup *padgrp;
  168. unsigned offset, gpp_offset;
  169. void __iomem *hostown;
  170. community = intel_get_community(pctrl, pin);
  171. if (!community)
  172. return true;
  173. if (!community->hostown_offset)
  174. return false;
  175. padgrp = intel_community_get_padgroup(community, pin);
  176. if (!padgrp)
  177. return true;
  178. gpp_offset = padgroup_offset(padgrp, pin);
  179. offset = community->hostown_offset + padgrp->reg_num * 4;
  180. hostown = community->regs + offset;
  181. return !(readl(hostown) & BIT(gpp_offset));
  182. }
  183. static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin)
  184. {
  185. struct intel_community *community;
  186. const struct intel_padgroup *padgrp;
  187. unsigned offset, gpp_offset;
  188. u32 value;
  189. community = intel_get_community(pctrl, pin);
  190. if (!community)
  191. return true;
  192. if (!community->padcfglock_offset)
  193. return false;
  194. padgrp = intel_community_get_padgroup(community, pin);
  195. if (!padgrp)
  196. return true;
  197. gpp_offset = padgroup_offset(padgrp, pin);
  198. /*
  199. * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
  200. * the pad is considered unlocked. Any other case means that it is
  201. * either fully or partially locked and we don't touch it.
  202. */
  203. offset = community->padcfglock_offset + padgrp->reg_num * 8;
  204. value = readl(community->regs + offset);
  205. if (value & BIT(gpp_offset))
  206. return true;
  207. offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8;
  208. value = readl(community->regs + offset);
  209. if (value & BIT(gpp_offset))
  210. return true;
  211. return false;
  212. }
  213. static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned pin)
  214. {
  215. return intel_pad_owned_by_host(pctrl, pin) &&
  216. !intel_pad_locked(pctrl, pin);
  217. }
  218. static int intel_get_groups_count(struct pinctrl_dev *pctldev)
  219. {
  220. struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  221. return pctrl->soc->ngroups;
  222. }
  223. static const char *intel_get_group_name(struct pinctrl_dev *pctldev,
  224. unsigned group)
  225. {
  226. struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  227. return pctrl->soc->groups[group].name;
  228. }
  229. static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
  230. const unsigned **pins, unsigned *npins)
  231. {
  232. struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  233. *pins = pctrl->soc->groups[group].pins;
  234. *npins = pctrl->soc->groups[group].npins;
  235. return 0;
  236. }
  237. static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
  238. unsigned pin)
  239. {
  240. struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  241. void __iomem *padcfg;
  242. u32 cfg0, cfg1, mode;
  243. bool locked, acpi;
  244. if (!intel_pad_owned_by_host(pctrl, pin)) {
  245. seq_puts(s, "not available");
  246. return;
  247. }
  248. cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
  249. cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
  250. mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
  251. if (mode == PADCFG0_PMODE_GPIO)
  252. seq_puts(s, "GPIO ");
  253. else
  254. seq_printf(s, "mode %d ", mode);
  255. seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1);
  256. /* Dump the additional PADCFG registers if available */
  257. padcfg = intel_get_padcfg(pctrl, pin, PADCFG2);
  258. if (padcfg)
  259. seq_printf(s, " 0x%08x", readl(padcfg));
  260. locked = intel_pad_locked(pctrl, pin);
  261. acpi = intel_pad_acpi_mode(pctrl, pin);
  262. if (locked || acpi) {
  263. seq_puts(s, " [");
  264. if (locked) {
  265. seq_puts(s, "LOCKED");
  266. if (acpi)
  267. seq_puts(s, ", ");
  268. }
  269. if (acpi)
  270. seq_puts(s, "ACPI");
  271. seq_puts(s, "]");
  272. }
  273. }
  274. static const struct pinctrl_ops intel_pinctrl_ops = {
  275. .get_groups_count = intel_get_groups_count,
  276. .get_group_name = intel_get_group_name,
  277. .get_group_pins = intel_get_group_pins,
  278. .pin_dbg_show = intel_pin_dbg_show,
  279. };
  280. static int intel_get_functions_count(struct pinctrl_dev *pctldev)
  281. {
  282. struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  283. return pctrl->soc->nfunctions;
  284. }
  285. static const char *intel_get_function_name(struct pinctrl_dev *pctldev,
  286. unsigned function)
  287. {
  288. struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  289. return pctrl->soc->functions[function].name;
  290. }
  291. static int intel_get_function_groups(struct pinctrl_dev *pctldev,
  292. unsigned function,
  293. const char * const **groups,
  294. unsigned * const ngroups)
  295. {
  296. struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  297. *groups = pctrl->soc->functions[function].groups;
  298. *ngroups = pctrl->soc->functions[function].ngroups;
  299. return 0;
  300. }
  301. static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
  302. unsigned group)
  303. {
  304. struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  305. const struct intel_pingroup *grp = &pctrl->soc->groups[group];
  306. unsigned long flags;
  307. int i;
  308. raw_spin_lock_irqsave(&pctrl->lock, flags);
  309. /*
  310. * All pins in the groups needs to be accessible and writable
  311. * before we can enable the mux for this group.
  312. */
  313. for (i = 0; i < grp->npins; i++) {
  314. if (!intel_pad_usable(pctrl, grp->pins[i])) {
  315. raw_spin_unlock_irqrestore(&pctrl->lock, flags);
  316. return -EBUSY;
  317. }
  318. }
  319. /* Now enable the mux setting for each pin in the group */
  320. for (i = 0; i < grp->npins; i++) {
  321. void __iomem *padcfg0;
  322. u32 value;
  323. padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0);
  324. value = readl(padcfg0);
  325. value &= ~PADCFG0_PMODE_MASK;
  326. if (grp->modes)
  327. value |= grp->modes[i] << PADCFG0_PMODE_SHIFT;
  328. else
  329. value |= grp->mode << PADCFG0_PMODE_SHIFT;
  330. writel(value, padcfg0);
  331. }
  332. raw_spin_unlock_irqrestore(&pctrl->lock, flags);
  333. return 0;
  334. }
  335. static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input)
  336. {
  337. u32 value;
  338. value = readl(padcfg0);
  339. if (input) {
  340. value &= ~PADCFG0_GPIORXDIS;
  341. value |= PADCFG0_GPIOTXDIS;
  342. } else {
  343. value &= ~PADCFG0_GPIOTXDIS;
  344. value |= PADCFG0_GPIORXDIS;
  345. }
  346. writel(value, padcfg0);
  347. }
  348. static int intel_gpio_get_gpio_mode(void __iomem *padcfg0)
  349. {
  350. return (readl(padcfg0) & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
  351. }
  352. static void intel_gpio_set_gpio_mode(void __iomem *padcfg0)
  353. {
  354. u32 value;
  355. /* Put the pad into GPIO mode */
  356. value = readl(padcfg0) & ~PADCFG0_PMODE_MASK;
  357. /* Disable SCI/SMI/NMI generation */
  358. value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
  359. value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
  360. writel(value, padcfg0);
  361. }
  362. static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
  363. struct pinctrl_gpio_range *range,
  364. unsigned pin)
  365. {
  366. struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  367. void __iomem *padcfg0;
  368. unsigned long flags;
  369. raw_spin_lock_irqsave(&pctrl->lock, flags);
  370. if (!intel_pad_usable(pctrl, pin)) {
  371. raw_spin_unlock_irqrestore(&pctrl->lock, flags);
  372. return -EBUSY;
  373. }
  374. padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
  375. /*
  376. * If pin is already configured in GPIO mode, we assume that
  377. * firmware provides correct settings. In such case we avoid
  378. * potential glitches on the pin. Otherwise, for the pin in
  379. * alternative mode, consumer has to supply respective flags.
  380. */
  381. if (intel_gpio_get_gpio_mode(padcfg0) == PADCFG0_PMODE_GPIO) {
  382. raw_spin_unlock_irqrestore(&pctrl->lock, flags);
  383. return 0;
  384. }
  385. intel_gpio_set_gpio_mode(padcfg0);
  386. /* Disable TX buffer and enable RX (this will be input) */
  387. __intel_gpio_set_direction(padcfg0, true);
  388. raw_spin_unlock_irqrestore(&pctrl->lock, flags);
  389. return 0;
  390. }
  391. static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
  392. struct pinctrl_gpio_range *range,
  393. unsigned pin, bool input)
  394. {
  395. struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  396. void __iomem *padcfg0;
  397. unsigned long flags;
  398. raw_spin_lock_irqsave(&pctrl->lock, flags);
  399. padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
  400. __intel_gpio_set_direction(padcfg0, input);
  401. raw_spin_unlock_irqrestore(&pctrl->lock, flags);
  402. return 0;
  403. }
  404. static const struct pinmux_ops intel_pinmux_ops = {
  405. .get_functions_count = intel_get_functions_count,
  406. .get_function_name = intel_get_function_name,
  407. .get_function_groups = intel_get_function_groups,
  408. .set_mux = intel_pinmux_set_mux,
  409. .gpio_request_enable = intel_gpio_request_enable,
  410. .gpio_set_direction = intel_gpio_set_direction,
  411. };
  412. static int intel_config_get(struct pinctrl_dev *pctldev, unsigned pin,
  413. unsigned long *config)
  414. {
  415. struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  416. enum pin_config_param param = pinconf_to_config_param(*config);
  417. const struct intel_community *community;
  418. u32 value, term;
  419. u32 arg = 0;
  420. if (!intel_pad_owned_by_host(pctrl, pin))
  421. return -ENOTSUPP;
  422. community = intel_get_community(pctrl, pin);
  423. value = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
  424. term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
  425. switch (param) {
  426. case PIN_CONFIG_BIAS_DISABLE:
  427. if (term)
  428. return -EINVAL;
  429. break;
  430. case PIN_CONFIG_BIAS_PULL_UP:
  431. if (!term || !(value & PADCFG1_TERM_UP))
  432. return -EINVAL;
  433. switch (term) {
  434. case PADCFG1_TERM_1K:
  435. arg = 1000;
  436. break;
  437. case PADCFG1_TERM_2K:
  438. arg = 2000;
  439. break;
  440. case PADCFG1_TERM_5K:
  441. arg = 5000;
  442. break;
  443. case PADCFG1_TERM_20K:
  444. arg = 20000;
  445. break;
  446. }
  447. break;
  448. case PIN_CONFIG_BIAS_PULL_DOWN:
  449. if (!term || value & PADCFG1_TERM_UP)
  450. return -EINVAL;
  451. switch (term) {
  452. case PADCFG1_TERM_1K:
  453. if (!(community->features & PINCTRL_FEATURE_1K_PD))
  454. return -EINVAL;
  455. arg = 1000;
  456. break;
  457. case PADCFG1_TERM_5K:
  458. arg = 5000;
  459. break;
  460. case PADCFG1_TERM_20K:
  461. arg = 20000;
  462. break;
  463. }
  464. break;
  465. case PIN_CONFIG_INPUT_DEBOUNCE: {
  466. void __iomem *padcfg2;
  467. u32 v;
  468. padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
  469. if (!padcfg2)
  470. return -ENOTSUPP;
  471. v = readl(padcfg2);
  472. if (!(v & PADCFG2_DEBEN))
  473. return -EINVAL;
  474. v = (v & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT;
  475. arg = BIT(v) * DEBOUNCE_PERIOD / 1000;
  476. break;
  477. }
  478. default:
  479. return -ENOTSUPP;
  480. }
  481. *config = pinconf_to_config_packed(param, arg);
  482. return 0;
  483. }
  484. static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned pin,
  485. unsigned long config)
  486. {
  487. unsigned param = pinconf_to_config_param(config);
  488. unsigned arg = pinconf_to_config_argument(config);
  489. const struct intel_community *community;
  490. void __iomem *padcfg1;
  491. unsigned long flags;
  492. int ret = 0;
  493. u32 value;
  494. raw_spin_lock_irqsave(&pctrl->lock, flags);
  495. community = intel_get_community(pctrl, pin);
  496. padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
  497. value = readl(padcfg1);
  498. switch (param) {
  499. case PIN_CONFIG_BIAS_DISABLE:
  500. value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP);
  501. break;
  502. case PIN_CONFIG_BIAS_PULL_UP:
  503. value &= ~PADCFG1_TERM_MASK;
  504. value |= PADCFG1_TERM_UP;
  505. /* Set default strength value in case none is given */
  506. if (arg == 1)
  507. arg = 5000;
  508. switch (arg) {
  509. case 20000:
  510. value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
  511. break;
  512. case 5000:
  513. value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
  514. break;
  515. case 2000:
  516. value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT;
  517. break;
  518. case 1000:
  519. value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
  520. break;
  521. default:
  522. ret = -EINVAL;
  523. }
  524. break;
  525. case PIN_CONFIG_BIAS_PULL_DOWN:
  526. value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK);
  527. /* Set default strength value in case none is given */
  528. if (arg == 1)
  529. arg = 5000;
  530. switch (arg) {
  531. case 20000:
  532. value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
  533. break;
  534. case 5000:
  535. value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
  536. break;
  537. case 1000:
  538. if (!(community->features & PINCTRL_FEATURE_1K_PD)) {
  539. ret = -EINVAL;
  540. break;
  541. }
  542. value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
  543. break;
  544. default:
  545. ret = -EINVAL;
  546. }
  547. break;
  548. }
  549. if (!ret)
  550. writel(value, padcfg1);
  551. raw_spin_unlock_irqrestore(&pctrl->lock, flags);
  552. return ret;
  553. }
  554. static int intel_config_set_debounce(struct intel_pinctrl *pctrl, unsigned pin,
  555. unsigned debounce)
  556. {
  557. void __iomem *padcfg0, *padcfg2;
  558. unsigned long flags;
  559. u32 value0, value2;
  560. int ret = 0;
  561. padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
  562. if (!padcfg2)
  563. return -ENOTSUPP;
  564. padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
  565. raw_spin_lock_irqsave(&pctrl->lock, flags);
  566. value0 = readl(padcfg0);
  567. value2 = readl(padcfg2);
  568. /* Disable glitch filter and debouncer */
  569. value0 &= ~PADCFG0_PREGFRXSEL;
  570. value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK);
  571. if (debounce) {
  572. unsigned long v;
  573. v = order_base_2(debounce * 1000 / DEBOUNCE_PERIOD);
  574. if (v < 3 || v > 15) {
  575. ret = -EINVAL;
  576. goto exit_unlock;
  577. } else {
  578. /* Enable glitch filter and debouncer */
  579. value0 |= PADCFG0_PREGFRXSEL;
  580. value2 |= v << PADCFG2_DEBOUNCE_SHIFT;
  581. value2 |= PADCFG2_DEBEN;
  582. }
  583. }
  584. writel(value0, padcfg0);
  585. writel(value2, padcfg2);
  586. exit_unlock:
  587. raw_spin_unlock_irqrestore(&pctrl->lock, flags);
  588. return ret;
  589. }
  590. static int intel_config_set(struct pinctrl_dev *pctldev, unsigned pin,
  591. unsigned long *configs, unsigned nconfigs)
  592. {
  593. struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  594. int i, ret;
  595. if (!intel_pad_usable(pctrl, pin))
  596. return -ENOTSUPP;
  597. for (i = 0; i < nconfigs; i++) {
  598. switch (pinconf_to_config_param(configs[i])) {
  599. case PIN_CONFIG_BIAS_DISABLE:
  600. case PIN_CONFIG_BIAS_PULL_UP:
  601. case PIN_CONFIG_BIAS_PULL_DOWN:
  602. ret = intel_config_set_pull(pctrl, pin, configs[i]);
  603. if (ret)
  604. return ret;
  605. break;
  606. case PIN_CONFIG_INPUT_DEBOUNCE:
  607. ret = intel_config_set_debounce(pctrl, pin,
  608. pinconf_to_config_argument(configs[i]));
  609. if (ret)
  610. return ret;
  611. break;
  612. default:
  613. return -ENOTSUPP;
  614. }
  615. }
  616. return 0;
  617. }
  618. static const struct pinconf_ops intel_pinconf_ops = {
  619. .is_generic = true,
  620. .pin_config_get = intel_config_get,
  621. .pin_config_set = intel_config_set,
  622. };
  623. static const struct pinctrl_desc intel_pinctrl_desc = {
  624. .pctlops = &intel_pinctrl_ops,
  625. .pmxops = &intel_pinmux_ops,
  626. .confops = &intel_pinconf_ops,
  627. .owner = THIS_MODULE,
  628. };
  629. /**
  630. * intel_gpio_to_pin() - Translate from GPIO offset to pin number
  631. * @pctrl: Pinctrl structure
  632. * @offset: GPIO offset from gpiolib
  633. * @commmunity: Community is filled here if not %NULL
  634. * @padgrp: Pad group is filled here if not %NULL
  635. *
  636. * When coming through gpiolib irqchip, the GPIO offset is not
  637. * automatically translated to pinctrl pin number. This function can be
  638. * used to find out the corresponding pinctrl pin.
  639. */
  640. static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned offset,
  641. const struct intel_community **community,
  642. const struct intel_padgroup **padgrp)
  643. {
  644. int i;
  645. for (i = 0; i < pctrl->ncommunities; i++) {
  646. const struct intel_community *comm = &pctrl->communities[i];
  647. int j;
  648. for (j = 0; j < comm->ngpps; j++) {
  649. const struct intel_padgroup *pgrp = &comm->gpps[j];
  650. if (pgrp->gpio_base < 0)
  651. continue;
  652. if (offset >= pgrp->gpio_base &&
  653. offset < pgrp->gpio_base + pgrp->size) {
  654. int pin;
  655. pin = pgrp->base + offset - pgrp->gpio_base;
  656. if (community)
  657. *community = comm;
  658. if (padgrp)
  659. *padgrp = pgrp;
  660. return pin;
  661. }
  662. }
  663. }
  664. return -EINVAL;
  665. }
  666. static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
  667. {
  668. struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
  669. void __iomem *reg;
  670. u32 padcfg0;
  671. int pin;
  672. pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
  673. if (pin < 0)
  674. return -EINVAL;
  675. reg = intel_get_padcfg(pctrl, pin, PADCFG0);
  676. if (!reg)
  677. return -EINVAL;
  678. padcfg0 = readl(reg);
  679. if (!(padcfg0 & PADCFG0_GPIOTXDIS))
  680. return !!(padcfg0 & PADCFG0_GPIOTXSTATE);
  681. return !!(padcfg0 & PADCFG0_GPIORXSTATE);
  682. }
  683. static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  684. {
  685. struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
  686. unsigned long flags;
  687. void __iomem *reg;
  688. u32 padcfg0;
  689. int pin;
  690. pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
  691. if (pin < 0)
  692. return;
  693. reg = intel_get_padcfg(pctrl, pin, PADCFG0);
  694. if (!reg)
  695. return;
  696. raw_spin_lock_irqsave(&pctrl->lock, flags);
  697. padcfg0 = readl(reg);
  698. if (value)
  699. padcfg0 |= PADCFG0_GPIOTXSTATE;
  700. else
  701. padcfg0 &= ~PADCFG0_GPIOTXSTATE;
  702. writel(padcfg0, reg);
  703. raw_spin_unlock_irqrestore(&pctrl->lock, flags);
  704. }
  705. static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
  706. {
  707. struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
  708. void __iomem *reg;
  709. u32 padcfg0;
  710. int pin;
  711. pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
  712. if (pin < 0)
  713. return -EINVAL;
  714. reg = intel_get_padcfg(pctrl, pin, PADCFG0);
  715. if (!reg)
  716. return -EINVAL;
  717. padcfg0 = readl(reg);
  718. if (padcfg0 & PADCFG0_PMODE_MASK)
  719. return -EINVAL;
  720. return !!(padcfg0 & PADCFG0_GPIOTXDIS);
  721. }
  722. static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
  723. {
  724. return pinctrl_gpio_direction_input(chip->base + offset);
  725. }
  726. static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
  727. int value)
  728. {
  729. intel_gpio_set(chip, offset, value);
  730. return pinctrl_gpio_direction_output(chip->base + offset);
  731. }
  732. static const struct gpio_chip intel_gpio_chip = {
  733. .owner = THIS_MODULE,
  734. .request = gpiochip_generic_request,
  735. .free = gpiochip_generic_free,
  736. .get_direction = intel_gpio_get_direction,
  737. .direction_input = intel_gpio_direction_input,
  738. .direction_output = intel_gpio_direction_output,
  739. .get = intel_gpio_get,
  740. .set = intel_gpio_set,
  741. .set_config = gpiochip_generic_config,
  742. };
  743. static void intel_gpio_irq_ack(struct irq_data *d)
  744. {
  745. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  746. struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
  747. const struct intel_community *community;
  748. const struct intel_padgroup *padgrp;
  749. int pin;
  750. pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
  751. if (pin >= 0) {
  752. unsigned gpp, gpp_offset, is_offset;
  753. gpp = padgrp->reg_num;
  754. gpp_offset = padgroup_offset(padgrp, pin);
  755. is_offset = community->is_offset + gpp * 4;
  756. raw_spin_lock(&pctrl->lock);
  757. writel(BIT(gpp_offset), community->regs + is_offset);
  758. raw_spin_unlock(&pctrl->lock);
  759. }
  760. }
  761. static void intel_gpio_irq_enable(struct irq_data *d)
  762. {
  763. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  764. struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
  765. const struct intel_community *community;
  766. const struct intel_padgroup *padgrp;
  767. int pin;
  768. pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
  769. if (pin >= 0) {
  770. unsigned gpp, gpp_offset, is_offset;
  771. unsigned long flags;
  772. u32 value;
  773. gpp = padgrp->reg_num;
  774. gpp_offset = padgroup_offset(padgrp, pin);
  775. is_offset = community->is_offset + gpp * 4;
  776. raw_spin_lock_irqsave(&pctrl->lock, flags);
  777. /* Clear interrupt status first to avoid unexpected interrupt */
  778. writel(BIT(gpp_offset), community->regs + is_offset);
  779. value = readl(community->regs + community->ie_offset + gpp * 4);
  780. value |= BIT(gpp_offset);
  781. writel(value, community->regs + community->ie_offset + gpp * 4);
  782. raw_spin_unlock_irqrestore(&pctrl->lock, flags);
  783. }
  784. }
  785. static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
  786. {
  787. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  788. struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
  789. const struct intel_community *community;
  790. const struct intel_padgroup *padgrp;
  791. int pin;
  792. pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
  793. if (pin >= 0) {
  794. unsigned gpp, gpp_offset;
  795. unsigned long flags;
  796. void __iomem *reg;
  797. u32 value;
  798. gpp = padgrp->reg_num;
  799. gpp_offset = padgroup_offset(padgrp, pin);
  800. reg = community->regs + community->ie_offset + gpp * 4;
  801. raw_spin_lock_irqsave(&pctrl->lock, flags);
  802. value = readl(reg);
  803. if (mask)
  804. value &= ~BIT(gpp_offset);
  805. else
  806. value |= BIT(gpp_offset);
  807. writel(value, reg);
  808. raw_spin_unlock_irqrestore(&pctrl->lock, flags);
  809. }
  810. }
  811. static void intel_gpio_irq_mask(struct irq_data *d)
  812. {
  813. intel_gpio_irq_mask_unmask(d, true);
  814. }
  815. static void intel_gpio_irq_unmask(struct irq_data *d)
  816. {
  817. intel_gpio_irq_mask_unmask(d, false);
  818. }
  819. static int intel_gpio_irq_type(struct irq_data *d, unsigned type)
  820. {
  821. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  822. struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
  823. unsigned pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
  824. unsigned long flags;
  825. void __iomem *reg;
  826. u32 value;
  827. reg = intel_get_padcfg(pctrl, pin, PADCFG0);
  828. if (!reg)
  829. return -EINVAL;
  830. /*
  831. * If the pin is in ACPI mode it is still usable as a GPIO but it
  832. * cannot be used as IRQ because GPI_IS status bit will not be
  833. * updated by the host controller hardware.
  834. */
  835. if (intel_pad_acpi_mode(pctrl, pin)) {
  836. dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin);
  837. return -EPERM;
  838. }
  839. raw_spin_lock_irqsave(&pctrl->lock, flags);
  840. intel_gpio_set_gpio_mode(reg);
  841. value = readl(reg);
  842. value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
  843. if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
  844. value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT;
  845. } else if (type & IRQ_TYPE_EDGE_FALLING) {
  846. value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
  847. value |= PADCFG0_RXINV;
  848. } else if (type & IRQ_TYPE_EDGE_RISING) {
  849. value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
  850. } else if (type & IRQ_TYPE_LEVEL_MASK) {
  851. if (type & IRQ_TYPE_LEVEL_LOW)
  852. value |= PADCFG0_RXINV;
  853. } else {
  854. value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT;
  855. }
  856. writel(value, reg);
  857. if (type & IRQ_TYPE_EDGE_BOTH)
  858. irq_set_handler_locked(d, handle_edge_irq);
  859. else if (type & IRQ_TYPE_LEVEL_MASK)
  860. irq_set_handler_locked(d, handle_level_irq);
  861. raw_spin_unlock_irqrestore(&pctrl->lock, flags);
  862. return 0;
  863. }
  864. static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
  865. {
  866. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  867. struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
  868. unsigned pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
  869. if (on)
  870. enable_irq_wake(pctrl->irq);
  871. else
  872. disable_irq_wake(pctrl->irq);
  873. dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin);
  874. return 0;
  875. }
  876. static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
  877. const struct intel_community *community)
  878. {
  879. struct gpio_chip *gc = &pctrl->chip;
  880. irqreturn_t ret = IRQ_NONE;
  881. int gpp;
  882. for (gpp = 0; gpp < community->ngpps; gpp++) {
  883. const struct intel_padgroup *padgrp = &community->gpps[gpp];
  884. unsigned long pending, enabled, gpp_offset;
  885. pending = readl(community->regs + community->is_offset +
  886. padgrp->reg_num * 4);
  887. enabled = readl(community->regs + community->ie_offset +
  888. padgrp->reg_num * 4);
  889. /* Only interrupts that are enabled */
  890. pending &= enabled;
  891. for_each_set_bit(gpp_offset, &pending, padgrp->size) {
  892. unsigned irq;
  893. irq = irq_find_mapping(gc->irq.domain,
  894. padgrp->gpio_base + gpp_offset);
  895. generic_handle_irq(irq);
  896. ret |= IRQ_HANDLED;
  897. }
  898. }
  899. return ret;
  900. }
  901. static irqreturn_t intel_gpio_irq(int irq, void *data)
  902. {
  903. const struct intel_community *community;
  904. struct intel_pinctrl *pctrl = data;
  905. irqreturn_t ret = IRQ_NONE;
  906. int i;
  907. /* Need to check all communities for pending interrupts */
  908. for (i = 0; i < pctrl->ncommunities; i++) {
  909. community = &pctrl->communities[i];
  910. ret |= intel_gpio_community_irq_handler(pctrl, community);
  911. }
  912. return ret;
  913. }
  914. static struct irq_chip intel_gpio_irqchip = {
  915. .name = "intel-gpio",
  916. .irq_enable = intel_gpio_irq_enable,
  917. .irq_ack = intel_gpio_irq_ack,
  918. .irq_mask = intel_gpio_irq_mask,
  919. .irq_unmask = intel_gpio_irq_unmask,
  920. .irq_set_type = intel_gpio_irq_type,
  921. .irq_set_wake = intel_gpio_irq_wake,
  922. .flags = IRQCHIP_MASK_ON_SUSPEND,
  923. };
  924. static int intel_gpio_add_pin_ranges(struct intel_pinctrl *pctrl,
  925. const struct intel_community *community)
  926. {
  927. int ret = 0, i;
  928. for (i = 0; i < community->ngpps; i++) {
  929. const struct intel_padgroup *gpp = &community->gpps[i];
  930. if (gpp->gpio_base < 0)
  931. continue;
  932. ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
  933. gpp->gpio_base, gpp->base,
  934. gpp->size);
  935. if (ret)
  936. return ret;
  937. }
  938. return ret;
  939. }
  940. static unsigned intel_gpio_ngpio(const struct intel_pinctrl *pctrl)
  941. {
  942. const struct intel_community *community;
  943. unsigned ngpio = 0;
  944. int i, j;
  945. for (i = 0; i < pctrl->ncommunities; i++) {
  946. community = &pctrl->communities[i];
  947. for (j = 0; j < community->ngpps; j++) {
  948. const struct intel_padgroup *gpp = &community->gpps[j];
  949. if (gpp->gpio_base < 0)
  950. continue;
  951. if (gpp->gpio_base + gpp->size > ngpio)
  952. ngpio = gpp->gpio_base + gpp->size;
  953. }
  954. }
  955. return ngpio;
  956. }
  957. static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
  958. {
  959. int ret, i;
  960. pctrl->chip = intel_gpio_chip;
  961. pctrl->chip.ngpio = intel_gpio_ngpio(pctrl);
  962. pctrl->chip.label = dev_name(pctrl->dev);
  963. pctrl->chip.parent = pctrl->dev;
  964. pctrl->chip.base = -1;
  965. pctrl->irq = irq;
  966. ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);
  967. if (ret) {
  968. dev_err(pctrl->dev, "failed to register gpiochip\n");
  969. return ret;
  970. }
  971. for (i = 0; i < pctrl->ncommunities; i++) {
  972. struct intel_community *community = &pctrl->communities[i];
  973. ret = intel_gpio_add_pin_ranges(pctrl, community);
  974. if (ret) {
  975. dev_err(pctrl->dev, "failed to add GPIO pin range\n");
  976. return ret;
  977. }
  978. }
  979. /*
  980. * We need to request the interrupt here (instead of providing chip
  981. * to the irq directly) because on some platforms several GPIO
  982. * controllers share the same interrupt line.
  983. */
  984. ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq,
  985. IRQF_SHARED | IRQF_NO_THREAD,
  986. dev_name(pctrl->dev), pctrl);
  987. if (ret) {
  988. dev_err(pctrl->dev, "failed to request interrupt\n");
  989. return ret;
  990. }
  991. ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0,
  992. handle_bad_irq, IRQ_TYPE_NONE);
  993. if (ret) {
  994. dev_err(pctrl->dev, "failed to add irqchip\n");
  995. return ret;
  996. }
  997. gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq,
  998. NULL);
  999. return 0;
  1000. }
  1001. static int intel_pinctrl_add_padgroups(struct intel_pinctrl *pctrl,
  1002. struct intel_community *community)
  1003. {
  1004. struct intel_padgroup *gpps;
  1005. unsigned npins = community->npins;
  1006. unsigned padown_num = 0;
  1007. size_t ngpps, i;
  1008. if (community->gpps)
  1009. ngpps = community->ngpps;
  1010. else
  1011. ngpps = DIV_ROUND_UP(community->npins, community->gpp_size);
  1012. gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);
  1013. if (!gpps)
  1014. return -ENOMEM;
  1015. for (i = 0; i < ngpps; i++) {
  1016. if (community->gpps) {
  1017. gpps[i] = community->gpps[i];
  1018. } else {
  1019. unsigned gpp_size = community->gpp_size;
  1020. gpps[i].reg_num = i;
  1021. gpps[i].base = community->pin_base + i * gpp_size;
  1022. gpps[i].size = min(gpp_size, npins);
  1023. npins -= gpps[i].size;
  1024. }
  1025. if (gpps[i].size > 32)
  1026. return -EINVAL;
  1027. if (!gpps[i].gpio_base)
  1028. gpps[i].gpio_base = gpps[i].base;
  1029. gpps[i].padown_num = padown_num;
  1030. /*
  1031. * In older hardware the number of padown registers per
  1032. * group is fixed regardless of the group size.
  1033. */
  1034. if (community->gpp_num_padown_regs)
  1035. padown_num += community->gpp_num_padown_regs;
  1036. else
  1037. padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32);
  1038. }
  1039. community->ngpps = ngpps;
  1040. community->gpps = gpps;
  1041. return 0;
  1042. }
  1043. static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
  1044. {
  1045. #ifdef CONFIG_PM_SLEEP
  1046. const struct intel_pinctrl_soc_data *soc = pctrl->soc;
  1047. struct intel_community_context *communities;
  1048. struct intel_pad_context *pads;
  1049. int i;
  1050. pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL);
  1051. if (!pads)
  1052. return -ENOMEM;
  1053. communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities,
  1054. sizeof(*communities), GFP_KERNEL);
  1055. if (!communities)
  1056. return -ENOMEM;
  1057. for (i = 0; i < pctrl->ncommunities; i++) {
  1058. struct intel_community *community = &pctrl->communities[i];
  1059. u32 *intmask;
  1060. intmask = devm_kcalloc(pctrl->dev, community->ngpps,
  1061. sizeof(*intmask), GFP_KERNEL);
  1062. if (!intmask)
  1063. return -ENOMEM;
  1064. communities[i].intmask = intmask;
  1065. }
  1066. pctrl->context.pads = pads;
  1067. pctrl->context.communities = communities;
  1068. #endif
  1069. return 0;
  1070. }
  1071. int intel_pinctrl_probe(struct platform_device *pdev,
  1072. const struct intel_pinctrl_soc_data *soc_data)
  1073. {
  1074. struct intel_pinctrl *pctrl;
  1075. int i, ret, irq;
  1076. if (!soc_data)
  1077. return -EINVAL;
  1078. pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
  1079. if (!pctrl)
  1080. return -ENOMEM;
  1081. pctrl->dev = &pdev->dev;
  1082. pctrl->soc = soc_data;
  1083. raw_spin_lock_init(&pctrl->lock);
  1084. /*
  1085. * Make a copy of the communities which we can use to hold pointers
  1086. * to the registers.
  1087. */
  1088. pctrl->ncommunities = pctrl->soc->ncommunities;
  1089. pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities,
  1090. sizeof(*pctrl->communities), GFP_KERNEL);
  1091. if (!pctrl->communities)
  1092. return -ENOMEM;
  1093. for (i = 0; i < pctrl->ncommunities; i++) {
  1094. struct intel_community *community = &pctrl->communities[i];
  1095. struct resource *res;
  1096. void __iomem *regs;
  1097. u32 padbar;
  1098. *community = pctrl->soc->communities[i];
  1099. res = platform_get_resource(pdev, IORESOURCE_MEM,
  1100. community->barno);
  1101. regs = devm_ioremap_resource(&pdev->dev, res);
  1102. if (IS_ERR(regs))
  1103. return PTR_ERR(regs);
  1104. /*
  1105. * Determine community features based on the revision if
  1106. * not specified already.
  1107. */
  1108. if (!community->features) {
  1109. u32 rev;
  1110. rev = (readl(regs + REVID) & REVID_MASK) >> REVID_SHIFT;
  1111. if (rev >= 0x94) {
  1112. community->features |= PINCTRL_FEATURE_DEBOUNCE;
  1113. community->features |= PINCTRL_FEATURE_1K_PD;
  1114. }
  1115. }
  1116. /* Read offset of the pad configuration registers */
  1117. padbar = readl(regs + PADBAR);
  1118. community->regs = regs;
  1119. community->pad_regs = regs + padbar;
  1120. if (!community->is_offset)
  1121. community->is_offset = GPI_IS;
  1122. ret = intel_pinctrl_add_padgroups(pctrl, community);
  1123. if (ret)
  1124. return ret;
  1125. }
  1126. irq = platform_get_irq(pdev, 0);
  1127. if (irq < 0) {
  1128. dev_err(&pdev->dev, "failed to get interrupt number\n");
  1129. return irq;
  1130. }
  1131. ret = intel_pinctrl_pm_init(pctrl);
  1132. if (ret)
  1133. return ret;
  1134. pctrl->pctldesc = intel_pinctrl_desc;
  1135. pctrl->pctldesc.name = dev_name(&pdev->dev);
  1136. pctrl->pctldesc.pins = pctrl->soc->pins;
  1137. pctrl->pctldesc.npins = pctrl->soc->npins;
  1138. pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
  1139. pctrl);
  1140. if (IS_ERR(pctrl->pctldev)) {
  1141. dev_err(&pdev->dev, "failed to register pinctrl driver\n");
  1142. return PTR_ERR(pctrl->pctldev);
  1143. }
  1144. ret = intel_gpio_probe(pctrl, irq);
  1145. if (ret)
  1146. return ret;
  1147. platform_set_drvdata(pdev, pctrl);
  1148. return 0;
  1149. }
  1150. EXPORT_SYMBOL_GPL(intel_pinctrl_probe);
  1151. #ifdef CONFIG_PM_SLEEP
  1152. static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned pin)
  1153. {
  1154. const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin);
  1155. if (!pd || !intel_pad_usable(pctrl, pin))
  1156. return false;
  1157. /*
  1158. * Only restore the pin if it is actually in use by the kernel (or
  1159. * by userspace). It is possible that some pins are used by the
  1160. * BIOS during resume and those are not always locked down so leave
  1161. * them alone.
  1162. */
  1163. if (pd->mux_owner || pd->gpio_owner ||
  1164. gpiochip_line_is_irq(&pctrl->chip, pin))
  1165. return true;
  1166. return false;
  1167. }
  1168. int intel_pinctrl_suspend(struct device *dev)
  1169. {
  1170. struct platform_device *pdev = to_platform_device(dev);
  1171. struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
  1172. struct intel_community_context *communities;
  1173. struct intel_pad_context *pads;
  1174. int i;
  1175. pads = pctrl->context.pads;
  1176. for (i = 0; i < pctrl->soc->npins; i++) {
  1177. const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
  1178. void __iomem *padcfg;
  1179. u32 val;
  1180. if (!intel_pinctrl_should_save(pctrl, desc->number))
  1181. continue;
  1182. val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0));
  1183. pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE;
  1184. val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1));
  1185. pads[i].padcfg1 = val;
  1186. padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
  1187. if (padcfg)
  1188. pads[i].padcfg2 = readl(padcfg);
  1189. }
  1190. communities = pctrl->context.communities;
  1191. for (i = 0; i < pctrl->ncommunities; i++) {
  1192. struct intel_community *community = &pctrl->communities[i];
  1193. void __iomem *base;
  1194. unsigned gpp;
  1195. base = community->regs + community->ie_offset;
  1196. for (gpp = 0; gpp < community->ngpps; gpp++)
  1197. communities[i].intmask[gpp] = readl(base + gpp * 4);
  1198. }
  1199. return 0;
  1200. }
  1201. EXPORT_SYMBOL_GPL(intel_pinctrl_suspend);
  1202. static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
  1203. {
  1204. size_t i;
  1205. for (i = 0; i < pctrl->ncommunities; i++) {
  1206. const struct intel_community *community;
  1207. void __iomem *base;
  1208. unsigned gpp;
  1209. community = &pctrl->communities[i];
  1210. base = community->regs;
  1211. for (gpp = 0; gpp < community->ngpps; gpp++) {
  1212. /* Mask and clear all interrupts */
  1213. writel(0, base + community->ie_offset + gpp * 4);
  1214. writel(0xffff, base + community->is_offset + gpp * 4);
  1215. }
  1216. }
  1217. }
  1218. int intel_pinctrl_resume(struct device *dev)
  1219. {
  1220. struct platform_device *pdev = to_platform_device(dev);
  1221. struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
  1222. const struct intel_community_context *communities;
  1223. const struct intel_pad_context *pads;
  1224. int i;
  1225. /* Mask all interrupts */
  1226. intel_gpio_irq_init(pctrl);
  1227. pads = pctrl->context.pads;
  1228. for (i = 0; i < pctrl->soc->npins; i++) {
  1229. const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
  1230. void __iomem *padcfg;
  1231. u32 val;
  1232. if (!intel_pinctrl_should_save(pctrl, desc->number))
  1233. continue;
  1234. padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0);
  1235. val = readl(padcfg) & ~PADCFG0_GPIORXSTATE;
  1236. if (val != pads[i].padcfg0) {
  1237. writel(pads[i].padcfg0, padcfg);
  1238. dev_dbg(dev, "restored pin %u padcfg0 %#08x\n",
  1239. desc->number, readl(padcfg));
  1240. }
  1241. padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1);
  1242. val = readl(padcfg);
  1243. if (val != pads[i].padcfg1) {
  1244. writel(pads[i].padcfg1, padcfg);
  1245. dev_dbg(dev, "restored pin %u padcfg1 %#08x\n",
  1246. desc->number, readl(padcfg));
  1247. }
  1248. padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
  1249. if (padcfg) {
  1250. val = readl(padcfg);
  1251. if (val != pads[i].padcfg2) {
  1252. writel(pads[i].padcfg2, padcfg);
  1253. dev_dbg(dev, "restored pin %u padcfg2 %#08x\n",
  1254. desc->number, readl(padcfg));
  1255. }
  1256. }
  1257. }
  1258. communities = pctrl->context.communities;
  1259. for (i = 0; i < pctrl->ncommunities; i++) {
  1260. struct intel_community *community = &pctrl->communities[i];
  1261. void __iomem *base;
  1262. unsigned gpp;
  1263. base = community->regs + community->ie_offset;
  1264. for (gpp = 0; gpp < community->ngpps; gpp++) {
  1265. writel(communities[i].intmask[gpp], base + gpp * 4);
  1266. dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp,
  1267. readl(base + gpp * 4));
  1268. }
  1269. }
  1270. return 0;
  1271. }
  1272. EXPORT_SYMBOL_GPL(intel_pinctrl_resume);
  1273. #endif
  1274. MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
  1275. MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
  1276. MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver");
  1277. MODULE_LICENSE("GPL v2");