pinctrl-axp209.c 13 KB

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  1. /*
  2. * AXP20x pinctrl and GPIO driver
  3. *
  4. * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
  5. * Copyright (C) 2017 Quentin Schulz <quentin.schulz@free-electrons.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the
  9. * Free Software Foundation; either version 2 of the License, or (at your
  10. * option) any later version.
  11. */
  12. #include <linux/bitops.h>
  13. #include <linux/device.h>
  14. #include <linux/gpio/driver.h>
  15. #include <linux/init.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/kernel.h>
  18. #include <linux/mfd/axp20x.h>
  19. #include <linux/module.h>
  20. #include <linux/of.h>
  21. #include <linux/of_device.h>
  22. #include <linux/pinctrl/pinconf-generic.h>
  23. #include <linux/pinctrl/pinctrl.h>
  24. #include <linux/pinctrl/pinmux.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/regmap.h>
  27. #include <linux/slab.h>
  28. #define AXP20X_GPIO_FUNCTIONS 0x7
  29. #define AXP20X_GPIO_FUNCTION_OUT_LOW 0
  30. #define AXP20X_GPIO_FUNCTION_OUT_HIGH 1
  31. #define AXP20X_GPIO_FUNCTION_INPUT 2
  32. #define AXP20X_FUNC_GPIO_OUT 0
  33. #define AXP20X_FUNC_GPIO_IN 1
  34. #define AXP20X_FUNC_LDO 2
  35. #define AXP20X_FUNC_ADC 3
  36. #define AXP20X_FUNCS_NB 4
  37. #define AXP20X_MUX_GPIO_OUT 0
  38. #define AXP20X_MUX_GPIO_IN BIT(1)
  39. #define AXP20X_MUX_ADC BIT(2)
  40. #define AXP813_MUX_ADC (BIT(2) | BIT(0))
  41. struct axp20x_pctrl_desc {
  42. const struct pinctrl_pin_desc *pins;
  43. unsigned int npins;
  44. /* Stores the pins supporting LDO function. Bit offset is pin number. */
  45. u8 ldo_mask;
  46. /* Stores the pins supporting ADC function. Bit offset is pin number. */
  47. u8 adc_mask;
  48. u8 gpio_status_offset;
  49. u8 adc_mux;
  50. };
  51. struct axp20x_pinctrl_function {
  52. const char *name;
  53. unsigned int muxval;
  54. const char **groups;
  55. unsigned int ngroups;
  56. };
  57. struct axp20x_pctl {
  58. struct gpio_chip chip;
  59. struct regmap *regmap;
  60. struct pinctrl_dev *pctl_dev;
  61. struct device *dev;
  62. const struct axp20x_pctrl_desc *desc;
  63. struct axp20x_pinctrl_function funcs[AXP20X_FUNCS_NB];
  64. };
  65. static const struct pinctrl_pin_desc axp209_pins[] = {
  66. PINCTRL_PIN(0, "GPIO0"),
  67. PINCTRL_PIN(1, "GPIO1"),
  68. PINCTRL_PIN(2, "GPIO2"),
  69. };
  70. static const struct pinctrl_pin_desc axp813_pins[] = {
  71. PINCTRL_PIN(0, "GPIO0"),
  72. PINCTRL_PIN(1, "GPIO1"),
  73. };
  74. static const struct axp20x_pctrl_desc axp20x_data = {
  75. .pins = axp209_pins,
  76. .npins = ARRAY_SIZE(axp209_pins),
  77. .ldo_mask = BIT(0) | BIT(1),
  78. .adc_mask = BIT(0) | BIT(1),
  79. .gpio_status_offset = 4,
  80. .adc_mux = AXP20X_MUX_ADC,
  81. };
  82. static const struct axp20x_pctrl_desc axp813_data = {
  83. .pins = axp813_pins,
  84. .npins = ARRAY_SIZE(axp813_pins),
  85. .ldo_mask = BIT(0) | BIT(1),
  86. .adc_mask = BIT(0),
  87. .gpio_status_offset = 0,
  88. .adc_mux = AXP813_MUX_ADC,
  89. };
  90. static int axp20x_gpio_get_reg(unsigned int offset)
  91. {
  92. switch (offset) {
  93. case 0:
  94. return AXP20X_GPIO0_CTRL;
  95. case 1:
  96. return AXP20X_GPIO1_CTRL;
  97. case 2:
  98. return AXP20X_GPIO2_CTRL;
  99. }
  100. return -EINVAL;
  101. }
  102. static int axp20x_gpio_input(struct gpio_chip *chip, unsigned int offset)
  103. {
  104. return pinctrl_gpio_direction_input(chip->base + offset);
  105. }
  106. static int axp20x_gpio_get(struct gpio_chip *chip, unsigned int offset)
  107. {
  108. struct axp20x_pctl *pctl = gpiochip_get_data(chip);
  109. unsigned int val;
  110. int ret;
  111. ret = regmap_read(pctl->regmap, AXP20X_GPIO20_SS, &val);
  112. if (ret)
  113. return ret;
  114. return !!(val & BIT(offset + pctl->desc->gpio_status_offset));
  115. }
  116. static int axp20x_gpio_get_direction(struct gpio_chip *chip,
  117. unsigned int offset)
  118. {
  119. struct axp20x_pctl *pctl = gpiochip_get_data(chip);
  120. unsigned int val;
  121. int reg, ret;
  122. reg = axp20x_gpio_get_reg(offset);
  123. if (reg < 0)
  124. return reg;
  125. ret = regmap_read(pctl->regmap, reg, &val);
  126. if (ret)
  127. return ret;
  128. /*
  129. * This shouldn't really happen if the pin is in use already,
  130. * or if it's not in use yet, it doesn't matter since we're
  131. * going to change the value soon anyway. Default to output.
  132. */
  133. if ((val & AXP20X_GPIO_FUNCTIONS) > 2)
  134. return 0;
  135. /*
  136. * The GPIO directions are the three lowest values.
  137. * 2 is input, 0 and 1 are output
  138. */
  139. return val & 2;
  140. }
  141. static int axp20x_gpio_output(struct gpio_chip *chip, unsigned int offset,
  142. int value)
  143. {
  144. chip->set(chip, offset, value);
  145. return 0;
  146. }
  147. static void axp20x_gpio_set(struct gpio_chip *chip, unsigned int offset,
  148. int value)
  149. {
  150. struct axp20x_pctl *pctl = gpiochip_get_data(chip);
  151. int reg;
  152. reg = axp20x_gpio_get_reg(offset);
  153. if (reg < 0)
  154. return;
  155. regmap_update_bits(pctl->regmap, reg,
  156. AXP20X_GPIO_FUNCTIONS,
  157. value ? AXP20X_GPIO_FUNCTION_OUT_HIGH :
  158. AXP20X_GPIO_FUNCTION_OUT_LOW);
  159. }
  160. static int axp20x_pmx_set(struct pinctrl_dev *pctldev, unsigned int offset,
  161. u8 config)
  162. {
  163. struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
  164. int reg;
  165. reg = axp20x_gpio_get_reg(offset);
  166. if (reg < 0)
  167. return reg;
  168. return regmap_update_bits(pctl->regmap, reg, AXP20X_GPIO_FUNCTIONS,
  169. config);
  170. }
  171. static int axp20x_pmx_func_cnt(struct pinctrl_dev *pctldev)
  172. {
  173. struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
  174. return ARRAY_SIZE(pctl->funcs);
  175. }
  176. static const char *axp20x_pmx_func_name(struct pinctrl_dev *pctldev,
  177. unsigned int selector)
  178. {
  179. struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
  180. return pctl->funcs[selector].name;
  181. }
  182. static int axp20x_pmx_func_groups(struct pinctrl_dev *pctldev,
  183. unsigned int selector,
  184. const char * const **groups,
  185. unsigned int *num_groups)
  186. {
  187. struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
  188. *groups = pctl->funcs[selector].groups;
  189. *num_groups = pctl->funcs[selector].ngroups;
  190. return 0;
  191. }
  192. static int axp20x_pmx_set_mux(struct pinctrl_dev *pctldev,
  193. unsigned int function, unsigned int group)
  194. {
  195. struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
  196. unsigned int mask;
  197. /* Every pin supports GPIO_OUT and GPIO_IN functions */
  198. if (function <= AXP20X_FUNC_GPIO_IN)
  199. return axp20x_pmx_set(pctldev, group,
  200. pctl->funcs[function].muxval);
  201. if (function == AXP20X_FUNC_LDO)
  202. mask = pctl->desc->ldo_mask;
  203. else
  204. mask = pctl->desc->adc_mask;
  205. if (!(BIT(group) & mask))
  206. return -EINVAL;
  207. /*
  208. * We let the regulator framework handle the LDO muxing as muxing bits
  209. * are basically also regulators on/off bits. It's better not to enforce
  210. * any state of the regulator when selecting LDO mux so that we don't
  211. * interfere with the regulator driver.
  212. */
  213. if (function == AXP20X_FUNC_LDO)
  214. return 0;
  215. return axp20x_pmx_set(pctldev, group, pctl->funcs[function].muxval);
  216. }
  217. static int axp20x_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
  218. struct pinctrl_gpio_range *range,
  219. unsigned int offset, bool input)
  220. {
  221. struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
  222. if (input)
  223. return axp20x_pmx_set(pctldev, offset,
  224. pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval);
  225. return axp20x_pmx_set(pctldev, offset,
  226. pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval);
  227. }
  228. static const struct pinmux_ops axp20x_pmx_ops = {
  229. .get_functions_count = axp20x_pmx_func_cnt,
  230. .get_function_name = axp20x_pmx_func_name,
  231. .get_function_groups = axp20x_pmx_func_groups,
  232. .set_mux = axp20x_pmx_set_mux,
  233. .gpio_set_direction = axp20x_pmx_gpio_set_direction,
  234. .strict = true,
  235. };
  236. static int axp20x_groups_cnt(struct pinctrl_dev *pctldev)
  237. {
  238. struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
  239. return pctl->desc->npins;
  240. }
  241. static int axp20x_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
  242. const unsigned int **pins, unsigned int *num_pins)
  243. {
  244. struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
  245. *pins = (unsigned int *)&pctl->desc->pins[selector];
  246. *num_pins = 1;
  247. return 0;
  248. }
  249. static const char *axp20x_group_name(struct pinctrl_dev *pctldev,
  250. unsigned int selector)
  251. {
  252. struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
  253. return pctl->desc->pins[selector].name;
  254. }
  255. static const struct pinctrl_ops axp20x_pctrl_ops = {
  256. .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
  257. .dt_free_map = pinconf_generic_dt_free_map,
  258. .get_groups_count = axp20x_groups_cnt,
  259. .get_group_name = axp20x_group_name,
  260. .get_group_pins = axp20x_group_pins,
  261. };
  262. static int axp20x_funcs_groups_from_mask(struct device *dev, unsigned int mask,
  263. unsigned int mask_len,
  264. struct axp20x_pinctrl_function *func,
  265. const struct pinctrl_pin_desc *pins)
  266. {
  267. unsigned long int mask_cpy = mask;
  268. const char **group;
  269. unsigned int ngroups = hweight8(mask);
  270. int bit;
  271. func->ngroups = ngroups;
  272. if (func->ngroups > 0) {
  273. func->groups = devm_kcalloc(dev,
  274. ngroups, sizeof(const char *),
  275. GFP_KERNEL);
  276. if (!func->groups)
  277. return -ENOMEM;
  278. group = func->groups;
  279. for_each_set_bit(bit, &mask_cpy, mask_len) {
  280. *group = pins[bit].name;
  281. group++;
  282. }
  283. }
  284. return 0;
  285. }
  286. static int axp20x_build_funcs_groups(struct platform_device *pdev)
  287. {
  288. struct axp20x_pctl *pctl = platform_get_drvdata(pdev);
  289. int i, ret, pin, npins = pctl->desc->npins;
  290. pctl->funcs[AXP20X_FUNC_GPIO_OUT].name = "gpio_out";
  291. pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval = AXP20X_MUX_GPIO_OUT;
  292. pctl->funcs[AXP20X_FUNC_GPIO_IN].name = "gpio_in";
  293. pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval = AXP20X_MUX_GPIO_IN;
  294. pctl->funcs[AXP20X_FUNC_LDO].name = "ldo";
  295. /*
  296. * Muxval for LDO is useless as we won't use it.
  297. * See comment in axp20x_pmx_set_mux.
  298. */
  299. pctl->funcs[AXP20X_FUNC_ADC].name = "adc";
  300. pctl->funcs[AXP20X_FUNC_ADC].muxval = pctl->desc->adc_mux;
  301. /* Every pin supports GPIO_OUT and GPIO_IN functions */
  302. for (i = 0; i <= AXP20X_FUNC_GPIO_IN; i++) {
  303. pctl->funcs[i].ngroups = npins;
  304. pctl->funcs[i].groups = devm_kcalloc(&pdev->dev,
  305. npins, sizeof(char *),
  306. GFP_KERNEL);
  307. for (pin = 0; pin < npins; pin++)
  308. pctl->funcs[i].groups[pin] = pctl->desc->pins[pin].name;
  309. }
  310. ret = axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->ldo_mask,
  311. npins, &pctl->funcs[AXP20X_FUNC_LDO],
  312. pctl->desc->pins);
  313. if (ret)
  314. return ret;
  315. ret = axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->adc_mask,
  316. npins, &pctl->funcs[AXP20X_FUNC_ADC],
  317. pctl->desc->pins);
  318. if (ret)
  319. return ret;
  320. return 0;
  321. }
  322. static const struct of_device_id axp20x_pctl_match[] = {
  323. { .compatible = "x-powers,axp209-gpio", .data = &axp20x_data, },
  324. { .compatible = "x-powers,axp813-gpio", .data = &axp813_data, },
  325. { }
  326. };
  327. MODULE_DEVICE_TABLE(of, axp20x_pctl_match);
  328. static int axp20x_pctl_probe(struct platform_device *pdev)
  329. {
  330. struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
  331. struct axp20x_pctl *pctl;
  332. struct device *dev = &pdev->dev;
  333. struct pinctrl_desc *pctrl_desc;
  334. int ret;
  335. if (!of_device_is_available(pdev->dev.of_node))
  336. return -ENODEV;
  337. if (!axp20x) {
  338. dev_err(&pdev->dev, "Parent drvdata not set\n");
  339. return -EINVAL;
  340. }
  341. pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
  342. if (!pctl)
  343. return -ENOMEM;
  344. pctl->chip.base = -1;
  345. pctl->chip.can_sleep = true;
  346. pctl->chip.request = gpiochip_generic_request;
  347. pctl->chip.free = gpiochip_generic_free;
  348. pctl->chip.parent = &pdev->dev;
  349. pctl->chip.label = dev_name(&pdev->dev);
  350. pctl->chip.owner = THIS_MODULE;
  351. pctl->chip.get = axp20x_gpio_get;
  352. pctl->chip.get_direction = axp20x_gpio_get_direction;
  353. pctl->chip.set = axp20x_gpio_set;
  354. pctl->chip.direction_input = axp20x_gpio_input;
  355. pctl->chip.direction_output = axp20x_gpio_output;
  356. pctl->desc = of_device_get_match_data(dev);
  357. pctl->chip.ngpio = pctl->desc->npins;
  358. pctl->regmap = axp20x->regmap;
  359. pctl->dev = &pdev->dev;
  360. platform_set_drvdata(pdev, pctl);
  361. ret = axp20x_build_funcs_groups(pdev);
  362. if (ret) {
  363. dev_err(&pdev->dev, "failed to build groups\n");
  364. return ret;
  365. }
  366. pctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctrl_desc), GFP_KERNEL);
  367. if (!pctrl_desc)
  368. return -ENOMEM;
  369. pctrl_desc->name = dev_name(&pdev->dev);
  370. pctrl_desc->owner = THIS_MODULE;
  371. pctrl_desc->pins = pctl->desc->pins;
  372. pctrl_desc->npins = pctl->desc->npins;
  373. pctrl_desc->pctlops = &axp20x_pctrl_ops;
  374. pctrl_desc->pmxops = &axp20x_pmx_ops;
  375. pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl);
  376. if (IS_ERR(pctl->pctl_dev)) {
  377. dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
  378. return PTR_ERR(pctl->pctl_dev);
  379. }
  380. ret = devm_gpiochip_add_data(&pdev->dev, &pctl->chip, pctl);
  381. if (ret) {
  382. dev_err(&pdev->dev, "Failed to register GPIO chip\n");
  383. return ret;
  384. }
  385. ret = gpiochip_add_pin_range(&pctl->chip, dev_name(&pdev->dev),
  386. pctl->desc->pins->number,
  387. pctl->desc->pins->number,
  388. pctl->desc->npins);
  389. if (ret) {
  390. dev_err(&pdev->dev, "failed to add pin range\n");
  391. return ret;
  392. }
  393. dev_info(&pdev->dev, "AXP209 pinctrl and GPIO driver loaded\n");
  394. return 0;
  395. }
  396. static struct platform_driver axp20x_pctl_driver = {
  397. .probe = axp20x_pctl_probe,
  398. .driver = {
  399. .name = "axp20x-gpio",
  400. .of_match_table = axp20x_pctl_match,
  401. },
  402. };
  403. module_platform_driver(axp20x_pctl_driver);
  404. MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
  405. MODULE_AUTHOR("Quentin Schulz <quentin.schulz@free-electrons.com>");
  406. MODULE_DESCRIPTION("AXP20x PMIC pinctrl and GPIO driver");
  407. MODULE_LICENSE("GPL");