intel_pmc_ipc.c 24 KB

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  1. /*
  2. * intel_pmc_ipc.c: Driver for the Intel PMC IPC mechanism
  3. *
  4. * (C) Copyright 2014-2015 Intel Corporation
  5. *
  6. * This driver is based on Intel SCU IPC driver(intel_scu_opc.c) by
  7. * Sreedhara DS <sreedhara.ds@intel.com>
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License
  11. * as published by the Free Software Foundation; version 2
  12. * of the License.
  13. *
  14. * PMC running in ARC processor communicates with other entity running in IA
  15. * core through IPC mechanism which in turn messaging between IA core ad PMC.
  16. */
  17. #include <linux/module.h>
  18. #include <linux/delay.h>
  19. #include <linux/errno.h>
  20. #include <linux/init.h>
  21. #include <linux/device.h>
  22. #include <linux/pm.h>
  23. #include <linux/pci.h>
  24. #include <linux/platform_device.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/pm_qos.h>
  27. #include <linux/kernel.h>
  28. #include <linux/bitops.h>
  29. #include <linux/sched.h>
  30. #include <linux/atomic.h>
  31. #include <linux/notifier.h>
  32. #include <linux/suspend.h>
  33. #include <linux/acpi.h>
  34. #include <linux/io-64-nonatomic-lo-hi.h>
  35. #include <linux/spinlock.h>
  36. #include <asm/intel_pmc_ipc.h>
  37. #include <linux/platform_data/itco_wdt.h>
  38. /*
  39. * IPC registers
  40. * The IA write to IPC_CMD command register triggers an interrupt to the ARC,
  41. * The ARC handles the interrupt and services it, writing optional data to
  42. * the IPC1 registers, updates the IPC_STS response register with the status.
  43. */
  44. #define IPC_CMD 0x0
  45. #define IPC_CMD_MSI 0x100
  46. #define IPC_CMD_SIZE 16
  47. #define IPC_CMD_SUBCMD 12
  48. #define IPC_STATUS 0x04
  49. #define IPC_STATUS_IRQ 0x4
  50. #define IPC_STATUS_ERR 0x2
  51. #define IPC_STATUS_BUSY 0x1
  52. #define IPC_SPTR 0x08
  53. #define IPC_DPTR 0x0C
  54. #define IPC_WRITE_BUFFER 0x80
  55. #define IPC_READ_BUFFER 0x90
  56. /* Residency with clock rate at 19.2MHz to usecs */
  57. #define S0IX_RESIDENCY_IN_USECS(d, s) \
  58. ({ \
  59. u64 result = 10ull * ((d) + (s)); \
  60. do_div(result, 192); \
  61. result; \
  62. })
  63. /*
  64. * 16-byte buffer for sending data associated with IPC command.
  65. */
  66. #define IPC_DATA_BUFFER_SIZE 16
  67. #define IPC_LOOP_CNT 3000000
  68. #define IPC_MAX_SEC 3
  69. #define IPC_TRIGGER_MODE_IRQ true
  70. /* exported resources from IFWI */
  71. #define PLAT_RESOURCE_IPC_INDEX 0
  72. #define PLAT_RESOURCE_IPC_SIZE 0x1000
  73. #define PLAT_RESOURCE_GCR_OFFSET 0x1000
  74. #define PLAT_RESOURCE_GCR_SIZE 0x1000
  75. #define PLAT_RESOURCE_BIOS_DATA_INDEX 1
  76. #define PLAT_RESOURCE_BIOS_IFACE_INDEX 2
  77. #define PLAT_RESOURCE_TELEM_SSRAM_INDEX 3
  78. #define PLAT_RESOURCE_ISP_DATA_INDEX 4
  79. #define PLAT_RESOURCE_ISP_IFACE_INDEX 5
  80. #define PLAT_RESOURCE_GTD_DATA_INDEX 6
  81. #define PLAT_RESOURCE_GTD_IFACE_INDEX 7
  82. #define PLAT_RESOURCE_ACPI_IO_INDEX 0
  83. /*
  84. * BIOS does not create an ACPI device for each PMC function,
  85. * but exports multiple resources from one ACPI device(IPC) for
  86. * multiple functions. This driver is responsible to create a
  87. * platform device and to export resources for those functions.
  88. */
  89. #define TCO_DEVICE_NAME "iTCO_wdt"
  90. #define SMI_EN_OFFSET 0x40
  91. #define SMI_EN_SIZE 4
  92. #define TCO_BASE_OFFSET 0x60
  93. #define TCO_REGS_SIZE 16
  94. #define PUNIT_DEVICE_NAME "intel_punit_ipc"
  95. #define TELEMETRY_DEVICE_NAME "intel_telemetry"
  96. #define TELEM_SSRAM_SIZE 240
  97. #define TELEM_PMC_SSRAM_OFFSET 0x1B00
  98. #define TELEM_PUNIT_SSRAM_OFFSET 0x1A00
  99. #define TCO_PMC_OFFSET 0x8
  100. #define TCO_PMC_SIZE 0x4
  101. /* PMC register bit definitions */
  102. /* PMC_CFG_REG bit masks */
  103. #define PMC_CFG_NO_REBOOT_MASK (1 << 4)
  104. #define PMC_CFG_NO_REBOOT_EN (1 << 4)
  105. #define PMC_CFG_NO_REBOOT_DIS (0 << 4)
  106. static struct intel_pmc_ipc_dev {
  107. struct device *dev;
  108. void __iomem *ipc_base;
  109. bool irq_mode;
  110. int irq;
  111. int cmd;
  112. struct completion cmd_complete;
  113. /* The following PMC BARs share the same ACPI device with the IPC */
  114. resource_size_t acpi_io_base;
  115. int acpi_io_size;
  116. struct platform_device *tco_dev;
  117. /* gcr */
  118. void __iomem *gcr_mem_base;
  119. bool has_gcr_regs;
  120. spinlock_t gcr_lock;
  121. /* punit */
  122. struct platform_device *punit_dev;
  123. /* Telemetry */
  124. resource_size_t telem_pmc_ssram_base;
  125. resource_size_t telem_punit_ssram_base;
  126. int telem_pmc_ssram_size;
  127. int telem_punit_ssram_size;
  128. u8 telem_res_inval;
  129. struct platform_device *telemetry_dev;
  130. } ipcdev;
  131. static char *ipc_err_sources[] = {
  132. [IPC_ERR_NONE] =
  133. "no error",
  134. [IPC_ERR_CMD_NOT_SUPPORTED] =
  135. "command not supported",
  136. [IPC_ERR_CMD_NOT_SERVICED] =
  137. "command not serviced",
  138. [IPC_ERR_UNABLE_TO_SERVICE] =
  139. "unable to service",
  140. [IPC_ERR_CMD_INVALID] =
  141. "command invalid",
  142. [IPC_ERR_CMD_FAILED] =
  143. "command failed",
  144. [IPC_ERR_EMSECURITY] =
  145. "Invalid Battery",
  146. [IPC_ERR_UNSIGNEDKERNEL] =
  147. "Unsigned kernel",
  148. };
  149. /* Prevent concurrent calls to the PMC */
  150. static DEFINE_MUTEX(ipclock);
  151. static inline void ipc_send_command(u32 cmd)
  152. {
  153. ipcdev.cmd = cmd;
  154. if (ipcdev.irq_mode) {
  155. reinit_completion(&ipcdev.cmd_complete);
  156. cmd |= IPC_CMD_MSI;
  157. }
  158. writel(cmd, ipcdev.ipc_base + IPC_CMD);
  159. }
  160. static inline u32 ipc_read_status(void)
  161. {
  162. return readl(ipcdev.ipc_base + IPC_STATUS);
  163. }
  164. static inline void ipc_data_writel(u32 data, u32 offset)
  165. {
  166. writel(data, ipcdev.ipc_base + IPC_WRITE_BUFFER + offset);
  167. }
  168. static inline u8 __maybe_unused ipc_data_readb(u32 offset)
  169. {
  170. return readb(ipcdev.ipc_base + IPC_READ_BUFFER + offset);
  171. }
  172. static inline u32 ipc_data_readl(u32 offset)
  173. {
  174. return readl(ipcdev.ipc_base + IPC_READ_BUFFER + offset);
  175. }
  176. static inline u64 gcr_data_readq(u32 offset)
  177. {
  178. return readq(ipcdev.gcr_mem_base + offset);
  179. }
  180. static inline int is_gcr_valid(u32 offset)
  181. {
  182. if (!ipcdev.has_gcr_regs)
  183. return -EACCES;
  184. if (offset > PLAT_RESOURCE_GCR_SIZE)
  185. return -EINVAL;
  186. return 0;
  187. }
  188. /**
  189. * intel_pmc_gcr_read() - Read a 32-bit PMC GCR register
  190. * @offset: offset of GCR register from GCR address base
  191. * @data: data pointer for storing the register output
  192. *
  193. * Reads the 32-bit PMC GCR register at given offset.
  194. *
  195. * Return: negative value on error or 0 on success.
  196. */
  197. int intel_pmc_gcr_read(u32 offset, u32 *data)
  198. {
  199. int ret;
  200. spin_lock(&ipcdev.gcr_lock);
  201. ret = is_gcr_valid(offset);
  202. if (ret < 0) {
  203. spin_unlock(&ipcdev.gcr_lock);
  204. return ret;
  205. }
  206. *data = readl(ipcdev.gcr_mem_base + offset);
  207. spin_unlock(&ipcdev.gcr_lock);
  208. return 0;
  209. }
  210. EXPORT_SYMBOL_GPL(intel_pmc_gcr_read);
  211. /**
  212. * intel_pmc_gcr_read64() - Read a 64-bit PMC GCR register
  213. * @offset: offset of GCR register from GCR address base
  214. * @data: data pointer for storing the register output
  215. *
  216. * Reads the 64-bit PMC GCR register at given offset.
  217. *
  218. * Return: negative value on error or 0 on success.
  219. */
  220. int intel_pmc_gcr_read64(u32 offset, u64 *data)
  221. {
  222. int ret;
  223. spin_lock(&ipcdev.gcr_lock);
  224. ret = is_gcr_valid(offset);
  225. if (ret < 0) {
  226. spin_unlock(&ipcdev.gcr_lock);
  227. return ret;
  228. }
  229. *data = readq(ipcdev.gcr_mem_base + offset);
  230. spin_unlock(&ipcdev.gcr_lock);
  231. return 0;
  232. }
  233. EXPORT_SYMBOL_GPL(intel_pmc_gcr_read64);
  234. /**
  235. * intel_pmc_gcr_write() - Write PMC GCR register
  236. * @offset: offset of GCR register from GCR address base
  237. * @data: register update value
  238. *
  239. * Writes the PMC GCR register of given offset with given
  240. * value.
  241. *
  242. * Return: negative value on error or 0 on success.
  243. */
  244. int intel_pmc_gcr_write(u32 offset, u32 data)
  245. {
  246. int ret;
  247. spin_lock(&ipcdev.gcr_lock);
  248. ret = is_gcr_valid(offset);
  249. if (ret < 0) {
  250. spin_unlock(&ipcdev.gcr_lock);
  251. return ret;
  252. }
  253. writel(data, ipcdev.gcr_mem_base + offset);
  254. spin_unlock(&ipcdev.gcr_lock);
  255. return 0;
  256. }
  257. EXPORT_SYMBOL_GPL(intel_pmc_gcr_write);
  258. /**
  259. * intel_pmc_gcr_update() - Update PMC GCR register bits
  260. * @offset: offset of GCR register from GCR address base
  261. * @mask: bit mask for update operation
  262. * @val: update value
  263. *
  264. * Updates the bits of given GCR register as specified by
  265. * @mask and @val.
  266. *
  267. * Return: negative value on error or 0 on success.
  268. */
  269. int intel_pmc_gcr_update(u32 offset, u32 mask, u32 val)
  270. {
  271. u32 new_val;
  272. int ret = 0;
  273. spin_lock(&ipcdev.gcr_lock);
  274. ret = is_gcr_valid(offset);
  275. if (ret < 0)
  276. goto gcr_ipc_unlock;
  277. new_val = readl(ipcdev.gcr_mem_base + offset);
  278. new_val &= ~mask;
  279. new_val |= val & mask;
  280. writel(new_val, ipcdev.gcr_mem_base + offset);
  281. new_val = readl(ipcdev.gcr_mem_base + offset);
  282. /* check whether the bit update is successful */
  283. if ((new_val & mask) != (val & mask)) {
  284. ret = -EIO;
  285. goto gcr_ipc_unlock;
  286. }
  287. gcr_ipc_unlock:
  288. spin_unlock(&ipcdev.gcr_lock);
  289. return ret;
  290. }
  291. EXPORT_SYMBOL_GPL(intel_pmc_gcr_update);
  292. static int update_no_reboot_bit(void *priv, bool set)
  293. {
  294. u32 value = set ? PMC_CFG_NO_REBOOT_EN : PMC_CFG_NO_REBOOT_DIS;
  295. return intel_pmc_gcr_update(PMC_GCR_PMC_CFG_REG,
  296. PMC_CFG_NO_REBOOT_MASK, value);
  297. }
  298. static int intel_pmc_ipc_check_status(void)
  299. {
  300. int status;
  301. int ret = 0;
  302. if (ipcdev.irq_mode) {
  303. if (0 == wait_for_completion_timeout(
  304. &ipcdev.cmd_complete, IPC_MAX_SEC * HZ))
  305. ret = -ETIMEDOUT;
  306. } else {
  307. int loop_count = IPC_LOOP_CNT;
  308. while ((ipc_read_status() & IPC_STATUS_BUSY) && --loop_count)
  309. udelay(1);
  310. if (loop_count == 0)
  311. ret = -ETIMEDOUT;
  312. }
  313. status = ipc_read_status();
  314. if (ret == -ETIMEDOUT) {
  315. dev_err(ipcdev.dev,
  316. "IPC timed out, TS=0x%x, CMD=0x%x\n",
  317. status, ipcdev.cmd);
  318. return ret;
  319. }
  320. if (status & IPC_STATUS_ERR) {
  321. int i;
  322. ret = -EIO;
  323. i = (status >> IPC_CMD_SIZE) & 0xFF;
  324. if (i < ARRAY_SIZE(ipc_err_sources))
  325. dev_err(ipcdev.dev,
  326. "IPC failed: %s, STS=0x%x, CMD=0x%x\n",
  327. ipc_err_sources[i], status, ipcdev.cmd);
  328. else
  329. dev_err(ipcdev.dev,
  330. "IPC failed: unknown, STS=0x%x, CMD=0x%x\n",
  331. status, ipcdev.cmd);
  332. if ((i == IPC_ERR_UNSIGNEDKERNEL) || (i == IPC_ERR_EMSECURITY))
  333. ret = -EACCES;
  334. }
  335. return ret;
  336. }
  337. /**
  338. * intel_pmc_ipc_simple_command() - Simple IPC command
  339. * @cmd: IPC command code.
  340. * @sub: IPC command sub type.
  341. *
  342. * Send a simple IPC command to PMC when don't need to specify
  343. * input/output data and source/dest pointers.
  344. *
  345. * Return: an IPC error code or 0 on success.
  346. */
  347. int intel_pmc_ipc_simple_command(int cmd, int sub)
  348. {
  349. int ret;
  350. mutex_lock(&ipclock);
  351. if (ipcdev.dev == NULL) {
  352. mutex_unlock(&ipclock);
  353. return -ENODEV;
  354. }
  355. ipc_send_command(sub << IPC_CMD_SUBCMD | cmd);
  356. ret = intel_pmc_ipc_check_status();
  357. mutex_unlock(&ipclock);
  358. return ret;
  359. }
  360. EXPORT_SYMBOL_GPL(intel_pmc_ipc_simple_command);
  361. /**
  362. * intel_pmc_ipc_raw_cmd() - IPC command with data and pointers
  363. * @cmd: IPC command code.
  364. * @sub: IPC command sub type.
  365. * @in: input data of this IPC command.
  366. * @inlen: input data length in bytes.
  367. * @out: output data of this IPC command.
  368. * @outlen: output data length in dwords.
  369. * @sptr: data writing to SPTR register.
  370. * @dptr: data writing to DPTR register.
  371. *
  372. * Send an IPC command to PMC with input/output data and source/dest pointers.
  373. *
  374. * Return: an IPC error code or 0 on success.
  375. */
  376. int intel_pmc_ipc_raw_cmd(u32 cmd, u32 sub, u8 *in, u32 inlen, u32 *out,
  377. u32 outlen, u32 dptr, u32 sptr)
  378. {
  379. u32 wbuf[4] = { 0 };
  380. int ret;
  381. int i;
  382. if (inlen > IPC_DATA_BUFFER_SIZE || outlen > IPC_DATA_BUFFER_SIZE / 4)
  383. return -EINVAL;
  384. mutex_lock(&ipclock);
  385. if (ipcdev.dev == NULL) {
  386. mutex_unlock(&ipclock);
  387. return -ENODEV;
  388. }
  389. memcpy(wbuf, in, inlen);
  390. writel(dptr, ipcdev.ipc_base + IPC_DPTR);
  391. writel(sptr, ipcdev.ipc_base + IPC_SPTR);
  392. /* The input data register is 32bit register and inlen is in Byte */
  393. for (i = 0; i < ((inlen + 3) / 4); i++)
  394. ipc_data_writel(wbuf[i], 4 * i);
  395. ipc_send_command((inlen << IPC_CMD_SIZE) |
  396. (sub << IPC_CMD_SUBCMD) | cmd);
  397. ret = intel_pmc_ipc_check_status();
  398. if (!ret) {
  399. /* out is read from 32bit register and outlen is in 32bit */
  400. for (i = 0; i < outlen; i++)
  401. *out++ = ipc_data_readl(4 * i);
  402. }
  403. mutex_unlock(&ipclock);
  404. return ret;
  405. }
  406. EXPORT_SYMBOL_GPL(intel_pmc_ipc_raw_cmd);
  407. /**
  408. * intel_pmc_ipc_command() - IPC command with input/output data
  409. * @cmd: IPC command code.
  410. * @sub: IPC command sub type.
  411. * @in: input data of this IPC command.
  412. * @inlen: input data length in bytes.
  413. * @out: output data of this IPC command.
  414. * @outlen: output data length in dwords.
  415. *
  416. * Send an IPC command to PMC with input/output data.
  417. *
  418. * Return: an IPC error code or 0 on success.
  419. */
  420. int intel_pmc_ipc_command(u32 cmd, u32 sub, u8 *in, u32 inlen,
  421. u32 *out, u32 outlen)
  422. {
  423. return intel_pmc_ipc_raw_cmd(cmd, sub, in, inlen, out, outlen, 0, 0);
  424. }
  425. EXPORT_SYMBOL_GPL(intel_pmc_ipc_command);
  426. static irqreturn_t ioc(int irq, void *dev_id)
  427. {
  428. int status;
  429. if (ipcdev.irq_mode) {
  430. status = ipc_read_status();
  431. writel(status | IPC_STATUS_IRQ, ipcdev.ipc_base + IPC_STATUS);
  432. }
  433. complete(&ipcdev.cmd_complete);
  434. return IRQ_HANDLED;
  435. }
  436. static int ipc_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  437. {
  438. struct intel_pmc_ipc_dev *pmc = &ipcdev;
  439. int ret;
  440. /* Only one PMC is supported */
  441. if (pmc->dev)
  442. return -EBUSY;
  443. pmc->irq_mode = IPC_TRIGGER_MODE_IRQ;
  444. spin_lock_init(&ipcdev.gcr_lock);
  445. ret = pcim_enable_device(pdev);
  446. if (ret)
  447. return ret;
  448. ret = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev));
  449. if (ret)
  450. return ret;
  451. init_completion(&pmc->cmd_complete);
  452. pmc->ipc_base = pcim_iomap_table(pdev)[0];
  453. ret = devm_request_irq(&pdev->dev, pdev->irq, ioc, 0, "intel_pmc_ipc",
  454. pmc);
  455. if (ret) {
  456. dev_err(&pdev->dev, "Failed to request irq\n");
  457. return ret;
  458. }
  459. pmc->dev = &pdev->dev;
  460. pci_set_drvdata(pdev, pmc);
  461. return 0;
  462. }
  463. static const struct pci_device_id ipc_pci_ids[] = {
  464. {PCI_VDEVICE(INTEL, 0x0a94), 0},
  465. {PCI_VDEVICE(INTEL, 0x1a94), 0},
  466. {PCI_VDEVICE(INTEL, 0x5a94), 0},
  467. { 0,}
  468. };
  469. MODULE_DEVICE_TABLE(pci, ipc_pci_ids);
  470. static struct pci_driver ipc_pci_driver = {
  471. .name = "intel_pmc_ipc",
  472. .id_table = ipc_pci_ids,
  473. .probe = ipc_pci_probe,
  474. };
  475. static ssize_t intel_pmc_ipc_simple_cmd_store(struct device *dev,
  476. struct device_attribute *attr,
  477. const char *buf, size_t count)
  478. {
  479. int subcmd;
  480. int cmd;
  481. int ret;
  482. ret = sscanf(buf, "%d %d", &cmd, &subcmd);
  483. if (ret != 2) {
  484. dev_err(dev, "Error args\n");
  485. return -EINVAL;
  486. }
  487. ret = intel_pmc_ipc_simple_command(cmd, subcmd);
  488. if (ret) {
  489. dev_err(dev, "command %d error with %d\n", cmd, ret);
  490. return ret;
  491. }
  492. return (ssize_t)count;
  493. }
  494. static ssize_t intel_pmc_ipc_northpeak_store(struct device *dev,
  495. struct device_attribute *attr,
  496. const char *buf, size_t count)
  497. {
  498. unsigned long val;
  499. int subcmd;
  500. int ret;
  501. if (kstrtoul(buf, 0, &val))
  502. return -EINVAL;
  503. if (val)
  504. subcmd = 1;
  505. else
  506. subcmd = 0;
  507. ret = intel_pmc_ipc_simple_command(PMC_IPC_NORTHPEAK_CTRL, subcmd);
  508. if (ret) {
  509. dev_err(dev, "command north %d error with %d\n", subcmd, ret);
  510. return ret;
  511. }
  512. return (ssize_t)count;
  513. }
  514. static DEVICE_ATTR(simplecmd, S_IWUSR,
  515. NULL, intel_pmc_ipc_simple_cmd_store);
  516. static DEVICE_ATTR(northpeak, S_IWUSR,
  517. NULL, intel_pmc_ipc_northpeak_store);
  518. static struct attribute *intel_ipc_attrs[] = {
  519. &dev_attr_northpeak.attr,
  520. &dev_attr_simplecmd.attr,
  521. NULL
  522. };
  523. static const struct attribute_group intel_ipc_group = {
  524. .attrs = intel_ipc_attrs,
  525. };
  526. static struct resource punit_res_array[] = {
  527. /* Punit BIOS */
  528. {
  529. .flags = IORESOURCE_MEM,
  530. },
  531. {
  532. .flags = IORESOURCE_MEM,
  533. },
  534. /* Punit ISP */
  535. {
  536. .flags = IORESOURCE_MEM,
  537. },
  538. {
  539. .flags = IORESOURCE_MEM,
  540. },
  541. /* Punit GTD */
  542. {
  543. .flags = IORESOURCE_MEM,
  544. },
  545. {
  546. .flags = IORESOURCE_MEM,
  547. },
  548. };
  549. #define TCO_RESOURCE_ACPI_IO 0
  550. #define TCO_RESOURCE_SMI_EN_IO 1
  551. #define TCO_RESOURCE_GCR_MEM 2
  552. static struct resource tco_res[] = {
  553. /* ACPI - TCO */
  554. {
  555. .flags = IORESOURCE_IO,
  556. },
  557. /* ACPI - SMI */
  558. {
  559. .flags = IORESOURCE_IO,
  560. },
  561. };
  562. static struct itco_wdt_platform_data tco_info = {
  563. .name = "Apollo Lake SoC",
  564. .version = 5,
  565. .no_reboot_priv = &ipcdev,
  566. .update_no_reboot_bit = update_no_reboot_bit,
  567. };
  568. #define TELEMETRY_RESOURCE_PUNIT_SSRAM 0
  569. #define TELEMETRY_RESOURCE_PMC_SSRAM 1
  570. static struct resource telemetry_res[] = {
  571. /*Telemetry*/
  572. {
  573. .flags = IORESOURCE_MEM,
  574. },
  575. {
  576. .flags = IORESOURCE_MEM,
  577. },
  578. };
  579. static int ipc_create_punit_device(void)
  580. {
  581. struct platform_device *pdev;
  582. const struct platform_device_info pdevinfo = {
  583. .parent = ipcdev.dev,
  584. .name = PUNIT_DEVICE_NAME,
  585. .id = -1,
  586. .res = punit_res_array,
  587. .num_res = ARRAY_SIZE(punit_res_array),
  588. };
  589. pdev = platform_device_register_full(&pdevinfo);
  590. if (IS_ERR(pdev))
  591. return PTR_ERR(pdev);
  592. ipcdev.punit_dev = pdev;
  593. return 0;
  594. }
  595. static int ipc_create_tco_device(void)
  596. {
  597. struct platform_device *pdev;
  598. struct resource *res;
  599. const struct platform_device_info pdevinfo = {
  600. .parent = ipcdev.dev,
  601. .name = TCO_DEVICE_NAME,
  602. .id = -1,
  603. .res = tco_res,
  604. .num_res = ARRAY_SIZE(tco_res),
  605. .data = &tco_info,
  606. .size_data = sizeof(tco_info),
  607. };
  608. res = tco_res + TCO_RESOURCE_ACPI_IO;
  609. res->start = ipcdev.acpi_io_base + TCO_BASE_OFFSET;
  610. res->end = res->start + TCO_REGS_SIZE - 1;
  611. res = tco_res + TCO_RESOURCE_SMI_EN_IO;
  612. res->start = ipcdev.acpi_io_base + SMI_EN_OFFSET;
  613. res->end = res->start + SMI_EN_SIZE - 1;
  614. pdev = platform_device_register_full(&pdevinfo);
  615. if (IS_ERR(pdev))
  616. return PTR_ERR(pdev);
  617. ipcdev.tco_dev = pdev;
  618. return 0;
  619. }
  620. static int ipc_create_telemetry_device(void)
  621. {
  622. struct platform_device *pdev;
  623. struct resource *res;
  624. const struct platform_device_info pdevinfo = {
  625. .parent = ipcdev.dev,
  626. .name = TELEMETRY_DEVICE_NAME,
  627. .id = -1,
  628. .res = telemetry_res,
  629. .num_res = ARRAY_SIZE(telemetry_res),
  630. };
  631. res = telemetry_res + TELEMETRY_RESOURCE_PUNIT_SSRAM;
  632. res->start = ipcdev.telem_punit_ssram_base;
  633. res->end = res->start + ipcdev.telem_punit_ssram_size - 1;
  634. res = telemetry_res + TELEMETRY_RESOURCE_PMC_SSRAM;
  635. res->start = ipcdev.telem_pmc_ssram_base;
  636. res->end = res->start + ipcdev.telem_pmc_ssram_size - 1;
  637. pdev = platform_device_register_full(&pdevinfo);
  638. if (IS_ERR(pdev))
  639. return PTR_ERR(pdev);
  640. ipcdev.telemetry_dev = pdev;
  641. return 0;
  642. }
  643. static int ipc_create_pmc_devices(void)
  644. {
  645. int ret;
  646. /* If we have ACPI based watchdog use that instead */
  647. if (!acpi_has_watchdog()) {
  648. ret = ipc_create_tco_device();
  649. if (ret) {
  650. dev_err(ipcdev.dev, "Failed to add tco platform device\n");
  651. return ret;
  652. }
  653. }
  654. ret = ipc_create_punit_device();
  655. if (ret) {
  656. dev_err(ipcdev.dev, "Failed to add punit platform device\n");
  657. platform_device_unregister(ipcdev.tco_dev);
  658. return ret;
  659. }
  660. if (!ipcdev.telem_res_inval) {
  661. ret = ipc_create_telemetry_device();
  662. if (ret) {
  663. dev_warn(ipcdev.dev,
  664. "Failed to add telemetry platform device\n");
  665. platform_device_unregister(ipcdev.punit_dev);
  666. platform_device_unregister(ipcdev.tco_dev);
  667. }
  668. }
  669. return ret;
  670. }
  671. static int ipc_plat_get_res(struct platform_device *pdev)
  672. {
  673. struct resource *res, *punit_res;
  674. void __iomem *addr;
  675. int size;
  676. res = platform_get_resource(pdev, IORESOURCE_IO,
  677. PLAT_RESOURCE_ACPI_IO_INDEX);
  678. if (!res) {
  679. dev_err(&pdev->dev, "Failed to get io resource\n");
  680. return -ENXIO;
  681. }
  682. size = resource_size(res);
  683. ipcdev.acpi_io_base = res->start;
  684. ipcdev.acpi_io_size = size;
  685. dev_info(&pdev->dev, "io res: %pR\n", res);
  686. punit_res = punit_res_array;
  687. /* This is index 0 to cover BIOS data register */
  688. res = platform_get_resource(pdev, IORESOURCE_MEM,
  689. PLAT_RESOURCE_BIOS_DATA_INDEX);
  690. if (!res) {
  691. dev_err(&pdev->dev, "Failed to get res of punit BIOS data\n");
  692. return -ENXIO;
  693. }
  694. *punit_res = *res;
  695. dev_info(&pdev->dev, "punit BIOS data res: %pR\n", res);
  696. /* This is index 1 to cover BIOS interface register */
  697. res = platform_get_resource(pdev, IORESOURCE_MEM,
  698. PLAT_RESOURCE_BIOS_IFACE_INDEX);
  699. if (!res) {
  700. dev_err(&pdev->dev, "Failed to get res of punit BIOS iface\n");
  701. return -ENXIO;
  702. }
  703. *++punit_res = *res;
  704. dev_info(&pdev->dev, "punit BIOS interface res: %pR\n", res);
  705. /* This is index 2 to cover ISP data register, optional */
  706. res = platform_get_resource(pdev, IORESOURCE_MEM,
  707. PLAT_RESOURCE_ISP_DATA_INDEX);
  708. ++punit_res;
  709. if (res) {
  710. *punit_res = *res;
  711. dev_info(&pdev->dev, "punit ISP data res: %pR\n", res);
  712. }
  713. /* This is index 3 to cover ISP interface register, optional */
  714. res = platform_get_resource(pdev, IORESOURCE_MEM,
  715. PLAT_RESOURCE_ISP_IFACE_INDEX);
  716. ++punit_res;
  717. if (res) {
  718. *punit_res = *res;
  719. dev_info(&pdev->dev, "punit ISP interface res: %pR\n", res);
  720. }
  721. /* This is index 4 to cover GTD data register, optional */
  722. res = platform_get_resource(pdev, IORESOURCE_MEM,
  723. PLAT_RESOURCE_GTD_DATA_INDEX);
  724. ++punit_res;
  725. if (res) {
  726. *punit_res = *res;
  727. dev_info(&pdev->dev, "punit GTD data res: %pR\n", res);
  728. }
  729. /* This is index 5 to cover GTD interface register, optional */
  730. res = platform_get_resource(pdev, IORESOURCE_MEM,
  731. PLAT_RESOURCE_GTD_IFACE_INDEX);
  732. ++punit_res;
  733. if (res) {
  734. *punit_res = *res;
  735. dev_info(&pdev->dev, "punit GTD interface res: %pR\n", res);
  736. }
  737. res = platform_get_resource(pdev, IORESOURCE_MEM,
  738. PLAT_RESOURCE_IPC_INDEX);
  739. if (!res) {
  740. dev_err(&pdev->dev, "Failed to get ipc resource\n");
  741. return -ENXIO;
  742. }
  743. size = PLAT_RESOURCE_IPC_SIZE + PLAT_RESOURCE_GCR_SIZE;
  744. res->end = res->start + size - 1;
  745. addr = devm_ioremap_resource(&pdev->dev, res);
  746. if (IS_ERR(addr))
  747. return PTR_ERR(addr);
  748. ipcdev.ipc_base = addr;
  749. ipcdev.gcr_mem_base = addr + PLAT_RESOURCE_GCR_OFFSET;
  750. dev_info(&pdev->dev, "ipc res: %pR\n", res);
  751. ipcdev.telem_res_inval = 0;
  752. res = platform_get_resource(pdev, IORESOURCE_MEM,
  753. PLAT_RESOURCE_TELEM_SSRAM_INDEX);
  754. if (!res) {
  755. dev_err(&pdev->dev, "Failed to get telemetry ssram resource\n");
  756. ipcdev.telem_res_inval = 1;
  757. } else {
  758. ipcdev.telem_punit_ssram_base = res->start +
  759. TELEM_PUNIT_SSRAM_OFFSET;
  760. ipcdev.telem_punit_ssram_size = TELEM_SSRAM_SIZE;
  761. ipcdev.telem_pmc_ssram_base = res->start +
  762. TELEM_PMC_SSRAM_OFFSET;
  763. ipcdev.telem_pmc_ssram_size = TELEM_SSRAM_SIZE;
  764. dev_info(&pdev->dev, "telemetry ssram res: %pR\n", res);
  765. }
  766. return 0;
  767. }
  768. /**
  769. * intel_pmc_s0ix_counter_read() - Read S0ix residency.
  770. * @data: Out param that contains current S0ix residency count.
  771. *
  772. * Return: an error code or 0 on success.
  773. */
  774. int intel_pmc_s0ix_counter_read(u64 *data)
  775. {
  776. u64 deep, shlw;
  777. if (!ipcdev.has_gcr_regs)
  778. return -EACCES;
  779. deep = gcr_data_readq(PMC_GCR_TELEM_DEEP_S0IX_REG);
  780. shlw = gcr_data_readq(PMC_GCR_TELEM_SHLW_S0IX_REG);
  781. *data = S0IX_RESIDENCY_IN_USECS(deep, shlw);
  782. return 0;
  783. }
  784. EXPORT_SYMBOL_GPL(intel_pmc_s0ix_counter_read);
  785. #ifdef CONFIG_ACPI
  786. static const struct acpi_device_id ipc_acpi_ids[] = {
  787. { "INT34D2", 0},
  788. { }
  789. };
  790. MODULE_DEVICE_TABLE(acpi, ipc_acpi_ids);
  791. #endif
  792. static int ipc_plat_probe(struct platform_device *pdev)
  793. {
  794. int ret;
  795. ipcdev.dev = &pdev->dev;
  796. ipcdev.irq_mode = IPC_TRIGGER_MODE_IRQ;
  797. init_completion(&ipcdev.cmd_complete);
  798. spin_lock_init(&ipcdev.gcr_lock);
  799. ipcdev.irq = platform_get_irq(pdev, 0);
  800. if (ipcdev.irq < 0) {
  801. dev_err(&pdev->dev, "Failed to get irq\n");
  802. return -EINVAL;
  803. }
  804. ret = ipc_plat_get_res(pdev);
  805. if (ret) {
  806. dev_err(&pdev->dev, "Failed to request resource\n");
  807. return ret;
  808. }
  809. ret = ipc_create_pmc_devices();
  810. if (ret) {
  811. dev_err(&pdev->dev, "Failed to create pmc devices\n");
  812. return ret;
  813. }
  814. if (devm_request_irq(&pdev->dev, ipcdev.irq, ioc, IRQF_NO_SUSPEND,
  815. "intel_pmc_ipc", &ipcdev)) {
  816. dev_err(&pdev->dev, "Failed to request irq\n");
  817. ret = -EBUSY;
  818. goto err_irq;
  819. }
  820. ret = sysfs_create_group(&pdev->dev.kobj, &intel_ipc_group);
  821. if (ret) {
  822. dev_err(&pdev->dev, "Failed to create sysfs group %d\n",
  823. ret);
  824. goto err_sys;
  825. }
  826. ipcdev.has_gcr_regs = true;
  827. return 0;
  828. err_sys:
  829. devm_free_irq(&pdev->dev, ipcdev.irq, &ipcdev);
  830. err_irq:
  831. platform_device_unregister(ipcdev.tco_dev);
  832. platform_device_unregister(ipcdev.punit_dev);
  833. platform_device_unregister(ipcdev.telemetry_dev);
  834. return ret;
  835. }
  836. static int ipc_plat_remove(struct platform_device *pdev)
  837. {
  838. sysfs_remove_group(&pdev->dev.kobj, &intel_ipc_group);
  839. devm_free_irq(&pdev->dev, ipcdev.irq, &ipcdev);
  840. platform_device_unregister(ipcdev.tco_dev);
  841. platform_device_unregister(ipcdev.punit_dev);
  842. platform_device_unregister(ipcdev.telemetry_dev);
  843. ipcdev.dev = NULL;
  844. return 0;
  845. }
  846. static struct platform_driver ipc_plat_driver = {
  847. .remove = ipc_plat_remove,
  848. .probe = ipc_plat_probe,
  849. .driver = {
  850. .name = "pmc-ipc-plat",
  851. .acpi_match_table = ACPI_PTR(ipc_acpi_ids),
  852. },
  853. };
  854. static int __init intel_pmc_ipc_init(void)
  855. {
  856. int ret;
  857. ret = platform_driver_register(&ipc_plat_driver);
  858. if (ret) {
  859. pr_err("Failed to register PMC ipc platform driver\n");
  860. return ret;
  861. }
  862. ret = pci_register_driver(&ipc_pci_driver);
  863. if (ret) {
  864. pr_err("Failed to register PMC ipc pci driver\n");
  865. platform_driver_unregister(&ipc_plat_driver);
  866. return ret;
  867. }
  868. return ret;
  869. }
  870. static void __exit intel_pmc_ipc_exit(void)
  871. {
  872. pci_unregister_driver(&ipc_pci_driver);
  873. platform_driver_unregister(&ipc_plat_driver);
  874. }
  875. MODULE_AUTHOR("Zha Qipeng <qipeng.zha@intel.com>");
  876. MODULE_DESCRIPTION("Intel PMC IPC driver");
  877. MODULE_LICENSE("GPL");
  878. /* Some modules are dependent on this, so init earlier */
  879. fs_initcall(intel_pmc_ipc_init);
  880. module_exit(intel_pmc_ipc_exit);