pmc_atom.c 14 KB

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  1. /*
  2. * Intel Atom SOC Power Management Controller Driver
  3. * Copyright (c) 2014, Intel Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms and conditions of the GNU General Public License,
  7. * version 2, as published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. */
  15. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  16. #include <linux/debugfs.h>
  17. #include <linux/device.h>
  18. #include <linux/dmi.h>
  19. #include <linux/init.h>
  20. #include <linux/io.h>
  21. #include <linux/platform_data/x86/clk-pmc-atom.h>
  22. #include <linux/platform_data/x86/pmc_atom.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/pci.h>
  25. #include <linux/seq_file.h>
  26. struct pmc_bit_map {
  27. const char *name;
  28. u32 bit_mask;
  29. };
  30. struct pmc_reg_map {
  31. const struct pmc_bit_map *d3_sts_0;
  32. const struct pmc_bit_map *d3_sts_1;
  33. const struct pmc_bit_map *func_dis;
  34. const struct pmc_bit_map *func_dis_2;
  35. const struct pmc_bit_map *pss;
  36. };
  37. struct pmc_data {
  38. const struct pmc_reg_map *map;
  39. const struct pmc_clk *clks;
  40. };
  41. struct pmc_dev {
  42. u32 base_addr;
  43. void __iomem *regmap;
  44. const struct pmc_reg_map *map;
  45. #ifdef CONFIG_DEBUG_FS
  46. struct dentry *dbgfs_dir;
  47. #endif /* CONFIG_DEBUG_FS */
  48. bool init;
  49. };
  50. static struct pmc_dev pmc_device;
  51. static u32 acpi_base_addr;
  52. static const struct pmc_clk byt_clks[] = {
  53. {
  54. .name = "xtal",
  55. .freq = 25000000,
  56. .parent_name = NULL,
  57. },
  58. {
  59. .name = "pll",
  60. .freq = 19200000,
  61. .parent_name = "xtal",
  62. },
  63. {},
  64. };
  65. static const struct pmc_clk cht_clks[] = {
  66. {
  67. .name = "xtal",
  68. .freq = 19200000,
  69. .parent_name = NULL,
  70. },
  71. {},
  72. };
  73. static const struct pmc_bit_map d3_sts_0_map[] = {
  74. {"LPSS1_F0_DMA", BIT_LPSS1_F0_DMA},
  75. {"LPSS1_F1_PWM1", BIT_LPSS1_F1_PWM1},
  76. {"LPSS1_F2_PWM2", BIT_LPSS1_F2_PWM2},
  77. {"LPSS1_F3_HSUART1", BIT_LPSS1_F3_HSUART1},
  78. {"LPSS1_F4_HSUART2", BIT_LPSS1_F4_HSUART2},
  79. {"LPSS1_F5_SPI", BIT_LPSS1_F5_SPI},
  80. {"LPSS1_F6_Reserved", BIT_LPSS1_F6_XXX},
  81. {"LPSS1_F7_Reserved", BIT_LPSS1_F7_XXX},
  82. {"SCC_EMMC", BIT_SCC_EMMC},
  83. {"SCC_SDIO", BIT_SCC_SDIO},
  84. {"SCC_SDCARD", BIT_SCC_SDCARD},
  85. {"SCC_MIPI", BIT_SCC_MIPI},
  86. {"HDA", BIT_HDA},
  87. {"LPE", BIT_LPE},
  88. {"OTG", BIT_OTG},
  89. {"USH", BIT_USH},
  90. {"GBE", BIT_GBE},
  91. {"SATA", BIT_SATA},
  92. {"USB_EHCI", BIT_USB_EHCI},
  93. {"SEC", BIT_SEC},
  94. {"PCIE_PORT0", BIT_PCIE_PORT0},
  95. {"PCIE_PORT1", BIT_PCIE_PORT1},
  96. {"PCIE_PORT2", BIT_PCIE_PORT2},
  97. {"PCIE_PORT3", BIT_PCIE_PORT3},
  98. {"LPSS2_F0_DMA", BIT_LPSS2_F0_DMA},
  99. {"LPSS2_F1_I2C1", BIT_LPSS2_F1_I2C1},
  100. {"LPSS2_F2_I2C2", BIT_LPSS2_F2_I2C2},
  101. {"LPSS2_F3_I2C3", BIT_LPSS2_F3_I2C3},
  102. {"LPSS2_F3_I2C4", BIT_LPSS2_F4_I2C4},
  103. {"LPSS2_F5_I2C5", BIT_LPSS2_F5_I2C5},
  104. {"LPSS2_F6_I2C6", BIT_LPSS2_F6_I2C6},
  105. {"LPSS2_F7_I2C7", BIT_LPSS2_F7_I2C7},
  106. {},
  107. };
  108. static struct pmc_bit_map byt_d3_sts_1_map[] = {
  109. {"SMB", BIT_SMB},
  110. {"OTG_SS_PHY", BIT_OTG_SS_PHY},
  111. {"USH_SS_PHY", BIT_USH_SS_PHY},
  112. {"DFX", BIT_DFX},
  113. {},
  114. };
  115. static struct pmc_bit_map cht_d3_sts_1_map[] = {
  116. {"SMB", BIT_SMB},
  117. {"GMM", BIT_STS_GMM},
  118. {"ISH", BIT_STS_ISH},
  119. {},
  120. };
  121. static struct pmc_bit_map cht_func_dis_2_map[] = {
  122. {"SMB", BIT_SMB},
  123. {"GMM", BIT_FD_GMM},
  124. {"ISH", BIT_FD_ISH},
  125. {},
  126. };
  127. static const struct pmc_bit_map byt_pss_map[] = {
  128. {"GBE", PMC_PSS_BIT_GBE},
  129. {"SATA", PMC_PSS_BIT_SATA},
  130. {"HDA", PMC_PSS_BIT_HDA},
  131. {"SEC", PMC_PSS_BIT_SEC},
  132. {"PCIE", PMC_PSS_BIT_PCIE},
  133. {"LPSS", PMC_PSS_BIT_LPSS},
  134. {"LPE", PMC_PSS_BIT_LPE},
  135. {"DFX", PMC_PSS_BIT_DFX},
  136. {"USH_CTRL", PMC_PSS_BIT_USH_CTRL},
  137. {"USH_SUS", PMC_PSS_BIT_USH_SUS},
  138. {"USH_VCCS", PMC_PSS_BIT_USH_VCCS},
  139. {"USH_VCCA", PMC_PSS_BIT_USH_VCCA},
  140. {"OTG_CTRL", PMC_PSS_BIT_OTG_CTRL},
  141. {"OTG_VCCS", PMC_PSS_BIT_OTG_VCCS},
  142. {"OTG_VCCA_CLK", PMC_PSS_BIT_OTG_VCCA_CLK},
  143. {"OTG_VCCA", PMC_PSS_BIT_OTG_VCCA},
  144. {"USB", PMC_PSS_BIT_USB},
  145. {"USB_SUS", PMC_PSS_BIT_USB_SUS},
  146. {},
  147. };
  148. static const struct pmc_bit_map cht_pss_map[] = {
  149. {"SATA", PMC_PSS_BIT_SATA},
  150. {"HDA", PMC_PSS_BIT_HDA},
  151. {"SEC", PMC_PSS_BIT_SEC},
  152. {"PCIE", PMC_PSS_BIT_PCIE},
  153. {"LPSS", PMC_PSS_BIT_LPSS},
  154. {"LPE", PMC_PSS_BIT_LPE},
  155. {"UFS", PMC_PSS_BIT_CHT_UFS},
  156. {"UXD", PMC_PSS_BIT_CHT_UXD},
  157. {"UXD_FD", PMC_PSS_BIT_CHT_UXD_FD},
  158. {"UX_ENG", PMC_PSS_BIT_CHT_UX_ENG},
  159. {"USB_SUS", PMC_PSS_BIT_CHT_USB_SUS},
  160. {"GMM", PMC_PSS_BIT_CHT_GMM},
  161. {"ISH", PMC_PSS_BIT_CHT_ISH},
  162. {"DFX_MASTER", PMC_PSS_BIT_CHT_DFX_MASTER},
  163. {"DFX_CLUSTER1", PMC_PSS_BIT_CHT_DFX_CLUSTER1},
  164. {"DFX_CLUSTER2", PMC_PSS_BIT_CHT_DFX_CLUSTER2},
  165. {"DFX_CLUSTER3", PMC_PSS_BIT_CHT_DFX_CLUSTER3},
  166. {"DFX_CLUSTER4", PMC_PSS_BIT_CHT_DFX_CLUSTER4},
  167. {"DFX_CLUSTER5", PMC_PSS_BIT_CHT_DFX_CLUSTER5},
  168. {},
  169. };
  170. static const struct pmc_reg_map byt_reg_map = {
  171. .d3_sts_0 = d3_sts_0_map,
  172. .d3_sts_1 = byt_d3_sts_1_map,
  173. .func_dis = d3_sts_0_map,
  174. .func_dis_2 = byt_d3_sts_1_map,
  175. .pss = byt_pss_map,
  176. };
  177. static const struct pmc_reg_map cht_reg_map = {
  178. .d3_sts_0 = d3_sts_0_map,
  179. .d3_sts_1 = cht_d3_sts_1_map,
  180. .func_dis = d3_sts_0_map,
  181. .func_dis_2 = cht_func_dis_2_map,
  182. .pss = cht_pss_map,
  183. };
  184. static const struct pmc_data byt_data = {
  185. .map = &byt_reg_map,
  186. .clks = byt_clks,
  187. };
  188. static const struct pmc_data cht_data = {
  189. .map = &cht_reg_map,
  190. .clks = cht_clks,
  191. };
  192. static inline u32 pmc_reg_read(struct pmc_dev *pmc, int reg_offset)
  193. {
  194. return readl(pmc->regmap + reg_offset);
  195. }
  196. static inline void pmc_reg_write(struct pmc_dev *pmc, int reg_offset, u32 val)
  197. {
  198. writel(val, pmc->regmap + reg_offset);
  199. }
  200. int pmc_atom_read(int offset, u32 *value)
  201. {
  202. struct pmc_dev *pmc = &pmc_device;
  203. if (!pmc->init)
  204. return -ENODEV;
  205. *value = pmc_reg_read(pmc, offset);
  206. return 0;
  207. }
  208. EXPORT_SYMBOL_GPL(pmc_atom_read);
  209. int pmc_atom_write(int offset, u32 value)
  210. {
  211. struct pmc_dev *pmc = &pmc_device;
  212. if (!pmc->init)
  213. return -ENODEV;
  214. pmc_reg_write(pmc, offset, value);
  215. return 0;
  216. }
  217. EXPORT_SYMBOL_GPL(pmc_atom_write);
  218. static void pmc_power_off(void)
  219. {
  220. u16 pm1_cnt_port;
  221. u32 pm1_cnt_value;
  222. pr_info("Preparing to enter system sleep state S5\n");
  223. pm1_cnt_port = acpi_base_addr + PM1_CNT;
  224. pm1_cnt_value = inl(pm1_cnt_port);
  225. pm1_cnt_value &= SLEEP_TYPE_MASK;
  226. pm1_cnt_value |= SLEEP_TYPE_S5;
  227. pm1_cnt_value |= SLEEP_ENABLE;
  228. outl(pm1_cnt_value, pm1_cnt_port);
  229. }
  230. static void pmc_hw_reg_setup(struct pmc_dev *pmc)
  231. {
  232. /*
  233. * Disable PMC S0IX_WAKE_EN events coming from:
  234. * - LPC clock run
  235. * - GPIO_SUS ored dedicated IRQs
  236. * - GPIO_SCORE ored dedicated IRQs
  237. * - GPIO_SUS shared IRQ
  238. * - GPIO_SCORE shared IRQ
  239. */
  240. pmc_reg_write(pmc, PMC_S0IX_WAKE_EN, (u32)PMC_WAKE_EN_SETTING);
  241. }
  242. #ifdef CONFIG_DEBUG_FS
  243. static void pmc_dev_state_print(struct seq_file *s, int reg_index,
  244. u32 sts, const struct pmc_bit_map *sts_map,
  245. u32 fd, const struct pmc_bit_map *fd_map)
  246. {
  247. int offset = PMC_REG_BIT_WIDTH * reg_index;
  248. int index;
  249. for (index = 0; sts_map[index].name; index++) {
  250. seq_printf(s, "Dev: %-2d - %-32s\tState: %s [%s]\n",
  251. offset + index, sts_map[index].name,
  252. fd_map[index].bit_mask & fd ? "Disabled" : "Enabled ",
  253. sts_map[index].bit_mask & sts ? "D3" : "D0");
  254. }
  255. }
  256. static int pmc_dev_state_show(struct seq_file *s, void *unused)
  257. {
  258. struct pmc_dev *pmc = s->private;
  259. const struct pmc_reg_map *m = pmc->map;
  260. u32 func_dis, func_dis_2;
  261. u32 d3_sts_0, d3_sts_1;
  262. func_dis = pmc_reg_read(pmc, PMC_FUNC_DIS);
  263. func_dis_2 = pmc_reg_read(pmc, PMC_FUNC_DIS_2);
  264. d3_sts_0 = pmc_reg_read(pmc, PMC_D3_STS_0);
  265. d3_sts_1 = pmc_reg_read(pmc, PMC_D3_STS_1);
  266. /* Low part */
  267. pmc_dev_state_print(s, 0, d3_sts_0, m->d3_sts_0, func_dis, m->func_dis);
  268. /* High part */
  269. pmc_dev_state_print(s, 1, d3_sts_1, m->d3_sts_1, func_dis_2, m->func_dis_2);
  270. return 0;
  271. }
  272. DEFINE_SHOW_ATTRIBUTE(pmc_dev_state);
  273. static int pmc_pss_state_show(struct seq_file *s, void *unused)
  274. {
  275. struct pmc_dev *pmc = s->private;
  276. const struct pmc_bit_map *map = pmc->map->pss;
  277. u32 pss = pmc_reg_read(pmc, PMC_PSS);
  278. int index;
  279. for (index = 0; map[index].name; index++) {
  280. seq_printf(s, "Island: %-2d - %-32s\tState: %s\n",
  281. index, map[index].name,
  282. map[index].bit_mask & pss ? "Off" : "On");
  283. }
  284. return 0;
  285. }
  286. DEFINE_SHOW_ATTRIBUTE(pmc_pss_state);
  287. static int pmc_sleep_tmr_show(struct seq_file *s, void *unused)
  288. {
  289. struct pmc_dev *pmc = s->private;
  290. u64 s0ir_tmr, s0i1_tmr, s0i2_tmr, s0i3_tmr, s0_tmr;
  291. s0ir_tmr = (u64)pmc_reg_read(pmc, PMC_S0IR_TMR) << PMC_TMR_SHIFT;
  292. s0i1_tmr = (u64)pmc_reg_read(pmc, PMC_S0I1_TMR) << PMC_TMR_SHIFT;
  293. s0i2_tmr = (u64)pmc_reg_read(pmc, PMC_S0I2_TMR) << PMC_TMR_SHIFT;
  294. s0i3_tmr = (u64)pmc_reg_read(pmc, PMC_S0I3_TMR) << PMC_TMR_SHIFT;
  295. s0_tmr = (u64)pmc_reg_read(pmc, PMC_S0_TMR) << PMC_TMR_SHIFT;
  296. seq_printf(s, "S0IR Residency:\t%lldus\n", s0ir_tmr);
  297. seq_printf(s, "S0I1 Residency:\t%lldus\n", s0i1_tmr);
  298. seq_printf(s, "S0I2 Residency:\t%lldus\n", s0i2_tmr);
  299. seq_printf(s, "S0I3 Residency:\t%lldus\n", s0i3_tmr);
  300. seq_printf(s, "S0 Residency:\t%lldus\n", s0_tmr);
  301. return 0;
  302. }
  303. DEFINE_SHOW_ATTRIBUTE(pmc_sleep_tmr);
  304. static void pmc_dbgfs_unregister(struct pmc_dev *pmc)
  305. {
  306. debugfs_remove_recursive(pmc->dbgfs_dir);
  307. }
  308. static int pmc_dbgfs_register(struct pmc_dev *pmc)
  309. {
  310. struct dentry *dir, *f;
  311. dir = debugfs_create_dir("pmc_atom", NULL);
  312. if (!dir)
  313. return -ENOMEM;
  314. pmc->dbgfs_dir = dir;
  315. f = debugfs_create_file("dev_state", S_IFREG | S_IRUGO,
  316. dir, pmc, &pmc_dev_state_fops);
  317. if (!f)
  318. goto err;
  319. f = debugfs_create_file("pss_state", S_IFREG | S_IRUGO,
  320. dir, pmc, &pmc_pss_state_fops);
  321. if (!f)
  322. goto err;
  323. f = debugfs_create_file("sleep_state", S_IFREG | S_IRUGO,
  324. dir, pmc, &pmc_sleep_tmr_fops);
  325. if (!f)
  326. goto err;
  327. return 0;
  328. err:
  329. pmc_dbgfs_unregister(pmc);
  330. return -ENODEV;
  331. }
  332. #else
  333. static int pmc_dbgfs_register(struct pmc_dev *pmc)
  334. {
  335. return 0;
  336. }
  337. #endif /* CONFIG_DEBUG_FS */
  338. /*
  339. * Some systems need one or more of their pmc_plt_clks to be
  340. * marked as critical.
  341. */
  342. static const struct dmi_system_id critclk_systems[] = {
  343. {
  344. /* pmc_plt_clk0 is used for an external HSIC USB HUB */
  345. .ident = "MPL CEC1x",
  346. .matches = {
  347. DMI_MATCH(DMI_SYS_VENDOR, "MPL AG"),
  348. DMI_MATCH(DMI_PRODUCT_NAME, "CEC10 Family"),
  349. },
  350. },
  351. {
  352. /* pmc_plt_clk0 - 3 are used for the 4 ethernet controllers */
  353. .ident = "Lex 3I380D",
  354. .matches = {
  355. DMI_MATCH(DMI_SYS_VENDOR, "Lex BayTrail"),
  356. DMI_MATCH(DMI_PRODUCT_NAME, "3I380D"),
  357. },
  358. },
  359. {
  360. /* pmc_plt_clk* - are used for ethernet controllers */
  361. .ident = "Lex 2I385SW",
  362. .matches = {
  363. DMI_MATCH(DMI_SYS_VENDOR, "Lex BayTrail"),
  364. DMI_MATCH(DMI_PRODUCT_NAME, "2I385SW"),
  365. },
  366. },
  367. {
  368. /* pmc_plt_clk* - are used for ethernet controllers */
  369. .ident = "Beckhoff Baytrail",
  370. .matches = {
  371. DMI_MATCH(DMI_SYS_VENDOR, "Beckhoff Automation"),
  372. DMI_MATCH(DMI_PRODUCT_FAMILY, "CBxx63"),
  373. },
  374. },
  375. {
  376. .ident = "SIMATIC IPC227E",
  377. .matches = {
  378. DMI_MATCH(DMI_SYS_VENDOR, "SIEMENS AG"),
  379. DMI_MATCH(DMI_PRODUCT_VERSION, "6ES7647-8B"),
  380. },
  381. },
  382. {
  383. .ident = "CONNECT X300",
  384. .matches = {
  385. DMI_MATCH(DMI_SYS_VENDOR, "SIEMENS AG"),
  386. DMI_MATCH(DMI_PRODUCT_VERSION, "A5E45074588"),
  387. },
  388. },
  389. { /*sentinel*/ }
  390. };
  391. static int pmc_setup_clks(struct pci_dev *pdev, void __iomem *pmc_regmap,
  392. const struct pmc_data *pmc_data)
  393. {
  394. struct platform_device *clkdev;
  395. struct pmc_clk_data *clk_data;
  396. const struct dmi_system_id *d = dmi_first_match(critclk_systems);
  397. clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
  398. if (!clk_data)
  399. return -ENOMEM;
  400. clk_data->base = pmc_regmap; /* offset is added by client */
  401. clk_data->clks = pmc_data->clks;
  402. if (d) {
  403. clk_data->critical = true;
  404. pr_info("%s critclks quirk enabled\n", d->ident);
  405. }
  406. clkdev = platform_device_register_data(&pdev->dev, "clk-pmc-atom",
  407. PLATFORM_DEVID_NONE,
  408. clk_data, sizeof(*clk_data));
  409. if (IS_ERR(clkdev)) {
  410. kfree(clk_data);
  411. return PTR_ERR(clkdev);
  412. }
  413. kfree(clk_data);
  414. return 0;
  415. }
  416. static int pmc_setup_dev(struct pci_dev *pdev, const struct pci_device_id *ent)
  417. {
  418. struct pmc_dev *pmc = &pmc_device;
  419. const struct pmc_data *data = (struct pmc_data *)ent->driver_data;
  420. const struct pmc_reg_map *map = data->map;
  421. int ret;
  422. /* Obtain ACPI base address */
  423. pci_read_config_dword(pdev, ACPI_BASE_ADDR_OFFSET, &acpi_base_addr);
  424. acpi_base_addr &= ACPI_BASE_ADDR_MASK;
  425. /* Install power off function */
  426. if (acpi_base_addr != 0 && pm_power_off == NULL)
  427. pm_power_off = pmc_power_off;
  428. pci_read_config_dword(pdev, PMC_BASE_ADDR_OFFSET, &pmc->base_addr);
  429. pmc->base_addr &= PMC_BASE_ADDR_MASK;
  430. pmc->regmap = ioremap_nocache(pmc->base_addr, PMC_MMIO_REG_LEN);
  431. if (!pmc->regmap) {
  432. dev_err(&pdev->dev, "error: ioremap failed\n");
  433. return -ENOMEM;
  434. }
  435. pmc->map = map;
  436. /* PMC hardware registers setup */
  437. pmc_hw_reg_setup(pmc);
  438. ret = pmc_dbgfs_register(pmc);
  439. if (ret)
  440. dev_warn(&pdev->dev, "debugfs register failed\n");
  441. /* Register platform clocks - PMC_PLT_CLK [0..5] */
  442. ret = pmc_setup_clks(pdev, pmc->regmap, data);
  443. if (ret)
  444. dev_warn(&pdev->dev, "platform clocks register failed: %d\n",
  445. ret);
  446. pmc->init = true;
  447. return ret;
  448. }
  449. /*
  450. * Data for PCI driver interface
  451. *
  452. * used by pci_match_id() call below.
  453. */
  454. static const struct pci_device_id pmc_pci_ids[] = {
  455. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_VLV_PMC), (kernel_ulong_t)&byt_data },
  456. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_CHT_PMC), (kernel_ulong_t)&cht_data },
  457. { 0, },
  458. };
  459. static int __init pmc_atom_init(void)
  460. {
  461. struct pci_dev *pdev = NULL;
  462. const struct pci_device_id *ent;
  463. /* We look for our device - PCU PMC
  464. * we assume that there is max. one device.
  465. *
  466. * We can't use plain pci_driver mechanism,
  467. * as the device is really a multiple function device,
  468. * main driver that binds to the pci_device is lpc_ich
  469. * and have to find & bind to the device this way.
  470. */
  471. for_each_pci_dev(pdev) {
  472. ent = pci_match_id(pmc_pci_ids, pdev);
  473. if (ent)
  474. return pmc_setup_dev(pdev, ent);
  475. }
  476. /* Device not found. */
  477. return -ENODEV;
  478. }
  479. device_initcall(pmc_atom_init);
  480. /*
  481. MODULE_AUTHOR("Aubrey Li <aubrey.li@linux.intel.com>");
  482. MODULE_DESCRIPTION("Intel Atom SOC Power Management Controller Interface");
  483. MODULE_LICENSE("GPL v2");
  484. */