pwm-img.c 11 KB

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  1. /*
  2. * Imagination Technologies Pulse Width Modulator driver
  3. *
  4. * Copyright (c) 2014-2015, Imagination Technologies
  5. *
  6. * Based on drivers/pwm/pwm-tegra.c, Copyright (c) 2010, NVIDIA Corporation
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License.
  11. */
  12. #include <linux/clk.h>
  13. #include <linux/err.h>
  14. #include <linux/io.h>
  15. #include <linux/mfd/syscon.h>
  16. #include <linux/module.h>
  17. #include <linux/of.h>
  18. #include <linux/of_device.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/pm_runtime.h>
  21. #include <linux/pwm.h>
  22. #include <linux/regmap.h>
  23. #include <linux/slab.h>
  24. /* PWM registers */
  25. #define PWM_CTRL_CFG 0x0000
  26. #define PWM_CTRL_CFG_NO_SUB_DIV 0
  27. #define PWM_CTRL_CFG_SUB_DIV0 1
  28. #define PWM_CTRL_CFG_SUB_DIV1 2
  29. #define PWM_CTRL_CFG_SUB_DIV0_DIV1 3
  30. #define PWM_CTRL_CFG_DIV_SHIFT(ch) ((ch) * 2 + 4)
  31. #define PWM_CTRL_CFG_DIV_MASK 0x3
  32. #define PWM_CH_CFG(ch) (0x4 + (ch) * 4)
  33. #define PWM_CH_CFG_TMBASE_SHIFT 0
  34. #define PWM_CH_CFG_DUTY_SHIFT 16
  35. #define PERIP_PWM_PDM_CONTROL 0x0140
  36. #define PERIP_PWM_PDM_CONTROL_CH_MASK 0x1
  37. #define PERIP_PWM_PDM_CONTROL_CH_SHIFT(ch) ((ch) * 4)
  38. #define IMG_PWM_PM_TIMEOUT 1000 /* ms */
  39. /*
  40. * PWM period is specified with a timebase register,
  41. * in number of step periods. The PWM duty cycle is also
  42. * specified in step periods, in the [0, $timebase] range.
  43. * In other words, the timebase imposes the duty cycle
  44. * resolution. Therefore, let's constraint the timebase to
  45. * a minimum value to allow a sane range of duty cycle values.
  46. * Imposing a minimum timebase, will impose a maximum PWM frequency.
  47. *
  48. * The value chosen is completely arbitrary.
  49. */
  50. #define MIN_TMBASE_STEPS 16
  51. #define IMG_PWM_NPWM 4
  52. struct img_pwm_soc_data {
  53. u32 max_timebase;
  54. };
  55. struct img_pwm_chip {
  56. struct device *dev;
  57. struct pwm_chip chip;
  58. struct clk *pwm_clk;
  59. struct clk *sys_clk;
  60. void __iomem *base;
  61. struct regmap *periph_regs;
  62. int max_period_ns;
  63. int min_period_ns;
  64. const struct img_pwm_soc_data *data;
  65. u32 suspend_ctrl_cfg;
  66. u32 suspend_ch_cfg[IMG_PWM_NPWM];
  67. };
  68. static inline struct img_pwm_chip *to_img_pwm_chip(struct pwm_chip *chip)
  69. {
  70. return container_of(chip, struct img_pwm_chip, chip);
  71. }
  72. static inline void img_pwm_writel(struct img_pwm_chip *chip,
  73. u32 reg, u32 val)
  74. {
  75. writel(val, chip->base + reg);
  76. }
  77. static inline u32 img_pwm_readl(struct img_pwm_chip *chip,
  78. u32 reg)
  79. {
  80. return readl(chip->base + reg);
  81. }
  82. static int img_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
  83. int duty_ns, int period_ns)
  84. {
  85. u32 val, div, duty, timebase;
  86. unsigned long mul, output_clk_hz, input_clk_hz;
  87. struct img_pwm_chip *pwm_chip = to_img_pwm_chip(chip);
  88. unsigned int max_timebase = pwm_chip->data->max_timebase;
  89. int ret;
  90. if (period_ns < pwm_chip->min_period_ns ||
  91. period_ns > pwm_chip->max_period_ns) {
  92. dev_err(chip->dev, "configured period not in range\n");
  93. return -ERANGE;
  94. }
  95. input_clk_hz = clk_get_rate(pwm_chip->pwm_clk);
  96. output_clk_hz = DIV_ROUND_UP(NSEC_PER_SEC, period_ns);
  97. mul = DIV_ROUND_UP(input_clk_hz, output_clk_hz);
  98. if (mul <= max_timebase) {
  99. div = PWM_CTRL_CFG_NO_SUB_DIV;
  100. timebase = DIV_ROUND_UP(mul, 1);
  101. } else if (mul <= max_timebase * 8) {
  102. div = PWM_CTRL_CFG_SUB_DIV0;
  103. timebase = DIV_ROUND_UP(mul, 8);
  104. } else if (mul <= max_timebase * 64) {
  105. div = PWM_CTRL_CFG_SUB_DIV1;
  106. timebase = DIV_ROUND_UP(mul, 64);
  107. } else if (mul <= max_timebase * 512) {
  108. div = PWM_CTRL_CFG_SUB_DIV0_DIV1;
  109. timebase = DIV_ROUND_UP(mul, 512);
  110. } else if (mul > max_timebase * 512) {
  111. dev_err(chip->dev,
  112. "failed to configure timebase steps/divider value\n");
  113. return -EINVAL;
  114. }
  115. duty = DIV_ROUND_UP(timebase * duty_ns, period_ns);
  116. ret = pm_runtime_get_sync(chip->dev);
  117. if (ret < 0) {
  118. pm_runtime_put_autosuspend(chip->dev);
  119. return ret;
  120. }
  121. val = img_pwm_readl(pwm_chip, PWM_CTRL_CFG);
  122. val &= ~(PWM_CTRL_CFG_DIV_MASK << PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm));
  123. val |= (div & PWM_CTRL_CFG_DIV_MASK) <<
  124. PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm);
  125. img_pwm_writel(pwm_chip, PWM_CTRL_CFG, val);
  126. val = (duty << PWM_CH_CFG_DUTY_SHIFT) |
  127. (timebase << PWM_CH_CFG_TMBASE_SHIFT);
  128. img_pwm_writel(pwm_chip, PWM_CH_CFG(pwm->hwpwm), val);
  129. pm_runtime_mark_last_busy(chip->dev);
  130. pm_runtime_put_autosuspend(chip->dev);
  131. return 0;
  132. }
  133. static int img_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
  134. {
  135. u32 val;
  136. struct img_pwm_chip *pwm_chip = to_img_pwm_chip(chip);
  137. int ret;
  138. ret = pm_runtime_get_sync(chip->dev);
  139. if (ret < 0)
  140. return ret;
  141. val = img_pwm_readl(pwm_chip, PWM_CTRL_CFG);
  142. val |= BIT(pwm->hwpwm);
  143. img_pwm_writel(pwm_chip, PWM_CTRL_CFG, val);
  144. regmap_update_bits(pwm_chip->periph_regs, PERIP_PWM_PDM_CONTROL,
  145. PERIP_PWM_PDM_CONTROL_CH_MASK <<
  146. PERIP_PWM_PDM_CONTROL_CH_SHIFT(pwm->hwpwm), 0);
  147. return 0;
  148. }
  149. static void img_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
  150. {
  151. u32 val;
  152. struct img_pwm_chip *pwm_chip = to_img_pwm_chip(chip);
  153. val = img_pwm_readl(pwm_chip, PWM_CTRL_CFG);
  154. val &= ~BIT(pwm->hwpwm);
  155. img_pwm_writel(pwm_chip, PWM_CTRL_CFG, val);
  156. pm_runtime_mark_last_busy(chip->dev);
  157. pm_runtime_put_autosuspend(chip->dev);
  158. }
  159. static const struct pwm_ops img_pwm_ops = {
  160. .config = img_pwm_config,
  161. .enable = img_pwm_enable,
  162. .disable = img_pwm_disable,
  163. .owner = THIS_MODULE,
  164. };
  165. static const struct img_pwm_soc_data pistachio_pwm = {
  166. .max_timebase = 255,
  167. };
  168. static const struct of_device_id img_pwm_of_match[] = {
  169. {
  170. .compatible = "img,pistachio-pwm",
  171. .data = &pistachio_pwm,
  172. },
  173. { }
  174. };
  175. MODULE_DEVICE_TABLE(of, img_pwm_of_match);
  176. static int img_pwm_runtime_suspend(struct device *dev)
  177. {
  178. struct img_pwm_chip *pwm_chip = dev_get_drvdata(dev);
  179. clk_disable_unprepare(pwm_chip->pwm_clk);
  180. clk_disable_unprepare(pwm_chip->sys_clk);
  181. return 0;
  182. }
  183. static int img_pwm_runtime_resume(struct device *dev)
  184. {
  185. struct img_pwm_chip *pwm_chip = dev_get_drvdata(dev);
  186. int ret;
  187. ret = clk_prepare_enable(pwm_chip->sys_clk);
  188. if (ret < 0) {
  189. dev_err(dev, "could not prepare or enable sys clock\n");
  190. return ret;
  191. }
  192. ret = clk_prepare_enable(pwm_chip->pwm_clk);
  193. if (ret < 0) {
  194. dev_err(dev, "could not prepare or enable pwm clock\n");
  195. clk_disable_unprepare(pwm_chip->sys_clk);
  196. return ret;
  197. }
  198. return 0;
  199. }
  200. static int img_pwm_probe(struct platform_device *pdev)
  201. {
  202. int ret;
  203. u64 val;
  204. unsigned long clk_rate;
  205. struct resource *res;
  206. struct img_pwm_chip *pwm;
  207. const struct of_device_id *of_dev_id;
  208. pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
  209. if (!pwm)
  210. return -ENOMEM;
  211. pwm->dev = &pdev->dev;
  212. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  213. pwm->base = devm_ioremap_resource(&pdev->dev, res);
  214. if (IS_ERR(pwm->base))
  215. return PTR_ERR(pwm->base);
  216. of_dev_id = of_match_device(img_pwm_of_match, &pdev->dev);
  217. if (!of_dev_id)
  218. return -ENODEV;
  219. pwm->data = of_dev_id->data;
  220. pwm->periph_regs = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
  221. "img,cr-periph");
  222. if (IS_ERR(pwm->periph_regs))
  223. return PTR_ERR(pwm->periph_regs);
  224. pwm->sys_clk = devm_clk_get(&pdev->dev, "sys");
  225. if (IS_ERR(pwm->sys_clk)) {
  226. dev_err(&pdev->dev, "failed to get system clock\n");
  227. return PTR_ERR(pwm->sys_clk);
  228. }
  229. pwm->pwm_clk = devm_clk_get(&pdev->dev, "pwm");
  230. if (IS_ERR(pwm->pwm_clk)) {
  231. dev_err(&pdev->dev, "failed to get pwm clock\n");
  232. return PTR_ERR(pwm->pwm_clk);
  233. }
  234. platform_set_drvdata(pdev, pwm);
  235. pm_runtime_set_autosuspend_delay(&pdev->dev, IMG_PWM_PM_TIMEOUT);
  236. pm_runtime_use_autosuspend(&pdev->dev);
  237. pm_runtime_enable(&pdev->dev);
  238. if (!pm_runtime_enabled(&pdev->dev)) {
  239. ret = img_pwm_runtime_resume(&pdev->dev);
  240. if (ret)
  241. goto err_pm_disable;
  242. }
  243. clk_rate = clk_get_rate(pwm->pwm_clk);
  244. if (!clk_rate) {
  245. dev_err(&pdev->dev, "pwm clock has no frequency\n");
  246. ret = -EINVAL;
  247. goto err_suspend;
  248. }
  249. /* The maximum input clock divider is 512 */
  250. val = (u64)NSEC_PER_SEC * 512 * pwm->data->max_timebase;
  251. do_div(val, clk_rate);
  252. pwm->max_period_ns = val;
  253. val = (u64)NSEC_PER_SEC * MIN_TMBASE_STEPS;
  254. do_div(val, clk_rate);
  255. pwm->min_period_ns = val;
  256. pwm->chip.dev = &pdev->dev;
  257. pwm->chip.ops = &img_pwm_ops;
  258. pwm->chip.base = -1;
  259. pwm->chip.npwm = IMG_PWM_NPWM;
  260. ret = pwmchip_add(&pwm->chip);
  261. if (ret < 0) {
  262. dev_err(&pdev->dev, "pwmchip_add failed: %d\n", ret);
  263. goto err_suspend;
  264. }
  265. return 0;
  266. err_suspend:
  267. if (!pm_runtime_enabled(&pdev->dev))
  268. img_pwm_runtime_suspend(&pdev->dev);
  269. err_pm_disable:
  270. pm_runtime_disable(&pdev->dev);
  271. pm_runtime_dont_use_autosuspend(&pdev->dev);
  272. return ret;
  273. }
  274. static int img_pwm_remove(struct platform_device *pdev)
  275. {
  276. struct img_pwm_chip *pwm_chip = platform_get_drvdata(pdev);
  277. u32 val;
  278. unsigned int i;
  279. int ret;
  280. ret = pm_runtime_get_sync(&pdev->dev);
  281. if (ret < 0) {
  282. pm_runtime_put(&pdev->dev);
  283. return ret;
  284. }
  285. for (i = 0; i < pwm_chip->chip.npwm; i++) {
  286. val = img_pwm_readl(pwm_chip, PWM_CTRL_CFG);
  287. val &= ~BIT(i);
  288. img_pwm_writel(pwm_chip, PWM_CTRL_CFG, val);
  289. }
  290. pm_runtime_put(&pdev->dev);
  291. pm_runtime_disable(&pdev->dev);
  292. if (!pm_runtime_status_suspended(&pdev->dev))
  293. img_pwm_runtime_suspend(&pdev->dev);
  294. return pwmchip_remove(&pwm_chip->chip);
  295. }
  296. #ifdef CONFIG_PM_SLEEP
  297. static int img_pwm_suspend(struct device *dev)
  298. {
  299. struct img_pwm_chip *pwm_chip = dev_get_drvdata(dev);
  300. int i, ret;
  301. if (pm_runtime_status_suspended(dev)) {
  302. ret = img_pwm_runtime_resume(dev);
  303. if (ret)
  304. return ret;
  305. }
  306. for (i = 0; i < pwm_chip->chip.npwm; i++)
  307. pwm_chip->suspend_ch_cfg[i] = img_pwm_readl(pwm_chip,
  308. PWM_CH_CFG(i));
  309. pwm_chip->suspend_ctrl_cfg = img_pwm_readl(pwm_chip, PWM_CTRL_CFG);
  310. img_pwm_runtime_suspend(dev);
  311. return 0;
  312. }
  313. static int img_pwm_resume(struct device *dev)
  314. {
  315. struct img_pwm_chip *pwm_chip = dev_get_drvdata(dev);
  316. int ret;
  317. int i;
  318. ret = img_pwm_runtime_resume(dev);
  319. if (ret)
  320. return ret;
  321. for (i = 0; i < pwm_chip->chip.npwm; i++)
  322. img_pwm_writel(pwm_chip, PWM_CH_CFG(i),
  323. pwm_chip->suspend_ch_cfg[i]);
  324. img_pwm_writel(pwm_chip, PWM_CTRL_CFG, pwm_chip->suspend_ctrl_cfg);
  325. for (i = 0; i < pwm_chip->chip.npwm; i++)
  326. if (pwm_chip->suspend_ctrl_cfg & BIT(i))
  327. regmap_update_bits(pwm_chip->periph_regs,
  328. PERIP_PWM_PDM_CONTROL,
  329. PERIP_PWM_PDM_CONTROL_CH_MASK <<
  330. PERIP_PWM_PDM_CONTROL_CH_SHIFT(i),
  331. 0);
  332. if (pm_runtime_status_suspended(dev))
  333. img_pwm_runtime_suspend(dev);
  334. return 0;
  335. }
  336. #endif /* CONFIG_PM */
  337. static const struct dev_pm_ops img_pwm_pm_ops = {
  338. SET_RUNTIME_PM_OPS(img_pwm_runtime_suspend,
  339. img_pwm_runtime_resume,
  340. NULL)
  341. SET_SYSTEM_SLEEP_PM_OPS(img_pwm_suspend, img_pwm_resume)
  342. };
  343. static struct platform_driver img_pwm_driver = {
  344. .driver = {
  345. .name = "img-pwm",
  346. .pm = &img_pwm_pm_ops,
  347. .of_match_table = img_pwm_of_match,
  348. },
  349. .probe = img_pwm_probe,
  350. .remove = img_pwm_remove,
  351. };
  352. module_platform_driver(img_pwm_driver);
  353. MODULE_AUTHOR("Sai Masarapu <Sai.Masarapu@imgtec.com>");
  354. MODULE_DESCRIPTION("Imagination Technologies PWM DAC driver");
  355. MODULE_LICENSE("GPL v2");