vfio_pci_config.c 51 KB

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  1. /*
  2. * VFIO PCI config space virtualization
  3. *
  4. * Copyright (C) 2012 Red Hat, Inc. All rights reserved.
  5. * Author: Alex Williamson <alex.williamson@redhat.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. * Derived from original vfio:
  12. * Copyright 2010 Cisco Systems, Inc. All rights reserved.
  13. * Author: Tom Lyon, pugs@cisco.com
  14. */
  15. /*
  16. * This code handles reading and writing of PCI configuration registers.
  17. * This is hairy because we want to allow a lot of flexibility to the
  18. * user driver, but cannot trust it with all of the config fields.
  19. * Tables determine which fields can be read and written, as well as
  20. * which fields are 'virtualized' - special actions and translations to
  21. * make it appear to the user that he has control, when in fact things
  22. * must be negotiated with the underlying OS.
  23. */
  24. #include <linux/fs.h>
  25. #include <linux/pci.h>
  26. #include <linux/uaccess.h>
  27. #include <linux/vfio.h>
  28. #include <linux/slab.h>
  29. #include "vfio_pci_private.h"
  30. /* Fake capability ID for standard config space */
  31. #define PCI_CAP_ID_BASIC 0
  32. #define is_bar(offset) \
  33. ((offset >= PCI_BASE_ADDRESS_0 && offset < PCI_BASE_ADDRESS_5 + 4) || \
  34. (offset >= PCI_ROM_ADDRESS && offset < PCI_ROM_ADDRESS + 4))
  35. /*
  36. * Lengths of PCI Config Capabilities
  37. * 0: Removed from the user visible capability list
  38. * FF: Variable length
  39. */
  40. static const u8 pci_cap_length[PCI_CAP_ID_MAX + 1] = {
  41. [PCI_CAP_ID_BASIC] = PCI_STD_HEADER_SIZEOF, /* pci config header */
  42. [PCI_CAP_ID_PM] = PCI_PM_SIZEOF,
  43. [PCI_CAP_ID_AGP] = PCI_AGP_SIZEOF,
  44. [PCI_CAP_ID_VPD] = PCI_CAP_VPD_SIZEOF,
  45. [PCI_CAP_ID_SLOTID] = 0, /* bridge - don't care */
  46. [PCI_CAP_ID_MSI] = 0xFF, /* 10, 14, 20, or 24 */
  47. [PCI_CAP_ID_CHSWP] = 0, /* cpci - not yet */
  48. [PCI_CAP_ID_PCIX] = 0xFF, /* 8 or 24 */
  49. [PCI_CAP_ID_HT] = 0xFF, /* hypertransport */
  50. [PCI_CAP_ID_VNDR] = 0xFF, /* variable */
  51. [PCI_CAP_ID_DBG] = 0, /* debug - don't care */
  52. [PCI_CAP_ID_CCRC] = 0, /* cpci - not yet */
  53. [PCI_CAP_ID_SHPC] = 0, /* hotswap - not yet */
  54. [PCI_CAP_ID_SSVID] = 0, /* bridge - don't care */
  55. [PCI_CAP_ID_AGP3] = 0, /* AGP8x - not yet */
  56. [PCI_CAP_ID_SECDEV] = 0, /* secure device not yet */
  57. [PCI_CAP_ID_EXP] = 0xFF, /* 20 or 44 */
  58. [PCI_CAP_ID_MSIX] = PCI_CAP_MSIX_SIZEOF,
  59. [PCI_CAP_ID_SATA] = 0xFF,
  60. [PCI_CAP_ID_AF] = PCI_CAP_AF_SIZEOF,
  61. };
  62. /*
  63. * Lengths of PCIe/PCI-X Extended Config Capabilities
  64. * 0: Removed or masked from the user visible capability list
  65. * FF: Variable length
  66. */
  67. static const u16 pci_ext_cap_length[PCI_EXT_CAP_ID_MAX + 1] = {
  68. [PCI_EXT_CAP_ID_ERR] = PCI_ERR_ROOT_COMMAND,
  69. [PCI_EXT_CAP_ID_VC] = 0xFF,
  70. [PCI_EXT_CAP_ID_DSN] = PCI_EXT_CAP_DSN_SIZEOF,
  71. [PCI_EXT_CAP_ID_PWR] = PCI_EXT_CAP_PWR_SIZEOF,
  72. [PCI_EXT_CAP_ID_RCLD] = 0, /* root only - don't care */
  73. [PCI_EXT_CAP_ID_RCILC] = 0, /* root only - don't care */
  74. [PCI_EXT_CAP_ID_RCEC] = 0, /* root only - don't care */
  75. [PCI_EXT_CAP_ID_MFVC] = 0xFF,
  76. [PCI_EXT_CAP_ID_VC9] = 0xFF, /* same as CAP_ID_VC */
  77. [PCI_EXT_CAP_ID_RCRB] = 0, /* root only - don't care */
  78. [PCI_EXT_CAP_ID_VNDR] = 0xFF,
  79. [PCI_EXT_CAP_ID_CAC] = 0, /* obsolete */
  80. [PCI_EXT_CAP_ID_ACS] = 0xFF,
  81. [PCI_EXT_CAP_ID_ARI] = PCI_EXT_CAP_ARI_SIZEOF,
  82. [PCI_EXT_CAP_ID_ATS] = PCI_EXT_CAP_ATS_SIZEOF,
  83. [PCI_EXT_CAP_ID_SRIOV] = PCI_EXT_CAP_SRIOV_SIZEOF,
  84. [PCI_EXT_CAP_ID_MRIOV] = 0, /* not yet */
  85. [PCI_EXT_CAP_ID_MCAST] = PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF,
  86. [PCI_EXT_CAP_ID_PRI] = PCI_EXT_CAP_PRI_SIZEOF,
  87. [PCI_EXT_CAP_ID_AMD_XXX] = 0, /* not yet */
  88. [PCI_EXT_CAP_ID_REBAR] = 0xFF,
  89. [PCI_EXT_CAP_ID_DPA] = 0xFF,
  90. [PCI_EXT_CAP_ID_TPH] = 0xFF,
  91. [PCI_EXT_CAP_ID_LTR] = PCI_EXT_CAP_LTR_SIZEOF,
  92. [PCI_EXT_CAP_ID_SECPCI] = 0, /* not yet */
  93. [PCI_EXT_CAP_ID_PMUX] = 0, /* not yet */
  94. [PCI_EXT_CAP_ID_PASID] = 0, /* not yet */
  95. };
  96. /*
  97. * Read/Write Permission Bits - one bit for each bit in capability
  98. * Any field can be read if it exists, but what is read depends on
  99. * whether the field is 'virtualized', or just pass thru to the
  100. * hardware. Any virtualized field is also virtualized for writes.
  101. * Writes are only permitted if they have a 1 bit here.
  102. */
  103. struct perm_bits {
  104. u8 *virt; /* read/write virtual data, not hw */
  105. u8 *write; /* writeable bits */
  106. int (*readfn)(struct vfio_pci_device *vdev, int pos, int count,
  107. struct perm_bits *perm, int offset, __le32 *val);
  108. int (*writefn)(struct vfio_pci_device *vdev, int pos, int count,
  109. struct perm_bits *perm, int offset, __le32 val);
  110. };
  111. #define NO_VIRT 0
  112. #define ALL_VIRT 0xFFFFFFFFU
  113. #define NO_WRITE 0
  114. #define ALL_WRITE 0xFFFFFFFFU
  115. static int vfio_user_config_read(struct pci_dev *pdev, int offset,
  116. __le32 *val, int count)
  117. {
  118. int ret = -EINVAL;
  119. u32 tmp_val = 0;
  120. switch (count) {
  121. case 1:
  122. {
  123. u8 tmp;
  124. ret = pci_user_read_config_byte(pdev, offset, &tmp);
  125. tmp_val = tmp;
  126. break;
  127. }
  128. case 2:
  129. {
  130. u16 tmp;
  131. ret = pci_user_read_config_word(pdev, offset, &tmp);
  132. tmp_val = tmp;
  133. break;
  134. }
  135. case 4:
  136. ret = pci_user_read_config_dword(pdev, offset, &tmp_val);
  137. break;
  138. }
  139. *val = cpu_to_le32(tmp_val);
  140. return ret;
  141. }
  142. static int vfio_user_config_write(struct pci_dev *pdev, int offset,
  143. __le32 val, int count)
  144. {
  145. int ret = -EINVAL;
  146. u32 tmp_val = le32_to_cpu(val);
  147. switch (count) {
  148. case 1:
  149. ret = pci_user_write_config_byte(pdev, offset, tmp_val);
  150. break;
  151. case 2:
  152. ret = pci_user_write_config_word(pdev, offset, tmp_val);
  153. break;
  154. case 4:
  155. ret = pci_user_write_config_dword(pdev, offset, tmp_val);
  156. break;
  157. }
  158. return ret;
  159. }
  160. static int vfio_default_config_read(struct vfio_pci_device *vdev, int pos,
  161. int count, struct perm_bits *perm,
  162. int offset, __le32 *val)
  163. {
  164. __le32 virt = 0;
  165. memcpy(val, vdev->vconfig + pos, count);
  166. memcpy(&virt, perm->virt + offset, count);
  167. /* Any non-virtualized bits? */
  168. if (cpu_to_le32(~0U >> (32 - (count * 8))) != virt) {
  169. struct pci_dev *pdev = vdev->pdev;
  170. __le32 phys_val = 0;
  171. int ret;
  172. ret = vfio_user_config_read(pdev, pos, &phys_val, count);
  173. if (ret)
  174. return ret;
  175. *val = (phys_val & ~virt) | (*val & virt);
  176. }
  177. return count;
  178. }
  179. static int vfio_default_config_write(struct vfio_pci_device *vdev, int pos,
  180. int count, struct perm_bits *perm,
  181. int offset, __le32 val)
  182. {
  183. __le32 virt = 0, write = 0;
  184. memcpy(&write, perm->write + offset, count);
  185. if (!write)
  186. return count; /* drop, no writable bits */
  187. memcpy(&virt, perm->virt + offset, count);
  188. /* Virtualized and writable bits go to vconfig */
  189. if (write & virt) {
  190. __le32 virt_val = 0;
  191. memcpy(&virt_val, vdev->vconfig + pos, count);
  192. virt_val &= ~(write & virt);
  193. virt_val |= (val & (write & virt));
  194. memcpy(vdev->vconfig + pos, &virt_val, count);
  195. }
  196. /* Non-virtualzed and writable bits go to hardware */
  197. if (write & ~virt) {
  198. struct pci_dev *pdev = vdev->pdev;
  199. __le32 phys_val = 0;
  200. int ret;
  201. ret = vfio_user_config_read(pdev, pos, &phys_val, count);
  202. if (ret)
  203. return ret;
  204. phys_val &= ~(write & ~virt);
  205. phys_val |= (val & (write & ~virt));
  206. ret = vfio_user_config_write(pdev, pos, phys_val, count);
  207. if (ret)
  208. return ret;
  209. }
  210. return count;
  211. }
  212. /* Allow direct read from hardware, except for capability next pointer */
  213. static int vfio_direct_config_read(struct vfio_pci_device *vdev, int pos,
  214. int count, struct perm_bits *perm,
  215. int offset, __le32 *val)
  216. {
  217. int ret;
  218. ret = vfio_user_config_read(vdev->pdev, pos, val, count);
  219. if (ret)
  220. return ret;
  221. if (pos >= PCI_CFG_SPACE_SIZE) { /* Extended cap header mangling */
  222. if (offset < 4)
  223. memcpy(val, vdev->vconfig + pos, count);
  224. } else if (pos >= PCI_STD_HEADER_SIZEOF) { /* Std cap mangling */
  225. if (offset == PCI_CAP_LIST_ID && count > 1)
  226. memcpy(val, vdev->vconfig + pos,
  227. min(PCI_CAP_FLAGS, count));
  228. else if (offset == PCI_CAP_LIST_NEXT)
  229. memcpy(val, vdev->vconfig + pos, 1);
  230. }
  231. return count;
  232. }
  233. /* Raw access skips any kind of virtualization */
  234. static int vfio_raw_config_write(struct vfio_pci_device *vdev, int pos,
  235. int count, struct perm_bits *perm,
  236. int offset, __le32 val)
  237. {
  238. int ret;
  239. ret = vfio_user_config_write(vdev->pdev, pos, val, count);
  240. if (ret)
  241. return ret;
  242. return count;
  243. }
  244. static int vfio_raw_config_read(struct vfio_pci_device *vdev, int pos,
  245. int count, struct perm_bits *perm,
  246. int offset, __le32 *val)
  247. {
  248. int ret;
  249. ret = vfio_user_config_read(vdev->pdev, pos, val, count);
  250. if (ret)
  251. return ret;
  252. return count;
  253. }
  254. /* Virt access uses only virtualization */
  255. static int vfio_virt_config_write(struct vfio_pci_device *vdev, int pos,
  256. int count, struct perm_bits *perm,
  257. int offset, __le32 val)
  258. {
  259. memcpy(vdev->vconfig + pos, &val, count);
  260. return count;
  261. }
  262. static int vfio_virt_config_read(struct vfio_pci_device *vdev, int pos,
  263. int count, struct perm_bits *perm,
  264. int offset, __le32 *val)
  265. {
  266. memcpy(val, vdev->vconfig + pos, count);
  267. return count;
  268. }
  269. /* Default capability regions to read-only, no-virtualization */
  270. static struct perm_bits cap_perms[PCI_CAP_ID_MAX + 1] = {
  271. [0 ... PCI_CAP_ID_MAX] = { .readfn = vfio_direct_config_read }
  272. };
  273. static struct perm_bits ecap_perms[PCI_EXT_CAP_ID_MAX + 1] = {
  274. [0 ... PCI_EXT_CAP_ID_MAX] = { .readfn = vfio_direct_config_read }
  275. };
  276. /*
  277. * Default unassigned regions to raw read-write access. Some devices
  278. * require this to function as they hide registers between the gaps in
  279. * config space (be2net). Like MMIO and I/O port registers, we have
  280. * to trust the hardware isolation.
  281. */
  282. static struct perm_bits unassigned_perms = {
  283. .readfn = vfio_raw_config_read,
  284. .writefn = vfio_raw_config_write
  285. };
  286. static struct perm_bits virt_perms = {
  287. .readfn = vfio_virt_config_read,
  288. .writefn = vfio_virt_config_write
  289. };
  290. static void free_perm_bits(struct perm_bits *perm)
  291. {
  292. kfree(perm->virt);
  293. kfree(perm->write);
  294. perm->virt = NULL;
  295. perm->write = NULL;
  296. }
  297. static int alloc_perm_bits(struct perm_bits *perm, int size)
  298. {
  299. /*
  300. * Round up all permission bits to the next dword, this lets us
  301. * ignore whether a read/write exceeds the defined capability
  302. * structure. We can do this because:
  303. * - Standard config space is already dword aligned
  304. * - Capabilities are all dword aligned (bits 0:1 of next reserved)
  305. * - Express capabilities defined as dword aligned
  306. */
  307. size = round_up(size, 4);
  308. /*
  309. * Zero state is
  310. * - All Readable, None Writeable, None Virtualized
  311. */
  312. perm->virt = kzalloc(size, GFP_KERNEL);
  313. perm->write = kzalloc(size, GFP_KERNEL);
  314. if (!perm->virt || !perm->write) {
  315. free_perm_bits(perm);
  316. return -ENOMEM;
  317. }
  318. perm->readfn = vfio_default_config_read;
  319. perm->writefn = vfio_default_config_write;
  320. return 0;
  321. }
  322. /*
  323. * Helper functions for filling in permission tables
  324. */
  325. static inline void p_setb(struct perm_bits *p, int off, u8 virt, u8 write)
  326. {
  327. p->virt[off] = virt;
  328. p->write[off] = write;
  329. }
  330. /* Handle endian-ness - pci and tables are little-endian */
  331. static inline void p_setw(struct perm_bits *p, int off, u16 virt, u16 write)
  332. {
  333. *(__le16 *)(&p->virt[off]) = cpu_to_le16(virt);
  334. *(__le16 *)(&p->write[off]) = cpu_to_le16(write);
  335. }
  336. /* Handle endian-ness - pci and tables are little-endian */
  337. static inline void p_setd(struct perm_bits *p, int off, u32 virt, u32 write)
  338. {
  339. *(__le32 *)(&p->virt[off]) = cpu_to_le32(virt);
  340. *(__le32 *)(&p->write[off]) = cpu_to_le32(write);
  341. }
  342. /* Caller should hold memory_lock semaphore */
  343. bool __vfio_pci_memory_enabled(struct vfio_pci_device *vdev)
  344. {
  345. struct pci_dev *pdev = vdev->pdev;
  346. u16 cmd = le16_to_cpu(*(__le16 *)&vdev->vconfig[PCI_COMMAND]);
  347. /*
  348. * SR-IOV VF memory enable is handled by the MSE bit in the
  349. * PF SR-IOV capability, there's therefore no need to trigger
  350. * faults based on the virtual value.
  351. */
  352. return pdev->is_virtfn || (cmd & PCI_COMMAND_MEMORY);
  353. }
  354. /*
  355. * Restore the *real* BARs after we detect a FLR or backdoor reset.
  356. * (backdoor = some device specific technique that we didn't catch)
  357. */
  358. static void vfio_bar_restore(struct vfio_pci_device *vdev)
  359. {
  360. struct pci_dev *pdev = vdev->pdev;
  361. u32 *rbar = vdev->rbar;
  362. u16 cmd;
  363. int i;
  364. if (pdev->is_virtfn)
  365. return;
  366. pr_info("%s: %s reset recovery - restoring bars\n",
  367. __func__, dev_name(&pdev->dev));
  368. for (i = PCI_BASE_ADDRESS_0; i <= PCI_BASE_ADDRESS_5; i += 4, rbar++)
  369. pci_user_write_config_dword(pdev, i, *rbar);
  370. pci_user_write_config_dword(pdev, PCI_ROM_ADDRESS, *rbar);
  371. if (vdev->nointx) {
  372. pci_user_read_config_word(pdev, PCI_COMMAND, &cmd);
  373. cmd |= PCI_COMMAND_INTX_DISABLE;
  374. pci_user_write_config_word(pdev, PCI_COMMAND, cmd);
  375. }
  376. }
  377. static __le32 vfio_generate_bar_flags(struct pci_dev *pdev, int bar)
  378. {
  379. unsigned long flags = pci_resource_flags(pdev, bar);
  380. u32 val;
  381. if (flags & IORESOURCE_IO)
  382. return cpu_to_le32(PCI_BASE_ADDRESS_SPACE_IO);
  383. val = PCI_BASE_ADDRESS_SPACE_MEMORY;
  384. if (flags & IORESOURCE_PREFETCH)
  385. val |= PCI_BASE_ADDRESS_MEM_PREFETCH;
  386. if (flags & IORESOURCE_MEM_64)
  387. val |= PCI_BASE_ADDRESS_MEM_TYPE_64;
  388. return cpu_to_le32(val);
  389. }
  390. /*
  391. * Pretend we're hardware and tweak the values of the *virtual* PCI BARs
  392. * to reflect the hardware capabilities. This implements BAR sizing.
  393. */
  394. static void vfio_bar_fixup(struct vfio_pci_device *vdev)
  395. {
  396. struct pci_dev *pdev = vdev->pdev;
  397. int i;
  398. __le32 *bar;
  399. u64 mask;
  400. bar = (__le32 *)&vdev->vconfig[PCI_BASE_ADDRESS_0];
  401. for (i = PCI_STD_RESOURCES; i <= PCI_STD_RESOURCE_END; i++, bar++) {
  402. if (!pci_resource_start(pdev, i)) {
  403. *bar = 0; /* Unmapped by host = unimplemented to user */
  404. continue;
  405. }
  406. mask = ~(pci_resource_len(pdev, i) - 1);
  407. *bar &= cpu_to_le32((u32)mask);
  408. *bar |= vfio_generate_bar_flags(pdev, i);
  409. if (*bar & cpu_to_le32(PCI_BASE_ADDRESS_MEM_TYPE_64)) {
  410. bar++;
  411. *bar &= cpu_to_le32((u32)(mask >> 32));
  412. i++;
  413. }
  414. }
  415. bar = (__le32 *)&vdev->vconfig[PCI_ROM_ADDRESS];
  416. /*
  417. * NB. REGION_INFO will have reported zero size if we weren't able
  418. * to read the ROM, but we still return the actual BAR size here if
  419. * it exists (or the shadow ROM space).
  420. */
  421. if (pci_resource_start(pdev, PCI_ROM_RESOURCE)) {
  422. mask = ~(pci_resource_len(pdev, PCI_ROM_RESOURCE) - 1);
  423. mask |= PCI_ROM_ADDRESS_ENABLE;
  424. *bar &= cpu_to_le32((u32)mask);
  425. } else if (pdev->resource[PCI_ROM_RESOURCE].flags &
  426. IORESOURCE_ROM_SHADOW) {
  427. mask = ~(0x20000 - 1);
  428. mask |= PCI_ROM_ADDRESS_ENABLE;
  429. *bar &= cpu_to_le32((u32)mask);
  430. } else
  431. *bar = 0;
  432. vdev->bardirty = false;
  433. }
  434. static int vfio_basic_config_read(struct vfio_pci_device *vdev, int pos,
  435. int count, struct perm_bits *perm,
  436. int offset, __le32 *val)
  437. {
  438. if (is_bar(offset)) /* pos == offset for basic config */
  439. vfio_bar_fixup(vdev);
  440. count = vfio_default_config_read(vdev, pos, count, perm, offset, val);
  441. /* Mask in virtual memory enable for SR-IOV devices */
  442. if (offset == PCI_COMMAND && vdev->pdev->is_virtfn) {
  443. u16 cmd = le16_to_cpu(*(__le16 *)&vdev->vconfig[PCI_COMMAND]);
  444. u32 tmp_val = le32_to_cpu(*val);
  445. tmp_val |= cmd & PCI_COMMAND_MEMORY;
  446. *val = cpu_to_le32(tmp_val);
  447. }
  448. return count;
  449. }
  450. /* Test whether BARs match the value we think they should contain */
  451. static bool vfio_need_bar_restore(struct vfio_pci_device *vdev)
  452. {
  453. int i = 0, pos = PCI_BASE_ADDRESS_0, ret;
  454. u32 bar;
  455. for (; pos <= PCI_BASE_ADDRESS_5; i++, pos += 4) {
  456. if (vdev->rbar[i]) {
  457. ret = pci_user_read_config_dword(vdev->pdev, pos, &bar);
  458. if (ret || vdev->rbar[i] != bar)
  459. return true;
  460. }
  461. }
  462. return false;
  463. }
  464. static int vfio_basic_config_write(struct vfio_pci_device *vdev, int pos,
  465. int count, struct perm_bits *perm,
  466. int offset, __le32 val)
  467. {
  468. struct pci_dev *pdev = vdev->pdev;
  469. __le16 *virt_cmd;
  470. u16 new_cmd = 0;
  471. int ret;
  472. virt_cmd = (__le16 *)&vdev->vconfig[PCI_COMMAND];
  473. if (offset == PCI_COMMAND) {
  474. bool phys_mem, virt_mem, new_mem, phys_io, virt_io, new_io;
  475. u16 phys_cmd;
  476. ret = pci_user_read_config_word(pdev, PCI_COMMAND, &phys_cmd);
  477. if (ret)
  478. return ret;
  479. new_cmd = le32_to_cpu(val);
  480. phys_io = !!(phys_cmd & PCI_COMMAND_IO);
  481. virt_io = !!(le16_to_cpu(*virt_cmd) & PCI_COMMAND_IO);
  482. new_io = !!(new_cmd & PCI_COMMAND_IO);
  483. phys_mem = !!(phys_cmd & PCI_COMMAND_MEMORY);
  484. virt_mem = !!(le16_to_cpu(*virt_cmd) & PCI_COMMAND_MEMORY);
  485. new_mem = !!(new_cmd & PCI_COMMAND_MEMORY);
  486. if (!new_mem)
  487. vfio_pci_zap_and_down_write_memory_lock(vdev);
  488. else
  489. down_write(&vdev->memory_lock);
  490. /*
  491. * If the user is writing mem/io enable (new_mem/io) and we
  492. * think it's already enabled (virt_mem/io), but the hardware
  493. * shows it disabled (phys_mem/io, then the device has
  494. * undergone some kind of backdoor reset and needs to be
  495. * restored before we allow it to enable the bars.
  496. * SR-IOV devices will trigger this, but we catch them later
  497. */
  498. if ((new_mem && virt_mem && !phys_mem) ||
  499. (new_io && virt_io && !phys_io) ||
  500. vfio_need_bar_restore(vdev))
  501. vfio_bar_restore(vdev);
  502. }
  503. count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
  504. if (count < 0) {
  505. if (offset == PCI_COMMAND)
  506. up_write(&vdev->memory_lock);
  507. return count;
  508. }
  509. /*
  510. * Save current memory/io enable bits in vconfig to allow for
  511. * the test above next time.
  512. */
  513. if (offset == PCI_COMMAND) {
  514. u16 mask = PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
  515. *virt_cmd &= cpu_to_le16(~mask);
  516. *virt_cmd |= cpu_to_le16(new_cmd & mask);
  517. up_write(&vdev->memory_lock);
  518. }
  519. /* Emulate INTx disable */
  520. if (offset >= PCI_COMMAND && offset <= PCI_COMMAND + 1) {
  521. bool virt_intx_disable;
  522. virt_intx_disable = !!(le16_to_cpu(*virt_cmd) &
  523. PCI_COMMAND_INTX_DISABLE);
  524. if (virt_intx_disable && !vdev->virq_disabled) {
  525. vdev->virq_disabled = true;
  526. vfio_pci_intx_mask(vdev);
  527. } else if (!virt_intx_disable && vdev->virq_disabled) {
  528. vdev->virq_disabled = false;
  529. vfio_pci_intx_unmask(vdev);
  530. }
  531. }
  532. if (is_bar(offset))
  533. vdev->bardirty = true;
  534. return count;
  535. }
  536. /* Permissions for the Basic PCI Header */
  537. static int __init init_pci_cap_basic_perm(struct perm_bits *perm)
  538. {
  539. if (alloc_perm_bits(perm, PCI_STD_HEADER_SIZEOF))
  540. return -ENOMEM;
  541. perm->readfn = vfio_basic_config_read;
  542. perm->writefn = vfio_basic_config_write;
  543. /* Virtualized for SR-IOV functions, which just have FFFF */
  544. p_setw(perm, PCI_VENDOR_ID, (u16)ALL_VIRT, NO_WRITE);
  545. p_setw(perm, PCI_DEVICE_ID, (u16)ALL_VIRT, NO_WRITE);
  546. /*
  547. * Virtualize INTx disable, we use it internally for interrupt
  548. * control and can emulate it for non-PCI 2.3 devices.
  549. */
  550. p_setw(perm, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE, (u16)ALL_WRITE);
  551. /* Virtualize capability list, we might want to skip/disable */
  552. p_setw(perm, PCI_STATUS, PCI_STATUS_CAP_LIST, NO_WRITE);
  553. /* No harm to write */
  554. p_setb(perm, PCI_CACHE_LINE_SIZE, NO_VIRT, (u8)ALL_WRITE);
  555. p_setb(perm, PCI_LATENCY_TIMER, NO_VIRT, (u8)ALL_WRITE);
  556. p_setb(perm, PCI_BIST, NO_VIRT, (u8)ALL_WRITE);
  557. /* Virtualize all bars, can't touch the real ones */
  558. p_setd(perm, PCI_BASE_ADDRESS_0, ALL_VIRT, ALL_WRITE);
  559. p_setd(perm, PCI_BASE_ADDRESS_1, ALL_VIRT, ALL_WRITE);
  560. p_setd(perm, PCI_BASE_ADDRESS_2, ALL_VIRT, ALL_WRITE);
  561. p_setd(perm, PCI_BASE_ADDRESS_3, ALL_VIRT, ALL_WRITE);
  562. p_setd(perm, PCI_BASE_ADDRESS_4, ALL_VIRT, ALL_WRITE);
  563. p_setd(perm, PCI_BASE_ADDRESS_5, ALL_VIRT, ALL_WRITE);
  564. p_setd(perm, PCI_ROM_ADDRESS, ALL_VIRT, ALL_WRITE);
  565. /* Allow us to adjust capability chain */
  566. p_setb(perm, PCI_CAPABILITY_LIST, (u8)ALL_VIRT, NO_WRITE);
  567. /* Sometimes used by sw, just virtualize */
  568. p_setb(perm, PCI_INTERRUPT_LINE, (u8)ALL_VIRT, (u8)ALL_WRITE);
  569. /* Virtualize interrupt pin to allow hiding INTx */
  570. p_setb(perm, PCI_INTERRUPT_PIN, (u8)ALL_VIRT, (u8)NO_WRITE);
  571. return 0;
  572. }
  573. static int vfio_pm_config_write(struct vfio_pci_device *vdev, int pos,
  574. int count, struct perm_bits *perm,
  575. int offset, __le32 val)
  576. {
  577. count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
  578. if (count < 0)
  579. return count;
  580. if (offset == PCI_PM_CTRL) {
  581. pci_power_t state;
  582. switch (le32_to_cpu(val) & PCI_PM_CTRL_STATE_MASK) {
  583. case 0:
  584. state = PCI_D0;
  585. break;
  586. case 1:
  587. state = PCI_D1;
  588. break;
  589. case 2:
  590. state = PCI_D2;
  591. break;
  592. case 3:
  593. state = PCI_D3hot;
  594. break;
  595. }
  596. pci_set_power_state(vdev->pdev, state);
  597. }
  598. return count;
  599. }
  600. /* Permissions for the Power Management capability */
  601. static int __init init_pci_cap_pm_perm(struct perm_bits *perm)
  602. {
  603. if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_PM]))
  604. return -ENOMEM;
  605. perm->writefn = vfio_pm_config_write;
  606. /*
  607. * We always virtualize the next field so we can remove
  608. * capabilities from the chain if we want to.
  609. */
  610. p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
  611. /*
  612. * Power management is defined *per function*, so we can let
  613. * the user change power state, but we trap and initiate the
  614. * change ourselves, so the state bits are read-only.
  615. */
  616. p_setd(perm, PCI_PM_CTRL, NO_VIRT, ~PCI_PM_CTRL_STATE_MASK);
  617. return 0;
  618. }
  619. static int vfio_vpd_config_write(struct vfio_pci_device *vdev, int pos,
  620. int count, struct perm_bits *perm,
  621. int offset, __le32 val)
  622. {
  623. struct pci_dev *pdev = vdev->pdev;
  624. __le16 *paddr = (__le16 *)(vdev->vconfig + pos - offset + PCI_VPD_ADDR);
  625. __le32 *pdata = (__le32 *)(vdev->vconfig + pos - offset + PCI_VPD_DATA);
  626. u16 addr;
  627. u32 data;
  628. /*
  629. * Write through to emulation. If the write includes the upper byte
  630. * of PCI_VPD_ADDR, then the PCI_VPD_ADDR_F bit is written and we
  631. * have work to do.
  632. */
  633. count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
  634. if (count < 0 || offset > PCI_VPD_ADDR + 1 ||
  635. offset + count <= PCI_VPD_ADDR + 1)
  636. return count;
  637. addr = le16_to_cpu(*paddr);
  638. if (addr & PCI_VPD_ADDR_F) {
  639. data = le32_to_cpu(*pdata);
  640. if (pci_write_vpd(pdev, addr & ~PCI_VPD_ADDR_F, 4, &data) != 4)
  641. return count;
  642. } else {
  643. data = 0;
  644. if (pci_read_vpd(pdev, addr, 4, &data) < 0)
  645. return count;
  646. *pdata = cpu_to_le32(data);
  647. }
  648. /*
  649. * Toggle PCI_VPD_ADDR_F in the emulated PCI_VPD_ADDR register to
  650. * signal completion. If an error occurs above, we assume that not
  651. * toggling this bit will induce a driver timeout.
  652. */
  653. addr ^= PCI_VPD_ADDR_F;
  654. *paddr = cpu_to_le16(addr);
  655. return count;
  656. }
  657. /* Permissions for Vital Product Data capability */
  658. static int __init init_pci_cap_vpd_perm(struct perm_bits *perm)
  659. {
  660. if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_VPD]))
  661. return -ENOMEM;
  662. perm->writefn = vfio_vpd_config_write;
  663. /*
  664. * We always virtualize the next field so we can remove
  665. * capabilities from the chain if we want to.
  666. */
  667. p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
  668. /*
  669. * Both the address and data registers are virtualized to
  670. * enable access through the pci_vpd_read/write functions
  671. */
  672. p_setw(perm, PCI_VPD_ADDR, (u16)ALL_VIRT, (u16)ALL_WRITE);
  673. p_setd(perm, PCI_VPD_DATA, ALL_VIRT, ALL_WRITE);
  674. return 0;
  675. }
  676. /* Permissions for PCI-X capability */
  677. static int __init init_pci_cap_pcix_perm(struct perm_bits *perm)
  678. {
  679. /* Alloc 24, but only 8 are used in v0 */
  680. if (alloc_perm_bits(perm, PCI_CAP_PCIX_SIZEOF_V2))
  681. return -ENOMEM;
  682. p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
  683. p_setw(perm, PCI_X_CMD, NO_VIRT, (u16)ALL_WRITE);
  684. p_setd(perm, PCI_X_ECC_CSR, NO_VIRT, ALL_WRITE);
  685. return 0;
  686. }
  687. static int vfio_exp_config_write(struct vfio_pci_device *vdev, int pos,
  688. int count, struct perm_bits *perm,
  689. int offset, __le32 val)
  690. {
  691. __le16 *ctrl = (__le16 *)(vdev->vconfig + pos -
  692. offset + PCI_EXP_DEVCTL);
  693. int readrq = le16_to_cpu(*ctrl) & PCI_EXP_DEVCTL_READRQ;
  694. count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
  695. if (count < 0)
  696. return count;
  697. /*
  698. * The FLR bit is virtualized, if set and the device supports PCIe
  699. * FLR, issue a reset_function. Regardless, clear the bit, the spec
  700. * requires it to be always read as zero. NB, reset_function might
  701. * not use a PCIe FLR, we don't have that level of granularity.
  702. */
  703. if (*ctrl & cpu_to_le16(PCI_EXP_DEVCTL_BCR_FLR)) {
  704. u32 cap;
  705. int ret;
  706. *ctrl &= ~cpu_to_le16(PCI_EXP_DEVCTL_BCR_FLR);
  707. ret = pci_user_read_config_dword(vdev->pdev,
  708. pos - offset + PCI_EXP_DEVCAP,
  709. &cap);
  710. if (!ret && (cap & PCI_EXP_DEVCAP_FLR)) {
  711. vfio_pci_zap_and_down_write_memory_lock(vdev);
  712. pci_try_reset_function(vdev->pdev);
  713. up_write(&vdev->memory_lock);
  714. }
  715. }
  716. /*
  717. * MPS is virtualized to the user, writes do not change the physical
  718. * register since determining a proper MPS value requires a system wide
  719. * device view. The MRRS is largely independent of MPS, but since the
  720. * user does not have that system-wide view, they might set a safe, but
  721. * inefficiently low value. Here we allow writes through to hardware,
  722. * but we set the floor to the physical device MPS setting, so that
  723. * we can at least use full TLPs, as defined by the MPS value.
  724. *
  725. * NB, if any devices actually depend on an artificially low MRRS
  726. * setting, this will need to be revisited, perhaps with a quirk
  727. * though pcie_set_readrq().
  728. */
  729. if (readrq != (le16_to_cpu(*ctrl) & PCI_EXP_DEVCTL_READRQ)) {
  730. readrq = 128 <<
  731. ((le16_to_cpu(*ctrl) & PCI_EXP_DEVCTL_READRQ) >> 12);
  732. readrq = max(readrq, pcie_get_mps(vdev->pdev));
  733. pcie_set_readrq(vdev->pdev, readrq);
  734. }
  735. return count;
  736. }
  737. /* Permissions for PCI Express capability */
  738. static int __init init_pci_cap_exp_perm(struct perm_bits *perm)
  739. {
  740. /* Alloc largest of possible sizes */
  741. if (alloc_perm_bits(perm, PCI_CAP_EXP_ENDPOINT_SIZEOF_V2))
  742. return -ENOMEM;
  743. perm->writefn = vfio_exp_config_write;
  744. p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
  745. /*
  746. * Allow writes to device control fields, except devctl_phantom,
  747. * which could confuse IOMMU, MPS, which can break communication
  748. * with other physical devices, and the ARI bit in devctl2, which
  749. * is set at probe time. FLR and MRRS get virtualized via our
  750. * writefn.
  751. */
  752. p_setw(perm, PCI_EXP_DEVCTL,
  753. PCI_EXP_DEVCTL_BCR_FLR | PCI_EXP_DEVCTL_PAYLOAD |
  754. PCI_EXP_DEVCTL_READRQ, ~PCI_EXP_DEVCTL_PHANTOM);
  755. p_setw(perm, PCI_EXP_DEVCTL2, NO_VIRT, ~PCI_EXP_DEVCTL2_ARI);
  756. return 0;
  757. }
  758. static int vfio_af_config_write(struct vfio_pci_device *vdev, int pos,
  759. int count, struct perm_bits *perm,
  760. int offset, __le32 val)
  761. {
  762. u8 *ctrl = vdev->vconfig + pos - offset + PCI_AF_CTRL;
  763. count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
  764. if (count < 0)
  765. return count;
  766. /*
  767. * The FLR bit is virtualized, if set and the device supports AF
  768. * FLR, issue a reset_function. Regardless, clear the bit, the spec
  769. * requires it to be always read as zero. NB, reset_function might
  770. * not use an AF FLR, we don't have that level of granularity.
  771. */
  772. if (*ctrl & PCI_AF_CTRL_FLR) {
  773. u8 cap;
  774. int ret;
  775. *ctrl &= ~PCI_AF_CTRL_FLR;
  776. ret = pci_user_read_config_byte(vdev->pdev,
  777. pos - offset + PCI_AF_CAP,
  778. &cap);
  779. if (!ret && (cap & PCI_AF_CAP_FLR) && (cap & PCI_AF_CAP_TP)) {
  780. vfio_pci_zap_and_down_write_memory_lock(vdev);
  781. pci_try_reset_function(vdev->pdev);
  782. up_write(&vdev->memory_lock);
  783. }
  784. }
  785. return count;
  786. }
  787. /* Permissions for Advanced Function capability */
  788. static int __init init_pci_cap_af_perm(struct perm_bits *perm)
  789. {
  790. if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_AF]))
  791. return -ENOMEM;
  792. perm->writefn = vfio_af_config_write;
  793. p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
  794. p_setb(perm, PCI_AF_CTRL, PCI_AF_CTRL_FLR, PCI_AF_CTRL_FLR);
  795. return 0;
  796. }
  797. /* Permissions for Advanced Error Reporting extended capability */
  798. static int __init init_pci_ext_cap_err_perm(struct perm_bits *perm)
  799. {
  800. u32 mask;
  801. if (alloc_perm_bits(perm, pci_ext_cap_length[PCI_EXT_CAP_ID_ERR]))
  802. return -ENOMEM;
  803. /*
  804. * Virtualize the first dword of all express capabilities
  805. * because it includes the next pointer. This lets us later
  806. * remove capabilities from the chain if we need to.
  807. */
  808. p_setd(perm, 0, ALL_VIRT, NO_WRITE);
  809. /* Writable bits mask */
  810. mask = PCI_ERR_UNC_UND | /* Undefined */
  811. PCI_ERR_UNC_DLP | /* Data Link Protocol */
  812. PCI_ERR_UNC_SURPDN | /* Surprise Down */
  813. PCI_ERR_UNC_POISON_TLP | /* Poisoned TLP */
  814. PCI_ERR_UNC_FCP | /* Flow Control Protocol */
  815. PCI_ERR_UNC_COMP_TIME | /* Completion Timeout */
  816. PCI_ERR_UNC_COMP_ABORT | /* Completer Abort */
  817. PCI_ERR_UNC_UNX_COMP | /* Unexpected Completion */
  818. PCI_ERR_UNC_RX_OVER | /* Receiver Overflow */
  819. PCI_ERR_UNC_MALF_TLP | /* Malformed TLP */
  820. PCI_ERR_UNC_ECRC | /* ECRC Error Status */
  821. PCI_ERR_UNC_UNSUP | /* Unsupported Request */
  822. PCI_ERR_UNC_ACSV | /* ACS Violation */
  823. PCI_ERR_UNC_INTN | /* internal error */
  824. PCI_ERR_UNC_MCBTLP | /* MC blocked TLP */
  825. PCI_ERR_UNC_ATOMEG | /* Atomic egress blocked */
  826. PCI_ERR_UNC_TLPPRE; /* TLP prefix blocked */
  827. p_setd(perm, PCI_ERR_UNCOR_STATUS, NO_VIRT, mask);
  828. p_setd(perm, PCI_ERR_UNCOR_MASK, NO_VIRT, mask);
  829. p_setd(perm, PCI_ERR_UNCOR_SEVER, NO_VIRT, mask);
  830. mask = PCI_ERR_COR_RCVR | /* Receiver Error Status */
  831. PCI_ERR_COR_BAD_TLP | /* Bad TLP Status */
  832. PCI_ERR_COR_BAD_DLLP | /* Bad DLLP Status */
  833. PCI_ERR_COR_REP_ROLL | /* REPLAY_NUM Rollover */
  834. PCI_ERR_COR_REP_TIMER | /* Replay Timer Timeout */
  835. PCI_ERR_COR_ADV_NFAT | /* Advisory Non-Fatal */
  836. PCI_ERR_COR_INTERNAL | /* Corrected Internal */
  837. PCI_ERR_COR_LOG_OVER; /* Header Log Overflow */
  838. p_setd(perm, PCI_ERR_COR_STATUS, NO_VIRT, mask);
  839. p_setd(perm, PCI_ERR_COR_MASK, NO_VIRT, mask);
  840. mask = PCI_ERR_CAP_ECRC_GENE | /* ECRC Generation Enable */
  841. PCI_ERR_CAP_ECRC_CHKE; /* ECRC Check Enable */
  842. p_setd(perm, PCI_ERR_CAP, NO_VIRT, mask);
  843. return 0;
  844. }
  845. /* Permissions for Power Budgeting extended capability */
  846. static int __init init_pci_ext_cap_pwr_perm(struct perm_bits *perm)
  847. {
  848. if (alloc_perm_bits(perm, pci_ext_cap_length[PCI_EXT_CAP_ID_PWR]))
  849. return -ENOMEM;
  850. p_setd(perm, 0, ALL_VIRT, NO_WRITE);
  851. /* Writing the data selector is OK, the info is still read-only */
  852. p_setb(perm, PCI_PWR_DATA, NO_VIRT, (u8)ALL_WRITE);
  853. return 0;
  854. }
  855. /*
  856. * Initialize the shared permission tables
  857. */
  858. void vfio_pci_uninit_perm_bits(void)
  859. {
  860. free_perm_bits(&cap_perms[PCI_CAP_ID_BASIC]);
  861. free_perm_bits(&cap_perms[PCI_CAP_ID_PM]);
  862. free_perm_bits(&cap_perms[PCI_CAP_ID_VPD]);
  863. free_perm_bits(&cap_perms[PCI_CAP_ID_PCIX]);
  864. free_perm_bits(&cap_perms[PCI_CAP_ID_EXP]);
  865. free_perm_bits(&cap_perms[PCI_CAP_ID_AF]);
  866. free_perm_bits(&ecap_perms[PCI_EXT_CAP_ID_ERR]);
  867. free_perm_bits(&ecap_perms[PCI_EXT_CAP_ID_PWR]);
  868. }
  869. int __init vfio_pci_init_perm_bits(void)
  870. {
  871. int ret;
  872. /* Basic config space */
  873. ret = init_pci_cap_basic_perm(&cap_perms[PCI_CAP_ID_BASIC]);
  874. /* Capabilities */
  875. ret |= init_pci_cap_pm_perm(&cap_perms[PCI_CAP_ID_PM]);
  876. ret |= init_pci_cap_vpd_perm(&cap_perms[PCI_CAP_ID_VPD]);
  877. ret |= init_pci_cap_pcix_perm(&cap_perms[PCI_CAP_ID_PCIX]);
  878. cap_perms[PCI_CAP_ID_VNDR].writefn = vfio_raw_config_write;
  879. ret |= init_pci_cap_exp_perm(&cap_perms[PCI_CAP_ID_EXP]);
  880. ret |= init_pci_cap_af_perm(&cap_perms[PCI_CAP_ID_AF]);
  881. /* Extended capabilities */
  882. ret |= init_pci_ext_cap_err_perm(&ecap_perms[PCI_EXT_CAP_ID_ERR]);
  883. ret |= init_pci_ext_cap_pwr_perm(&ecap_perms[PCI_EXT_CAP_ID_PWR]);
  884. ecap_perms[PCI_EXT_CAP_ID_VNDR].writefn = vfio_raw_config_write;
  885. if (ret)
  886. vfio_pci_uninit_perm_bits();
  887. return ret;
  888. }
  889. static int vfio_find_cap_start(struct vfio_pci_device *vdev, int pos)
  890. {
  891. u8 cap;
  892. int base = (pos >= PCI_CFG_SPACE_SIZE) ? PCI_CFG_SPACE_SIZE :
  893. PCI_STD_HEADER_SIZEOF;
  894. cap = vdev->pci_config_map[pos];
  895. if (cap == PCI_CAP_ID_BASIC)
  896. return 0;
  897. /* XXX Can we have to abutting capabilities of the same type? */
  898. while (pos - 1 >= base && vdev->pci_config_map[pos - 1] == cap)
  899. pos--;
  900. return pos;
  901. }
  902. static int vfio_msi_config_read(struct vfio_pci_device *vdev, int pos,
  903. int count, struct perm_bits *perm,
  904. int offset, __le32 *val)
  905. {
  906. /* Update max available queue size from msi_qmax */
  907. if (offset <= PCI_MSI_FLAGS && offset + count >= PCI_MSI_FLAGS) {
  908. __le16 *flags;
  909. int start;
  910. start = vfio_find_cap_start(vdev, pos);
  911. flags = (__le16 *)&vdev->vconfig[start];
  912. *flags &= cpu_to_le16(~PCI_MSI_FLAGS_QMASK);
  913. *flags |= cpu_to_le16(vdev->msi_qmax << 1);
  914. }
  915. return vfio_default_config_read(vdev, pos, count, perm, offset, val);
  916. }
  917. static int vfio_msi_config_write(struct vfio_pci_device *vdev, int pos,
  918. int count, struct perm_bits *perm,
  919. int offset, __le32 val)
  920. {
  921. count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
  922. if (count < 0)
  923. return count;
  924. /* Fixup and write configured queue size and enable to hardware */
  925. if (offset <= PCI_MSI_FLAGS && offset + count >= PCI_MSI_FLAGS) {
  926. __le16 *pflags;
  927. u16 flags;
  928. int start, ret;
  929. start = vfio_find_cap_start(vdev, pos);
  930. pflags = (__le16 *)&vdev->vconfig[start + PCI_MSI_FLAGS];
  931. flags = le16_to_cpu(*pflags);
  932. /* MSI is enabled via ioctl */
  933. if (!is_msi(vdev))
  934. flags &= ~PCI_MSI_FLAGS_ENABLE;
  935. /* Check queue size */
  936. if ((flags & PCI_MSI_FLAGS_QSIZE) >> 4 > vdev->msi_qmax) {
  937. flags &= ~PCI_MSI_FLAGS_QSIZE;
  938. flags |= vdev->msi_qmax << 4;
  939. }
  940. /* Write back to virt and to hardware */
  941. *pflags = cpu_to_le16(flags);
  942. ret = pci_user_write_config_word(vdev->pdev,
  943. start + PCI_MSI_FLAGS,
  944. flags);
  945. if (ret)
  946. return ret;
  947. }
  948. return count;
  949. }
  950. /*
  951. * MSI determination is per-device, so this routine gets used beyond
  952. * initialization time. Don't add __init
  953. */
  954. static int init_pci_cap_msi_perm(struct perm_bits *perm, int len, u16 flags)
  955. {
  956. if (alloc_perm_bits(perm, len))
  957. return -ENOMEM;
  958. perm->readfn = vfio_msi_config_read;
  959. perm->writefn = vfio_msi_config_write;
  960. p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
  961. /*
  962. * The upper byte of the control register is reserved,
  963. * just setup the lower byte.
  964. */
  965. p_setb(perm, PCI_MSI_FLAGS, (u8)ALL_VIRT, (u8)ALL_WRITE);
  966. p_setd(perm, PCI_MSI_ADDRESS_LO, ALL_VIRT, ALL_WRITE);
  967. if (flags & PCI_MSI_FLAGS_64BIT) {
  968. p_setd(perm, PCI_MSI_ADDRESS_HI, ALL_VIRT, ALL_WRITE);
  969. p_setw(perm, PCI_MSI_DATA_64, (u16)ALL_VIRT, (u16)ALL_WRITE);
  970. if (flags & PCI_MSI_FLAGS_MASKBIT) {
  971. p_setd(perm, PCI_MSI_MASK_64, NO_VIRT, ALL_WRITE);
  972. p_setd(perm, PCI_MSI_PENDING_64, NO_VIRT, ALL_WRITE);
  973. }
  974. } else {
  975. p_setw(perm, PCI_MSI_DATA_32, (u16)ALL_VIRT, (u16)ALL_WRITE);
  976. if (flags & PCI_MSI_FLAGS_MASKBIT) {
  977. p_setd(perm, PCI_MSI_MASK_32, NO_VIRT, ALL_WRITE);
  978. p_setd(perm, PCI_MSI_PENDING_32, NO_VIRT, ALL_WRITE);
  979. }
  980. }
  981. return 0;
  982. }
  983. /* Determine MSI CAP field length; initialize msi_perms on 1st call per vdev */
  984. static int vfio_msi_cap_len(struct vfio_pci_device *vdev, u8 pos)
  985. {
  986. struct pci_dev *pdev = vdev->pdev;
  987. int len, ret;
  988. u16 flags;
  989. ret = pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &flags);
  990. if (ret)
  991. return pcibios_err_to_errno(ret);
  992. len = 10; /* Minimum size */
  993. if (flags & PCI_MSI_FLAGS_64BIT)
  994. len += 4;
  995. if (flags & PCI_MSI_FLAGS_MASKBIT)
  996. len += 10;
  997. if (vdev->msi_perm)
  998. return len;
  999. vdev->msi_perm = kmalloc(sizeof(struct perm_bits), GFP_KERNEL);
  1000. if (!vdev->msi_perm)
  1001. return -ENOMEM;
  1002. ret = init_pci_cap_msi_perm(vdev->msi_perm, len, flags);
  1003. if (ret) {
  1004. kfree(vdev->msi_perm);
  1005. return ret;
  1006. }
  1007. return len;
  1008. }
  1009. /* Determine extended capability length for VC (2 & 9) and MFVC */
  1010. static int vfio_vc_cap_len(struct vfio_pci_device *vdev, u16 pos)
  1011. {
  1012. struct pci_dev *pdev = vdev->pdev;
  1013. u32 tmp;
  1014. int ret, evcc, phases, vc_arb;
  1015. int len = PCI_CAP_VC_BASE_SIZEOF;
  1016. ret = pci_read_config_dword(pdev, pos + PCI_VC_PORT_CAP1, &tmp);
  1017. if (ret)
  1018. return pcibios_err_to_errno(ret);
  1019. evcc = tmp & PCI_VC_CAP1_EVCC; /* extended vc count */
  1020. ret = pci_read_config_dword(pdev, pos + PCI_VC_PORT_CAP2, &tmp);
  1021. if (ret)
  1022. return pcibios_err_to_errno(ret);
  1023. if (tmp & PCI_VC_CAP2_128_PHASE)
  1024. phases = 128;
  1025. else if (tmp & PCI_VC_CAP2_64_PHASE)
  1026. phases = 64;
  1027. else if (tmp & PCI_VC_CAP2_32_PHASE)
  1028. phases = 32;
  1029. else
  1030. phases = 0;
  1031. vc_arb = phases * 4;
  1032. /*
  1033. * Port arbitration tables are root & switch only;
  1034. * function arbitration tables are function 0 only.
  1035. * In either case, we'll never let user write them so
  1036. * we don't care how big they are
  1037. */
  1038. len += (1 + evcc) * PCI_CAP_VC_PER_VC_SIZEOF;
  1039. if (vc_arb) {
  1040. len = round_up(len, 16);
  1041. len += vc_arb / 8;
  1042. }
  1043. return len;
  1044. }
  1045. static int vfio_cap_len(struct vfio_pci_device *vdev, u8 cap, u8 pos)
  1046. {
  1047. struct pci_dev *pdev = vdev->pdev;
  1048. u32 dword;
  1049. u16 word;
  1050. u8 byte;
  1051. int ret;
  1052. switch (cap) {
  1053. case PCI_CAP_ID_MSI:
  1054. return vfio_msi_cap_len(vdev, pos);
  1055. case PCI_CAP_ID_PCIX:
  1056. ret = pci_read_config_word(pdev, pos + PCI_X_CMD, &word);
  1057. if (ret)
  1058. return pcibios_err_to_errno(ret);
  1059. if (PCI_X_CMD_VERSION(word)) {
  1060. if (pdev->cfg_size > PCI_CFG_SPACE_SIZE) {
  1061. /* Test for extended capabilities */
  1062. pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE,
  1063. &dword);
  1064. vdev->extended_caps = (dword != 0);
  1065. }
  1066. return PCI_CAP_PCIX_SIZEOF_V2;
  1067. } else
  1068. return PCI_CAP_PCIX_SIZEOF_V0;
  1069. case PCI_CAP_ID_VNDR:
  1070. /* length follows next field */
  1071. ret = pci_read_config_byte(pdev, pos + PCI_CAP_FLAGS, &byte);
  1072. if (ret)
  1073. return pcibios_err_to_errno(ret);
  1074. return byte;
  1075. case PCI_CAP_ID_EXP:
  1076. if (pdev->cfg_size > PCI_CFG_SPACE_SIZE) {
  1077. /* Test for extended capabilities */
  1078. pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &dword);
  1079. vdev->extended_caps = (dword != 0);
  1080. }
  1081. /* length based on version and type */
  1082. if ((pcie_caps_reg(pdev) & PCI_EXP_FLAGS_VERS) == 1) {
  1083. if (pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END)
  1084. return 0xc; /* "All Devices" only, no link */
  1085. return PCI_CAP_EXP_ENDPOINT_SIZEOF_V1;
  1086. } else {
  1087. if (pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END)
  1088. return 0x2c; /* No link */
  1089. return PCI_CAP_EXP_ENDPOINT_SIZEOF_V2;
  1090. }
  1091. case PCI_CAP_ID_HT:
  1092. ret = pci_read_config_byte(pdev, pos + 3, &byte);
  1093. if (ret)
  1094. return pcibios_err_to_errno(ret);
  1095. return (byte & HT_3BIT_CAP_MASK) ?
  1096. HT_CAP_SIZEOF_SHORT : HT_CAP_SIZEOF_LONG;
  1097. case PCI_CAP_ID_SATA:
  1098. ret = pci_read_config_byte(pdev, pos + PCI_SATA_REGS, &byte);
  1099. if (ret)
  1100. return pcibios_err_to_errno(ret);
  1101. byte &= PCI_SATA_REGS_MASK;
  1102. if (byte == PCI_SATA_REGS_INLINE)
  1103. return PCI_SATA_SIZEOF_LONG;
  1104. else
  1105. return PCI_SATA_SIZEOF_SHORT;
  1106. default:
  1107. pr_warn("%s: %s unknown length for pci cap 0x%x@0x%x\n",
  1108. dev_name(&pdev->dev), __func__, cap, pos);
  1109. }
  1110. return 0;
  1111. }
  1112. static int vfio_ext_cap_len(struct vfio_pci_device *vdev, u16 ecap, u16 epos)
  1113. {
  1114. struct pci_dev *pdev = vdev->pdev;
  1115. u8 byte;
  1116. u32 dword;
  1117. int ret;
  1118. switch (ecap) {
  1119. case PCI_EXT_CAP_ID_VNDR:
  1120. ret = pci_read_config_dword(pdev, epos + PCI_VSEC_HDR, &dword);
  1121. if (ret)
  1122. return pcibios_err_to_errno(ret);
  1123. return dword >> PCI_VSEC_HDR_LEN_SHIFT;
  1124. case PCI_EXT_CAP_ID_VC:
  1125. case PCI_EXT_CAP_ID_VC9:
  1126. case PCI_EXT_CAP_ID_MFVC:
  1127. return vfio_vc_cap_len(vdev, epos);
  1128. case PCI_EXT_CAP_ID_ACS:
  1129. ret = pci_read_config_byte(pdev, epos + PCI_ACS_CAP, &byte);
  1130. if (ret)
  1131. return pcibios_err_to_errno(ret);
  1132. if (byte & PCI_ACS_EC) {
  1133. int bits;
  1134. ret = pci_read_config_byte(pdev,
  1135. epos + PCI_ACS_EGRESS_BITS,
  1136. &byte);
  1137. if (ret)
  1138. return pcibios_err_to_errno(ret);
  1139. bits = byte ? round_up(byte, 32) : 256;
  1140. return 8 + (bits / 8);
  1141. }
  1142. return 8;
  1143. case PCI_EXT_CAP_ID_REBAR:
  1144. ret = pci_read_config_byte(pdev, epos + PCI_REBAR_CTRL, &byte);
  1145. if (ret)
  1146. return pcibios_err_to_errno(ret);
  1147. byte &= PCI_REBAR_CTRL_NBAR_MASK;
  1148. byte >>= PCI_REBAR_CTRL_NBAR_SHIFT;
  1149. return 4 + (byte * 8);
  1150. case PCI_EXT_CAP_ID_DPA:
  1151. ret = pci_read_config_byte(pdev, epos + PCI_DPA_CAP, &byte);
  1152. if (ret)
  1153. return pcibios_err_to_errno(ret);
  1154. byte &= PCI_DPA_CAP_SUBSTATE_MASK;
  1155. return PCI_DPA_BASE_SIZEOF + byte + 1;
  1156. case PCI_EXT_CAP_ID_TPH:
  1157. ret = pci_read_config_dword(pdev, epos + PCI_TPH_CAP, &dword);
  1158. if (ret)
  1159. return pcibios_err_to_errno(ret);
  1160. if ((dword & PCI_TPH_CAP_LOC_MASK) == PCI_TPH_LOC_CAP) {
  1161. int sts;
  1162. sts = dword & PCI_TPH_CAP_ST_MASK;
  1163. sts >>= PCI_TPH_CAP_ST_SHIFT;
  1164. return PCI_TPH_BASE_SIZEOF + (sts * 2) + 2;
  1165. }
  1166. return PCI_TPH_BASE_SIZEOF;
  1167. default:
  1168. pr_warn("%s: %s unknown length for pci ecap 0x%x@0x%x\n",
  1169. dev_name(&pdev->dev), __func__, ecap, epos);
  1170. }
  1171. return 0;
  1172. }
  1173. static int vfio_fill_vconfig_bytes(struct vfio_pci_device *vdev,
  1174. int offset, int size)
  1175. {
  1176. struct pci_dev *pdev = vdev->pdev;
  1177. int ret = 0;
  1178. /*
  1179. * We try to read physical config space in the largest chunks
  1180. * we can, assuming that all of the fields support dword access.
  1181. * pci_save_state() makes this same assumption and seems to do ok.
  1182. */
  1183. while (size) {
  1184. int filled;
  1185. if (size >= 4 && !(offset % 4)) {
  1186. __le32 *dwordp = (__le32 *)&vdev->vconfig[offset];
  1187. u32 dword;
  1188. ret = pci_read_config_dword(pdev, offset, &dword);
  1189. if (ret)
  1190. return ret;
  1191. *dwordp = cpu_to_le32(dword);
  1192. filled = 4;
  1193. } else if (size >= 2 && !(offset % 2)) {
  1194. __le16 *wordp = (__le16 *)&vdev->vconfig[offset];
  1195. u16 word;
  1196. ret = pci_read_config_word(pdev, offset, &word);
  1197. if (ret)
  1198. return ret;
  1199. *wordp = cpu_to_le16(word);
  1200. filled = 2;
  1201. } else {
  1202. u8 *byte = &vdev->vconfig[offset];
  1203. ret = pci_read_config_byte(pdev, offset, byte);
  1204. if (ret)
  1205. return ret;
  1206. filled = 1;
  1207. }
  1208. offset += filled;
  1209. size -= filled;
  1210. }
  1211. return ret;
  1212. }
  1213. static int vfio_cap_init(struct vfio_pci_device *vdev)
  1214. {
  1215. struct pci_dev *pdev = vdev->pdev;
  1216. u8 *map = vdev->pci_config_map;
  1217. u16 status;
  1218. u8 pos, *prev, cap;
  1219. int loops, ret, caps = 0;
  1220. /* Any capabilities? */
  1221. ret = pci_read_config_word(pdev, PCI_STATUS, &status);
  1222. if (ret)
  1223. return ret;
  1224. if (!(status & PCI_STATUS_CAP_LIST))
  1225. return 0; /* Done */
  1226. ret = pci_read_config_byte(pdev, PCI_CAPABILITY_LIST, &pos);
  1227. if (ret)
  1228. return ret;
  1229. /* Mark the previous position in case we want to skip a capability */
  1230. prev = &vdev->vconfig[PCI_CAPABILITY_LIST];
  1231. /* We can bound our loop, capabilities are dword aligned */
  1232. loops = (PCI_CFG_SPACE_SIZE - PCI_STD_HEADER_SIZEOF) / PCI_CAP_SIZEOF;
  1233. while (pos && loops--) {
  1234. u8 next;
  1235. int i, len = 0;
  1236. ret = pci_read_config_byte(pdev, pos, &cap);
  1237. if (ret)
  1238. return ret;
  1239. ret = pci_read_config_byte(pdev,
  1240. pos + PCI_CAP_LIST_NEXT, &next);
  1241. if (ret)
  1242. return ret;
  1243. /*
  1244. * ID 0 is a NULL capability, conflicting with our fake
  1245. * PCI_CAP_ID_BASIC. As it has no content, consider it
  1246. * hidden for now.
  1247. */
  1248. if (cap && cap <= PCI_CAP_ID_MAX) {
  1249. len = pci_cap_length[cap];
  1250. if (len == 0xFF) { /* Variable length */
  1251. len = vfio_cap_len(vdev, cap, pos);
  1252. if (len < 0)
  1253. return len;
  1254. }
  1255. }
  1256. if (!len) {
  1257. pr_info("%s: %s hiding cap 0x%x\n",
  1258. __func__, dev_name(&pdev->dev), cap);
  1259. *prev = next;
  1260. pos = next;
  1261. continue;
  1262. }
  1263. /* Sanity check, do we overlap other capabilities? */
  1264. for (i = 0; i < len; i++) {
  1265. if (likely(map[pos + i] == PCI_CAP_ID_INVALID))
  1266. continue;
  1267. pr_warn("%s: %s pci config conflict @0x%x, was cap 0x%x now cap 0x%x\n",
  1268. __func__, dev_name(&pdev->dev),
  1269. pos + i, map[pos + i], cap);
  1270. }
  1271. BUILD_BUG_ON(PCI_CAP_ID_MAX >= PCI_CAP_ID_INVALID_VIRT);
  1272. memset(map + pos, cap, len);
  1273. ret = vfio_fill_vconfig_bytes(vdev, pos, len);
  1274. if (ret)
  1275. return ret;
  1276. prev = &vdev->vconfig[pos + PCI_CAP_LIST_NEXT];
  1277. pos = next;
  1278. caps++;
  1279. }
  1280. /* If we didn't fill any capabilities, clear the status flag */
  1281. if (!caps) {
  1282. __le16 *vstatus = (__le16 *)&vdev->vconfig[PCI_STATUS];
  1283. *vstatus &= ~cpu_to_le16(PCI_STATUS_CAP_LIST);
  1284. }
  1285. return 0;
  1286. }
  1287. static int vfio_ecap_init(struct vfio_pci_device *vdev)
  1288. {
  1289. struct pci_dev *pdev = vdev->pdev;
  1290. u8 *map = vdev->pci_config_map;
  1291. u16 epos;
  1292. __le32 *prev = NULL;
  1293. int loops, ret, ecaps = 0;
  1294. if (!vdev->extended_caps)
  1295. return 0;
  1296. epos = PCI_CFG_SPACE_SIZE;
  1297. loops = (pdev->cfg_size - PCI_CFG_SPACE_SIZE) / PCI_CAP_SIZEOF;
  1298. while (loops-- && epos >= PCI_CFG_SPACE_SIZE) {
  1299. u32 header;
  1300. u16 ecap;
  1301. int i, len = 0;
  1302. bool hidden = false;
  1303. ret = pci_read_config_dword(pdev, epos, &header);
  1304. if (ret)
  1305. return ret;
  1306. ecap = PCI_EXT_CAP_ID(header);
  1307. if (ecap <= PCI_EXT_CAP_ID_MAX) {
  1308. len = pci_ext_cap_length[ecap];
  1309. if (len == 0xFF) {
  1310. len = vfio_ext_cap_len(vdev, ecap, epos);
  1311. if (len < 0)
  1312. return ret;
  1313. }
  1314. }
  1315. if (!len) {
  1316. pr_info("%s: %s hiding ecap 0x%x@0x%x\n",
  1317. __func__, dev_name(&pdev->dev), ecap, epos);
  1318. /* If not the first in the chain, we can skip over it */
  1319. if (prev) {
  1320. u32 val = epos = PCI_EXT_CAP_NEXT(header);
  1321. *prev &= cpu_to_le32(~(0xffcU << 20));
  1322. *prev |= cpu_to_le32(val << 20);
  1323. continue;
  1324. }
  1325. /*
  1326. * Otherwise, fill in a placeholder, the direct
  1327. * readfn will virtualize this automatically
  1328. */
  1329. len = PCI_CAP_SIZEOF;
  1330. hidden = true;
  1331. }
  1332. for (i = 0; i < len; i++) {
  1333. if (likely(map[epos + i] == PCI_CAP_ID_INVALID))
  1334. continue;
  1335. pr_warn("%s: %s pci config conflict @0x%x, was ecap 0x%x now ecap 0x%x\n",
  1336. __func__, dev_name(&pdev->dev),
  1337. epos + i, map[epos + i], ecap);
  1338. }
  1339. /*
  1340. * Even though ecap is 2 bytes, we're currently a long way
  1341. * from exceeding 1 byte capabilities. If we ever make it
  1342. * up to 0xFE we'll need to up this to a two-byte, byte map.
  1343. */
  1344. BUILD_BUG_ON(PCI_EXT_CAP_ID_MAX >= PCI_CAP_ID_INVALID_VIRT);
  1345. memset(map + epos, ecap, len);
  1346. ret = vfio_fill_vconfig_bytes(vdev, epos, len);
  1347. if (ret)
  1348. return ret;
  1349. /*
  1350. * If we're just using this capability to anchor the list,
  1351. * hide the real ID. Only count real ecaps. XXX PCI spec
  1352. * indicates to use cap id = 0, version = 0, next = 0 if
  1353. * ecaps are absent, hope users check all the way to next.
  1354. */
  1355. if (hidden)
  1356. *(__le32 *)&vdev->vconfig[epos] &=
  1357. cpu_to_le32((0xffcU << 20));
  1358. else
  1359. ecaps++;
  1360. prev = (__le32 *)&vdev->vconfig[epos];
  1361. epos = PCI_EXT_CAP_NEXT(header);
  1362. }
  1363. if (!ecaps)
  1364. *(u32 *)&vdev->vconfig[PCI_CFG_SPACE_SIZE] = 0;
  1365. return 0;
  1366. }
  1367. /*
  1368. * Nag about hardware bugs, hopefully to have vendors fix them, but at least
  1369. * to collect a list of dependencies for the VF INTx pin quirk below.
  1370. */
  1371. static const struct pci_device_id known_bogus_vf_intx_pin[] = {
  1372. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x270c) },
  1373. {}
  1374. };
  1375. /*
  1376. * For each device we allocate a pci_config_map that indicates the
  1377. * capability occupying each dword and thus the struct perm_bits we
  1378. * use for read and write. We also allocate a virtualized config
  1379. * space which tracks reads and writes to bits that we emulate for
  1380. * the user. Initial values filled from device.
  1381. *
  1382. * Using shared struct perm_bits between all vfio-pci devices saves
  1383. * us from allocating cfg_size buffers for virt and write for every
  1384. * device. We could remove vconfig and allocate individual buffers
  1385. * for each area requiring emulated bits, but the array of pointers
  1386. * would be comparable in size (at least for standard config space).
  1387. */
  1388. int vfio_config_init(struct vfio_pci_device *vdev)
  1389. {
  1390. struct pci_dev *pdev = vdev->pdev;
  1391. u8 *map, *vconfig;
  1392. int ret;
  1393. /*
  1394. * Config space, caps and ecaps are all dword aligned, so we could
  1395. * use one byte per dword to record the type. However, there are
  1396. * no requiremenst on the length of a capability, so the gap between
  1397. * capabilities needs byte granularity.
  1398. */
  1399. map = kmalloc(pdev->cfg_size, GFP_KERNEL);
  1400. if (!map)
  1401. return -ENOMEM;
  1402. vconfig = kmalloc(pdev->cfg_size, GFP_KERNEL);
  1403. if (!vconfig) {
  1404. kfree(map);
  1405. return -ENOMEM;
  1406. }
  1407. vdev->pci_config_map = map;
  1408. vdev->vconfig = vconfig;
  1409. memset(map, PCI_CAP_ID_BASIC, PCI_STD_HEADER_SIZEOF);
  1410. memset(map + PCI_STD_HEADER_SIZEOF, PCI_CAP_ID_INVALID,
  1411. pdev->cfg_size - PCI_STD_HEADER_SIZEOF);
  1412. ret = vfio_fill_vconfig_bytes(vdev, 0, PCI_STD_HEADER_SIZEOF);
  1413. if (ret)
  1414. goto out;
  1415. vdev->bardirty = true;
  1416. /*
  1417. * XXX can we just pci_load_saved_state/pci_restore_state?
  1418. * may need to rebuild vconfig after that
  1419. */
  1420. /* For restore after reset */
  1421. vdev->rbar[0] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_0]);
  1422. vdev->rbar[1] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_1]);
  1423. vdev->rbar[2] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_2]);
  1424. vdev->rbar[3] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_3]);
  1425. vdev->rbar[4] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_4]);
  1426. vdev->rbar[5] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_5]);
  1427. vdev->rbar[6] = le32_to_cpu(*(__le32 *)&vconfig[PCI_ROM_ADDRESS]);
  1428. if (pdev->is_virtfn) {
  1429. *(__le16 *)&vconfig[PCI_VENDOR_ID] = cpu_to_le16(pdev->vendor);
  1430. *(__le16 *)&vconfig[PCI_DEVICE_ID] = cpu_to_le16(pdev->device);
  1431. /*
  1432. * Per SR-IOV spec rev 1.1, 3.4.1.18 the interrupt pin register
  1433. * does not apply to VFs and VFs must implement this register
  1434. * as read-only with value zero. Userspace is not readily able
  1435. * to identify whether a device is a VF and thus that the pin
  1436. * definition on the device is bogus should it violate this
  1437. * requirement. We already virtualize the pin register for
  1438. * other purposes, so we simply need to replace the bogus value
  1439. * and consider VFs when we determine INTx IRQ count.
  1440. */
  1441. if (vconfig[PCI_INTERRUPT_PIN] &&
  1442. !pci_match_id(known_bogus_vf_intx_pin, pdev))
  1443. pci_warn(pdev,
  1444. "Hardware bug: VF reports bogus INTx pin %d\n",
  1445. vconfig[PCI_INTERRUPT_PIN]);
  1446. vconfig[PCI_INTERRUPT_PIN] = 0; /* Gratuitous for good VFs */
  1447. /*
  1448. * VFs do no implement the memory enable bit of the COMMAND
  1449. * register therefore we'll not have it set in our initial
  1450. * copy of config space after pci_enable_device(). For
  1451. * consistency with PFs, set the virtual enable bit here.
  1452. */
  1453. *(__le16 *)&vconfig[PCI_COMMAND] |=
  1454. cpu_to_le16(PCI_COMMAND_MEMORY);
  1455. }
  1456. if (!IS_ENABLED(CONFIG_VFIO_PCI_INTX) || vdev->nointx)
  1457. vconfig[PCI_INTERRUPT_PIN] = 0;
  1458. ret = vfio_cap_init(vdev);
  1459. if (ret)
  1460. goto out;
  1461. ret = vfio_ecap_init(vdev);
  1462. if (ret)
  1463. goto out;
  1464. return 0;
  1465. out:
  1466. kfree(map);
  1467. vdev->pci_config_map = NULL;
  1468. kfree(vconfig);
  1469. vdev->vconfig = NULL;
  1470. return pcibios_err_to_errno(ret);
  1471. }
  1472. void vfio_config_free(struct vfio_pci_device *vdev)
  1473. {
  1474. kfree(vdev->vconfig);
  1475. vdev->vconfig = NULL;
  1476. kfree(vdev->pci_config_map);
  1477. vdev->pci_config_map = NULL;
  1478. if (vdev->msi_perm) {
  1479. free_perm_bits(vdev->msi_perm);
  1480. kfree(vdev->msi_perm);
  1481. vdev->msi_perm = NULL;
  1482. }
  1483. }
  1484. /*
  1485. * Find the remaining number of bytes in a dword that match the given
  1486. * position. Stop at either the end of the capability or the dword boundary.
  1487. */
  1488. static size_t vfio_pci_cap_remaining_dword(struct vfio_pci_device *vdev,
  1489. loff_t pos)
  1490. {
  1491. u8 cap = vdev->pci_config_map[pos];
  1492. size_t i;
  1493. for (i = 1; (pos + i) % 4 && vdev->pci_config_map[pos + i] == cap; i++)
  1494. /* nop */;
  1495. return i;
  1496. }
  1497. static ssize_t vfio_config_do_rw(struct vfio_pci_device *vdev, char __user *buf,
  1498. size_t count, loff_t *ppos, bool iswrite)
  1499. {
  1500. struct pci_dev *pdev = vdev->pdev;
  1501. struct perm_bits *perm;
  1502. __le32 val = 0;
  1503. int cap_start = 0, offset;
  1504. u8 cap_id;
  1505. ssize_t ret;
  1506. if (*ppos < 0 || *ppos >= pdev->cfg_size ||
  1507. *ppos + count > pdev->cfg_size)
  1508. return -EFAULT;
  1509. /*
  1510. * Chop accesses into aligned chunks containing no more than a
  1511. * single capability. Caller increments to the next chunk.
  1512. */
  1513. count = min(count, vfio_pci_cap_remaining_dword(vdev, *ppos));
  1514. if (count >= 4 && !(*ppos % 4))
  1515. count = 4;
  1516. else if (count >= 2 && !(*ppos % 2))
  1517. count = 2;
  1518. else
  1519. count = 1;
  1520. ret = count;
  1521. cap_id = vdev->pci_config_map[*ppos];
  1522. if (cap_id == PCI_CAP_ID_INVALID) {
  1523. perm = &unassigned_perms;
  1524. cap_start = *ppos;
  1525. } else if (cap_id == PCI_CAP_ID_INVALID_VIRT) {
  1526. perm = &virt_perms;
  1527. cap_start = *ppos;
  1528. } else {
  1529. if (*ppos >= PCI_CFG_SPACE_SIZE) {
  1530. WARN_ON(cap_id > PCI_EXT_CAP_ID_MAX);
  1531. perm = &ecap_perms[cap_id];
  1532. cap_start = vfio_find_cap_start(vdev, *ppos);
  1533. } else {
  1534. WARN_ON(cap_id > PCI_CAP_ID_MAX);
  1535. perm = &cap_perms[cap_id];
  1536. if (cap_id == PCI_CAP_ID_MSI)
  1537. perm = vdev->msi_perm;
  1538. if (cap_id > PCI_CAP_ID_BASIC)
  1539. cap_start = vfio_find_cap_start(vdev, *ppos);
  1540. }
  1541. }
  1542. WARN_ON(!cap_start && cap_id != PCI_CAP_ID_BASIC);
  1543. WARN_ON(cap_start > *ppos);
  1544. offset = *ppos - cap_start;
  1545. if (iswrite) {
  1546. if (!perm->writefn)
  1547. return ret;
  1548. if (copy_from_user(&val, buf, count))
  1549. return -EFAULT;
  1550. ret = perm->writefn(vdev, *ppos, count, perm, offset, val);
  1551. } else {
  1552. if (perm->readfn) {
  1553. ret = perm->readfn(vdev, *ppos, count,
  1554. perm, offset, &val);
  1555. if (ret < 0)
  1556. return ret;
  1557. }
  1558. if (copy_to_user(buf, &val, count))
  1559. return -EFAULT;
  1560. }
  1561. return ret;
  1562. }
  1563. ssize_t vfio_pci_config_rw(struct vfio_pci_device *vdev, char __user *buf,
  1564. size_t count, loff_t *ppos, bool iswrite)
  1565. {
  1566. size_t done = 0;
  1567. int ret = 0;
  1568. loff_t pos = *ppos;
  1569. pos &= VFIO_PCI_OFFSET_MASK;
  1570. while (count) {
  1571. ret = vfio_config_do_rw(vdev, buf, count, &pos, iswrite);
  1572. if (ret < 0)
  1573. return ret;
  1574. count -= ret;
  1575. done += ret;
  1576. buf += ret;
  1577. pos += ret;
  1578. }
  1579. *ppos += done;
  1580. return done;
  1581. }