3c120_devboard.dts 4.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2013 Altera Corporation
  4. *
  5. * This file is generated by sopc2dts.
  6. */
  7. /dts-v1/;
  8. / {
  9. model = "altr,qsys_ghrd_3c120";
  10. compatible = "altr,qsys_ghrd_3c120";
  11. #address-cells = <1>;
  12. #size-cells = <1>;
  13. cpus {
  14. #address-cells = <1>;
  15. #size-cells = <0>;
  16. cpu: cpu@0x0 {
  17. device_type = "cpu";
  18. compatible = "altr,nios2-1.0";
  19. reg = <0x00000000>;
  20. interrupt-controller;
  21. #interrupt-cells = <1>;
  22. clock-frequency = <125000000>;
  23. dcache-line-size = <32>;
  24. icache-line-size = <32>;
  25. dcache-size = <32768>;
  26. icache-size = <32768>;
  27. altr,implementation = "fast";
  28. altr,pid-num-bits = <8>;
  29. altr,tlb-num-ways = <16>;
  30. altr,tlb-num-entries = <128>;
  31. altr,tlb-ptr-sz = <7>;
  32. altr,has-div = <1>;
  33. altr,has-mul = <1>;
  34. altr,reset-addr = <0xc2800000>;
  35. altr,fast-tlb-miss-addr = <0xc7fff400>;
  36. altr,exception-addr = <0xd0000020>;
  37. altr,has-initda = <1>;
  38. altr,has-mmu = <1>;
  39. };
  40. };
  41. memory@0 {
  42. device_type = "memory";
  43. reg = <0x10000000 0x08000000>,
  44. <0x07fff400 0x00000400>;
  45. };
  46. sopc@0 {
  47. device_type = "soc";
  48. ranges;
  49. #address-cells = <1>;
  50. #size-cells = <1>;
  51. compatible = "altr,avalon", "simple-bus";
  52. bus-frequency = <125000000>;
  53. pb_cpu_to_io: bridge@0x8000000 {
  54. compatible = "simple-bus";
  55. reg = <0x08000000 0x00800000>;
  56. #address-cells = <1>;
  57. #size-cells = <1>;
  58. ranges = <0x00002000 0x08002000 0x00002000>,
  59. <0x00004000 0x08004000 0x00000400>,
  60. <0x00004400 0x08004400 0x00000040>,
  61. <0x00004800 0x08004800 0x00000040>,
  62. <0x00004c80 0x08004c80 0x00000020>,
  63. <0x00004cc0 0x08004cc0 0x00000010>,
  64. <0x00004ce0 0x08004ce0 0x00000010>,
  65. <0x00004d00 0x08004d00 0x00000010>,
  66. <0x00004d40 0x08004d40 0x00000008>,
  67. <0x00004d50 0x08004d50 0x00000008>,
  68. <0x00008000 0x08008000 0x00000020>,
  69. <0x00400000 0x08400000 0x00000020>;
  70. timer_1ms: timer@0x400000 {
  71. compatible = "altr,timer-1.0";
  72. reg = <0x00400000 0x00000020>;
  73. interrupt-parent = <&cpu>;
  74. interrupts = <11>;
  75. clock-frequency = <125000000>;
  76. };
  77. timer_0: timer@0x8000 {
  78. compatible = "altr,timer-1.0";
  79. reg = < 0x00008000 0x00000020 >;
  80. interrupt-parent = < &cpu >;
  81. interrupts = < 5 >;
  82. clock-frequency = < 125000000 >;
  83. };
  84. sysid: sysid@0x4d40 {
  85. compatible = "altr,sysid-1.0";
  86. reg = <0x00004d40 0x00000008>;
  87. };
  88. jtag_uart: serial@0x4d50 {
  89. compatible = "altr,juart-1.0";
  90. reg = <0x00004d50 0x00000008>;
  91. interrupt-parent = <&cpu>;
  92. interrupts = <1>;
  93. };
  94. tse_mac: ethernet@0x4000 {
  95. compatible = "altr,tse-1.0";
  96. reg = <0x00004000 0x00000400>,
  97. <0x00004400 0x00000040>,
  98. <0x00004800 0x00000040>,
  99. <0x00002000 0x00002000>;
  100. reg-names = "control_port", "rx_csr", "tx_csr", "s1";
  101. interrupt-parent = <&cpu>;
  102. interrupts = <2 3>;
  103. interrupt-names = "rx_irq", "tx_irq";
  104. rx-fifo-depth = <8192>;
  105. tx-fifo-depth = <8192>;
  106. max-frame-size = <1518>;
  107. local-mac-address = [ 00 00 00 00 00 00 ];
  108. phy-mode = "rgmii-id";
  109. phy-handle = <&phy0>;
  110. tse_mac_mdio: mdio {
  111. compatible = "altr,tse-mdio";
  112. #address-cells = <1>;
  113. #size-cells = <0>;
  114. phy0: ethernet-phy@18 {
  115. reg = <18>;
  116. device_type = "ethernet-phy";
  117. };
  118. };
  119. };
  120. uart: serial@0x4c80 {
  121. compatible = "altr,uart-1.0";
  122. reg = <0x00004c80 0x00000020>;
  123. interrupt-parent = <&cpu>;
  124. interrupts = <10>;
  125. current-speed = <115200>;
  126. clock-frequency = <62500000>;
  127. };
  128. user_led_pio_8out: gpio@0x4cc0 {
  129. compatible = "altr,pio-1.0";
  130. reg = <0x00004cc0 0x00000010>;
  131. resetvalue = <255>;
  132. altr,gpio-bank-width = <8>;
  133. #gpio-cells = <2>;
  134. gpio-controller;
  135. gpio-bank-name = "led";
  136. };
  137. user_dipsw_pio_8in: gpio@0x4ce0 {
  138. compatible = "altr,pio-1.0";
  139. reg = <0x00004ce0 0x00000010>;
  140. interrupt-parent = <&cpu>;
  141. interrupts = <8>;
  142. edge_type = <2>;
  143. level_trigger = <0>;
  144. resetvalue = <0>;
  145. altr,gpio-bank-width = <8>;
  146. #gpio-cells = <2>;
  147. gpio-controller;
  148. gpio-bank-name = "dipsw";
  149. };
  150. user_pb_pio_4in: gpio@0x4d00 {
  151. compatible = "altr,pio-1.0";
  152. reg = <0x00004d00 0x00000010>;
  153. interrupt-parent = <&cpu>;
  154. interrupts = <9>;
  155. edge_type = <2>;
  156. level_trigger = <0>;
  157. resetvalue = <0>;
  158. altr,gpio-bank-width = <4>;
  159. #gpio-cells = <2>;
  160. gpio-controller;
  161. gpio-bank-name = "pb";
  162. };
  163. };
  164. cfi_flash_64m: flash@0x0 {
  165. compatible = "cfi-flash";
  166. reg = <0x00000000 0x04000000>;
  167. bank-width = <2>;
  168. device-width = <1>;
  169. #address-cells = <1>;
  170. #size-cells = <1>;
  171. partition@800000 {
  172. reg = <0x00800000 0x01e00000>;
  173. label = "JFFS2 Filesystem";
  174. };
  175. };
  176. };
  177. chosen {
  178. bootargs = "debug console=ttyJ0,115200";
  179. stdout-path = &jtag_uart;
  180. };
  181. };