pch7.c 2.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014 Google, Inc
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <pch.h>
  8. #define GPIO_BASE 0x44
  9. #define BIOS_CTRL 0xd8
  10. static int pch7_get_spi_base(struct udevice *dev, ulong *sbasep)
  11. {
  12. u32 rcba;
  13. dm_pci_read_config32(dev, PCH_RCBA, &rcba);
  14. /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */
  15. rcba = rcba & 0xffffc000;
  16. *sbasep = rcba + 0x3020;
  17. return 0;
  18. }
  19. static int pch7_set_spi_protect(struct udevice *dev, bool protect)
  20. {
  21. uint8_t bios_cntl;
  22. /* Adjust the BIOS write protect to dis/allow write commands */
  23. dm_pci_read_config8(dev, BIOS_CTRL, &bios_cntl);
  24. if (protect)
  25. bios_cntl &= ~BIOS_CTRL_BIOSWE;
  26. else
  27. bios_cntl |= BIOS_CTRL_BIOSWE;
  28. dm_pci_write_config8(dev, BIOS_CTRL, bios_cntl);
  29. return 0;
  30. }
  31. static int pch7_get_gpio_base(struct udevice *dev, u32 *gbasep)
  32. {
  33. u32 base;
  34. /*
  35. * GPIO_BASE moved to its current offset with ICH6, but prior to
  36. * that it was unused (or undocumented). Check that it looks
  37. * okay: not all ones or zeros.
  38. *
  39. * Note we don't need check bit0 here, because the Tunnel Creek
  40. * GPIO base address register bit0 is reserved (read returns 0),
  41. * while on the Ivybridge the bit0 is used to indicate it is an
  42. * I/O space.
  43. */
  44. dm_pci_read_config32(dev, GPIO_BASE, &base);
  45. if (base == 0x00000000 || base == 0xffffffff) {
  46. debug("%s: unexpected BASE value\n", __func__);
  47. return -ENODEV;
  48. }
  49. /*
  50. * Okay, I guess we're looking at the right device. The actual
  51. * GPIO registers are in the PCI device's I/O space, starting
  52. * at the offset that we just read. Bit 0 indicates that it's
  53. * an I/O address, not a memory address, so mask that off.
  54. */
  55. *gbasep = base & 1 ? base & ~3 : base & ~15;
  56. return 0;
  57. }
  58. static const struct pch_ops pch7_ops = {
  59. .get_spi_base = pch7_get_spi_base,
  60. .set_spi_protect = pch7_set_spi_protect,
  61. .get_gpio_base = pch7_get_gpio_base,
  62. };
  63. static const struct udevice_id pch7_ids[] = {
  64. { .compatible = "intel,pch7" },
  65. { }
  66. };
  67. U_BOOT_DRIVER(pch7_drv) = {
  68. .name = "intel-pch7",
  69. .id = UCLASS_PCH,
  70. .of_match = pch7_ids,
  71. .ops = &pch7_ops,
  72. };