fotg210.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Faraday USB 2.0 OTG Controller
  4. *
  5. * (C) Copyright 2010 Faraday Technology
  6. * Dante Su <dantesu@faraday-tech.com>
  7. */
  8. #include <common.h>
  9. #include <command.h>
  10. #include <config.h>
  11. #include <net.h>
  12. #include <malloc.h>
  13. #include <asm/io.h>
  14. #include <linux/errno.h>
  15. #include <linux/types.h>
  16. #include <linux/usb/ch9.h>
  17. #include <linux/usb/gadget.h>
  18. #include <usb/fotg210.h>
  19. #define CFG_NUM_ENDPOINTS 4
  20. #define CFG_EP0_MAX_PACKET_SIZE 64
  21. #define CFG_EPX_MAX_PACKET_SIZE 512
  22. #define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 2) /* 250 ms */
  23. struct fotg210_chip;
  24. struct fotg210_ep {
  25. struct usb_ep ep;
  26. uint maxpacket;
  27. uint id;
  28. uint stopped;
  29. struct list_head queue;
  30. struct fotg210_chip *chip;
  31. const struct usb_endpoint_descriptor *desc;
  32. };
  33. struct fotg210_request {
  34. struct usb_request req;
  35. struct list_head queue;
  36. struct fotg210_ep *ep;
  37. };
  38. struct fotg210_chip {
  39. struct usb_gadget gadget;
  40. struct usb_gadget_driver *driver;
  41. struct fotg210_regs *regs;
  42. uint8_t irq;
  43. uint16_t addr;
  44. int pullup;
  45. enum usb_device_state state;
  46. struct fotg210_ep ep[1 + CFG_NUM_ENDPOINTS];
  47. };
  48. static struct usb_endpoint_descriptor ep0_desc = {
  49. .bLength = sizeof(struct usb_endpoint_descriptor),
  50. .bDescriptorType = USB_DT_ENDPOINT,
  51. .bEndpointAddress = USB_DIR_IN,
  52. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  53. };
  54. static inline int fifo_to_ep(struct fotg210_chip *chip, int id, int in)
  55. {
  56. return (id < 0) ? 0 : ((id & 0x03) + 1);
  57. }
  58. static inline int ep_to_fifo(struct fotg210_chip *chip, int id)
  59. {
  60. return (id <= 0) ? -1 : ((id - 1) & 0x03);
  61. }
  62. static inline int ep_reset(struct fotg210_chip *chip, uint8_t ep_addr)
  63. {
  64. int ep = ep_addr & USB_ENDPOINT_NUMBER_MASK;
  65. struct fotg210_regs *regs = chip->regs;
  66. if (ep_addr & USB_DIR_IN) {
  67. /* reset endpoint */
  68. setbits_le32(&regs->iep[ep - 1], IEP_RESET);
  69. mdelay(1);
  70. clrbits_le32(&regs->iep[ep - 1], IEP_RESET);
  71. /* clear endpoint stall */
  72. clrbits_le32(&regs->iep[ep - 1], IEP_STALL);
  73. } else {
  74. /* reset endpoint */
  75. setbits_le32(&regs->oep[ep - 1], OEP_RESET);
  76. mdelay(1);
  77. clrbits_le32(&regs->oep[ep - 1], OEP_RESET);
  78. /* clear endpoint stall */
  79. clrbits_le32(&regs->oep[ep - 1], OEP_STALL);
  80. }
  81. return 0;
  82. }
  83. static int fotg210_reset(struct fotg210_chip *chip)
  84. {
  85. struct fotg210_regs *regs = chip->regs;
  86. uint32_t i;
  87. chip->state = USB_STATE_POWERED;
  88. /* chip enable */
  89. writel(DEVCTRL_EN, &regs->dev_ctrl);
  90. /* device address reset */
  91. chip->addr = 0;
  92. writel(0, &regs->dev_addr);
  93. /* set idle counter to 7ms */
  94. writel(7, &regs->idle);
  95. /* disable all interrupts */
  96. writel(IMR_MASK, &regs->imr);
  97. writel(GIMR_MASK, &regs->gimr);
  98. writel(GIMR0_MASK, &regs->gimr0);
  99. writel(GIMR1_MASK, &regs->gimr1);
  100. writel(GIMR2_MASK, &regs->gimr2);
  101. /* clear interrupts */
  102. writel(ISR_MASK, &regs->isr);
  103. writel(0, &regs->gisr);
  104. writel(0, &regs->gisr0);
  105. writel(0, &regs->gisr1);
  106. writel(0, &regs->gisr2);
  107. /* chip reset */
  108. setbits_le32(&regs->dev_ctrl, DEVCTRL_RESET);
  109. mdelay(10);
  110. if (readl(&regs->dev_ctrl) & DEVCTRL_RESET) {
  111. printf("fotg210: chip reset failed\n");
  112. return -1;
  113. }
  114. /* CX FIFO reset */
  115. setbits_le32(&regs->cxfifo, CXFIFO_CXFIFOCLR);
  116. mdelay(10);
  117. if (readl(&regs->cxfifo) & CXFIFO_CXFIFOCLR) {
  118. printf("fotg210: ep0 fifo reset failed\n");
  119. return -1;
  120. }
  121. /* create static ep-fifo map (EP1 <-> FIFO0, EP2 <-> FIFO1 ...) */
  122. writel(EPMAP14_DEFAULT, &regs->epmap14);
  123. writel(EPMAP58_DEFAULT, &regs->epmap58);
  124. writel(FIFOMAP_DEFAULT, &regs->fifomap);
  125. writel(0, &regs->fifocfg);
  126. for (i = 0; i < 8; ++i) {
  127. writel(CFG_EPX_MAX_PACKET_SIZE, &regs->iep[i]);
  128. writel(CFG_EPX_MAX_PACKET_SIZE, &regs->oep[i]);
  129. }
  130. /* FIFO reset */
  131. for (i = 0; i < 4; ++i) {
  132. writel(FIFOCSR_RESET, &regs->fifocsr[i]);
  133. mdelay(10);
  134. if (readl(&regs->fifocsr[i]) & FIFOCSR_RESET) {
  135. printf("fotg210: fifo%d reset failed\n", i);
  136. return -1;
  137. }
  138. }
  139. /* enable only device interrupt and triggered at level-high */
  140. writel(IMR_IRQLH | IMR_HOST | IMR_OTG, &regs->imr);
  141. writel(ISR_MASK, &regs->isr);
  142. /* disable EP0 IN/OUT interrupt */
  143. writel(GIMR0_CXOUT | GIMR0_CXIN, &regs->gimr0);
  144. /* disable EPX IN+SPK+OUT interrupts */
  145. writel(GIMR1_MASK, &regs->gimr1);
  146. /* disable wakeup+idle+dma+zlp interrupts */
  147. writel(GIMR2_WAKEUP | GIMR2_IDLE | GIMR2_DMAERR | GIMR2_DMAFIN
  148. | GIMR2_ZLPRX | GIMR2_ZLPTX, &regs->gimr2);
  149. /* enable all group interrupt */
  150. writel(0, &regs->gimr);
  151. /* suspend delay = 3 ms */
  152. writel(3, &regs->idle);
  153. /* turn-on device interrupts */
  154. setbits_le32(&regs->dev_ctrl, DEVCTRL_GIRQ_EN);
  155. return 0;
  156. }
  157. static inline int fotg210_cxwait(struct fotg210_chip *chip, uint32_t mask)
  158. {
  159. struct fotg210_regs *regs = chip->regs;
  160. int ret = -1;
  161. ulong ts;
  162. for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
  163. if ((readl(&regs->cxfifo) & mask) != mask)
  164. continue;
  165. ret = 0;
  166. break;
  167. }
  168. if (ret)
  169. printf("fotg210: cx/ep0 timeout\n");
  170. return ret;
  171. }
  172. static int fotg210_dma(struct fotg210_ep *ep, struct fotg210_request *req)
  173. {
  174. struct fotg210_chip *chip = ep->chip;
  175. struct fotg210_regs *regs = chip->regs;
  176. uint32_t tmp, ts;
  177. uint8_t *buf = req->req.buf + req->req.actual;
  178. uint32_t len = req->req.length - req->req.actual;
  179. int fifo = ep_to_fifo(chip, ep->id);
  180. int ret = -EBUSY;
  181. /* 1. init dma buffer */
  182. if (len > ep->maxpacket)
  183. len = ep->maxpacket;
  184. /* 2. wait for dma ready (hardware) */
  185. for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
  186. if (!(readl(&regs->dma_ctrl) & DMACTRL_START)) {
  187. ret = 0;
  188. break;
  189. }
  190. }
  191. if (ret) {
  192. printf("fotg210: dma busy\n");
  193. req->req.status = ret;
  194. return ret;
  195. }
  196. /* 3. DMA target setup */
  197. if (ep->desc->bEndpointAddress & USB_DIR_IN)
  198. flush_dcache_range((ulong)buf, (ulong)buf + len);
  199. else
  200. invalidate_dcache_range((ulong)buf, (ulong)buf + len);
  201. writel(virt_to_phys(buf), &regs->dma_addr);
  202. if (ep->desc->bEndpointAddress & USB_DIR_IN) {
  203. if (ep->id == 0) {
  204. /* Wait until cx/ep0 fifo empty */
  205. fotg210_cxwait(chip, CXFIFO_CXFIFOE);
  206. udelay(1);
  207. writel(DMAFIFO_CX, &regs->dma_fifo);
  208. } else {
  209. /* Wait until epx fifo empty */
  210. fotg210_cxwait(chip, CXFIFO_FIFOE(fifo));
  211. writel(DMAFIFO_FIFO(fifo), &regs->dma_fifo);
  212. }
  213. writel(DMACTRL_LEN(len) | DMACTRL_MEM2FIFO, &regs->dma_ctrl);
  214. } else {
  215. uint32_t blen;
  216. if (ep->id == 0) {
  217. writel(DMAFIFO_CX, &regs->dma_fifo);
  218. do {
  219. blen = CXFIFO_BYTES(readl(&regs->cxfifo));
  220. } while (blen < len);
  221. } else {
  222. writel(DMAFIFO_FIFO(fifo), &regs->dma_fifo);
  223. blen = FIFOCSR_BYTES(readl(&regs->fifocsr[fifo]));
  224. }
  225. len = (len < blen) ? len : blen;
  226. writel(DMACTRL_LEN(len) | DMACTRL_FIFO2MEM, &regs->dma_ctrl);
  227. }
  228. /* 4. DMA start */
  229. setbits_le32(&regs->dma_ctrl, DMACTRL_START);
  230. /* 5. DMA wait */
  231. ret = -EBUSY;
  232. for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
  233. tmp = readl(&regs->gisr2);
  234. /* DMA complete */
  235. if (tmp & GISR2_DMAFIN) {
  236. ret = 0;
  237. break;
  238. }
  239. /* DMA error */
  240. if (tmp & GISR2_DMAERR) {
  241. printf("fotg210: dma error\n");
  242. break;
  243. }
  244. /* resume, suspend, reset */
  245. if (tmp & (GISR2_RESUME | GISR2_SUSPEND | GISR2_RESET)) {
  246. printf("fotg210: dma reset by host\n");
  247. break;
  248. }
  249. }
  250. /* 7. DMA target reset */
  251. if (ret)
  252. writel(DMACTRL_ABORT | DMACTRL_CLRFF, &regs->dma_ctrl);
  253. writel(0, &regs->gisr2);
  254. writel(0, &regs->dma_fifo);
  255. req->req.status = ret;
  256. if (!ret)
  257. req->req.actual += len;
  258. else
  259. printf("fotg210: ep%d dma error(code=%d)\n", ep->id, ret);
  260. return len;
  261. }
  262. /*
  263. * result of setup packet
  264. */
  265. #define CX_IDLE 0
  266. #define CX_FINISH 1
  267. #define CX_STALL 2
  268. static void fotg210_setup(struct fotg210_chip *chip)
  269. {
  270. int id, ret = CX_IDLE;
  271. uint32_t tmp[2];
  272. struct usb_ctrlrequest *req = (struct usb_ctrlrequest *)tmp;
  273. struct fotg210_regs *regs = chip->regs;
  274. /*
  275. * If this is the first Cx 8 byte command,
  276. * we can now query USB mode (high/full speed; USB 2.0/USB 1.0)
  277. */
  278. if (chip->state == USB_STATE_POWERED) {
  279. chip->state = USB_STATE_DEFAULT;
  280. if (readl(&regs->otgcsr) & OTGCSR_DEV_B) {
  281. /* Mini-B */
  282. if (readl(&regs->dev_ctrl) & DEVCTRL_HS) {
  283. puts("fotg210: HS\n");
  284. chip->gadget.speed = USB_SPEED_HIGH;
  285. /* SOF mask timer = 1100 ticks */
  286. writel(SOFMTR_TMR(1100), &regs->sof_mtr);
  287. } else {
  288. puts("fotg210: FS\n");
  289. chip->gadget.speed = USB_SPEED_FULL;
  290. /* SOF mask timer = 10000 ticks */
  291. writel(SOFMTR_TMR(10000), &regs->sof_mtr);
  292. }
  293. } else {
  294. printf("fotg210: mini-A?\n");
  295. }
  296. }
  297. /* switch data port to ep0 */
  298. writel(DMAFIFO_CX, &regs->dma_fifo);
  299. /* fetch 8 bytes setup packet */
  300. tmp[0] = readl(&regs->ep0_data);
  301. tmp[1] = readl(&regs->ep0_data);
  302. /* release data port */
  303. writel(0, &regs->dma_fifo);
  304. if (req->bRequestType & USB_DIR_IN)
  305. ep0_desc.bEndpointAddress = USB_DIR_IN;
  306. else
  307. ep0_desc.bEndpointAddress = USB_DIR_OUT;
  308. ret = CX_IDLE;
  309. if ((req->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
  310. switch (req->bRequest) {
  311. case USB_REQ_SET_CONFIGURATION:
  312. debug("fotg210: set_cfg(%d)\n", req->wValue & 0x00FF);
  313. if (!(req->wValue & 0x00FF)) {
  314. chip->state = USB_STATE_ADDRESS;
  315. writel(chip->addr, &regs->dev_addr);
  316. } else {
  317. chip->state = USB_STATE_CONFIGURED;
  318. writel(chip->addr | DEVADDR_CONF,
  319. &regs->dev_addr);
  320. }
  321. ret = CX_IDLE;
  322. break;
  323. case USB_REQ_SET_ADDRESS:
  324. debug("fotg210: set_addr(0x%04X)\n", req->wValue);
  325. chip->state = USB_STATE_ADDRESS;
  326. chip->addr = req->wValue & DEVADDR_ADDR_MASK;
  327. ret = CX_FINISH;
  328. writel(chip->addr, &regs->dev_addr);
  329. break;
  330. case USB_REQ_CLEAR_FEATURE:
  331. debug("fotg210: clr_feature(%d, %d)\n",
  332. req->bRequestType & 0x03, req->wValue);
  333. switch (req->wValue) {
  334. case 0: /* [Endpoint] halt */
  335. ep_reset(chip, req->wIndex);
  336. ret = CX_FINISH;
  337. break;
  338. case 1: /* [Device] remote wake-up */
  339. case 2: /* [Device] test mode */
  340. default:
  341. ret = CX_STALL;
  342. break;
  343. }
  344. break;
  345. case USB_REQ_SET_FEATURE:
  346. debug("fotg210: set_feature(%d, %d)\n",
  347. req->wValue, req->wIndex & 0xf);
  348. switch (req->wValue) {
  349. case 0: /* Endpoint Halt */
  350. id = req->wIndex & 0xf;
  351. setbits_le32(&regs->iep[id - 1], IEP_STALL);
  352. setbits_le32(&regs->oep[id - 1], OEP_STALL);
  353. ret = CX_FINISH;
  354. break;
  355. case 1: /* Remote Wakeup */
  356. case 2: /* Test Mode */
  357. default:
  358. ret = CX_STALL;
  359. break;
  360. }
  361. break;
  362. case USB_REQ_GET_STATUS:
  363. debug("fotg210: get_status\n");
  364. ret = CX_STALL;
  365. break;
  366. case USB_REQ_SET_DESCRIPTOR:
  367. debug("fotg210: set_descriptor\n");
  368. ret = CX_STALL;
  369. break;
  370. case USB_REQ_SYNCH_FRAME:
  371. debug("fotg210: sync frame\n");
  372. ret = CX_STALL;
  373. break;
  374. }
  375. } /* if ((req->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) */
  376. if (ret == CX_IDLE && chip->driver->setup) {
  377. if (chip->driver->setup(&chip->gadget, req) < 0)
  378. ret = CX_STALL;
  379. else
  380. ret = CX_FINISH;
  381. }
  382. switch (ret) {
  383. case CX_FINISH:
  384. setbits_le32(&regs->cxfifo, CXFIFO_CXFIN);
  385. break;
  386. case CX_STALL:
  387. setbits_le32(&regs->cxfifo, CXFIFO_CXSTALL | CXFIFO_CXFIN);
  388. printf("fotg210: cx_stall!\n");
  389. break;
  390. case CX_IDLE:
  391. debug("fotg210: cx_idle?\n");
  392. default:
  393. break;
  394. }
  395. }
  396. /*
  397. * fifo - FIFO id
  398. * zlp - zero length packet
  399. */
  400. static void fotg210_recv(struct fotg210_chip *chip, int ep_id)
  401. {
  402. struct fotg210_regs *regs = chip->regs;
  403. struct fotg210_ep *ep = chip->ep + ep_id;
  404. struct fotg210_request *req;
  405. int len;
  406. if (ep->stopped || (ep->desc->bEndpointAddress & USB_DIR_IN)) {
  407. printf("fotg210: ep%d recv, invalid!\n", ep->id);
  408. return;
  409. }
  410. if (list_empty(&ep->queue)) {
  411. printf("fotg210: ep%d recv, drop!\n", ep->id);
  412. return;
  413. }
  414. req = list_first_entry(&ep->queue, struct fotg210_request, queue);
  415. len = fotg210_dma(ep, req);
  416. if (len < ep->ep.maxpacket || req->req.length <= req->req.actual) {
  417. list_del_init(&req->queue);
  418. if (req->req.complete)
  419. req->req.complete(&ep->ep, &req->req);
  420. }
  421. if (ep->id > 0 && list_empty(&ep->queue)) {
  422. setbits_le32(&regs->gimr1,
  423. GIMR1_FIFO_RX(ep_to_fifo(chip, ep->id)));
  424. }
  425. }
  426. /*
  427. * USB Gadget Layer
  428. */
  429. static int fotg210_ep_enable(
  430. struct usb_ep *_ep, const struct usb_endpoint_descriptor *desc)
  431. {
  432. struct fotg210_ep *ep = container_of(_ep, struct fotg210_ep, ep);
  433. struct fotg210_chip *chip = ep->chip;
  434. struct fotg210_regs *regs = chip->regs;
  435. int id = ep_to_fifo(chip, ep->id);
  436. int in = (desc->bEndpointAddress & USB_DIR_IN) ? 1 : 0;
  437. if (!_ep || !desc
  438. || desc->bDescriptorType != USB_DT_ENDPOINT
  439. || le16_to_cpu(desc->wMaxPacketSize) == 0) {
  440. printf("fotg210: bad ep or descriptor\n");
  441. return -EINVAL;
  442. }
  443. ep->desc = desc;
  444. ep->stopped = 0;
  445. if (in)
  446. setbits_le32(&regs->fifomap, FIFOMAP(id, FIFOMAP_IN));
  447. switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
  448. case USB_ENDPOINT_XFER_CONTROL:
  449. return -EINVAL;
  450. case USB_ENDPOINT_XFER_ISOC:
  451. setbits_le32(&regs->fifocfg,
  452. FIFOCFG(id, FIFOCFG_EN | FIFOCFG_ISOC));
  453. break;
  454. case USB_ENDPOINT_XFER_BULK:
  455. setbits_le32(&regs->fifocfg,
  456. FIFOCFG(id, FIFOCFG_EN | FIFOCFG_BULK));
  457. break;
  458. case USB_ENDPOINT_XFER_INT:
  459. setbits_le32(&regs->fifocfg,
  460. FIFOCFG(id, FIFOCFG_EN | FIFOCFG_INTR));
  461. break;
  462. }
  463. return 0;
  464. }
  465. static int fotg210_ep_disable(struct usb_ep *_ep)
  466. {
  467. struct fotg210_ep *ep = container_of(_ep, struct fotg210_ep, ep);
  468. struct fotg210_chip *chip = ep->chip;
  469. struct fotg210_regs *regs = chip->regs;
  470. int id = ep_to_fifo(chip, ep->id);
  471. ep->desc = NULL;
  472. ep->stopped = 1;
  473. clrbits_le32(&regs->fifocfg, FIFOCFG(id, FIFOCFG_CFG_MASK));
  474. clrbits_le32(&regs->fifomap, FIFOMAP(id, FIFOMAP_DIR_MASK));
  475. return 0;
  476. }
  477. static struct usb_request *fotg210_ep_alloc_request(
  478. struct usb_ep *_ep, gfp_t gfp_flags)
  479. {
  480. struct fotg210_request *req = malloc(sizeof(*req));
  481. if (req) {
  482. memset(req, 0, sizeof(*req));
  483. INIT_LIST_HEAD(&req->queue);
  484. }
  485. return &req->req;
  486. }
  487. static void fotg210_ep_free_request(
  488. struct usb_ep *_ep, struct usb_request *_req)
  489. {
  490. struct fotg210_request *req;
  491. req = container_of(_req, struct fotg210_request, req);
  492. free(req);
  493. }
  494. static int fotg210_ep_queue(
  495. struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
  496. {
  497. struct fotg210_ep *ep = container_of(_ep, struct fotg210_ep, ep);
  498. struct fotg210_chip *chip = ep->chip;
  499. struct fotg210_regs *regs = chip->regs;
  500. struct fotg210_request *req;
  501. req = container_of(_req, struct fotg210_request, req);
  502. if (!_req || !_req->complete || !_req->buf
  503. || !list_empty(&req->queue)) {
  504. printf("fotg210: invalid request to ep%d\n", ep->id);
  505. return -EINVAL;
  506. }
  507. if (!chip || chip->state == USB_STATE_SUSPENDED) {
  508. printf("fotg210: request while chip suspended\n");
  509. return -EINVAL;
  510. }
  511. req->req.actual = 0;
  512. req->req.status = -EINPROGRESS;
  513. if (req->req.length == 0) {
  514. req->req.status = 0;
  515. if (req->req.complete)
  516. req->req.complete(&ep->ep, &req->req);
  517. return 0;
  518. }
  519. if (ep->id == 0) {
  520. do {
  521. int len = fotg210_dma(ep, req);
  522. if (len < ep->ep.maxpacket)
  523. break;
  524. if (ep->desc->bEndpointAddress & USB_DIR_IN)
  525. udelay(100);
  526. } while (req->req.length > req->req.actual);
  527. } else {
  528. if (ep->desc->bEndpointAddress & USB_DIR_IN) {
  529. do {
  530. int len = fotg210_dma(ep, req);
  531. if (len < ep->ep.maxpacket)
  532. break;
  533. } while (req->req.length > req->req.actual);
  534. } else {
  535. list_add_tail(&req->queue, &ep->queue);
  536. clrbits_le32(&regs->gimr1,
  537. GIMR1_FIFO_RX(ep_to_fifo(chip, ep->id)));
  538. }
  539. }
  540. if (ep->id == 0 || (ep->desc->bEndpointAddress & USB_DIR_IN)) {
  541. if (req->req.complete)
  542. req->req.complete(&ep->ep, &req->req);
  543. }
  544. return 0;
  545. }
  546. static int fotg210_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  547. {
  548. struct fotg210_ep *ep = container_of(_ep, struct fotg210_ep, ep);
  549. struct fotg210_request *req;
  550. /* make sure it's actually queued on this endpoint */
  551. list_for_each_entry(req, &ep->queue, queue) {
  552. if (&req->req == _req)
  553. break;
  554. }
  555. if (&req->req != _req)
  556. return -EINVAL;
  557. /* remove the request */
  558. list_del_init(&req->queue);
  559. /* update status & invoke complete callback */
  560. if (req->req.status == -EINPROGRESS) {
  561. req->req.status = -ECONNRESET;
  562. if (req->req.complete)
  563. req->req.complete(_ep, &req->req);
  564. }
  565. return 0;
  566. }
  567. static int fotg210_ep_halt(struct usb_ep *_ep, int halt)
  568. {
  569. struct fotg210_ep *ep = container_of(_ep, struct fotg210_ep, ep);
  570. struct fotg210_chip *chip = ep->chip;
  571. struct fotg210_regs *regs = chip->regs;
  572. int ret = -1;
  573. debug("fotg210: ep%d halt=%d\n", ep->id, halt);
  574. /* Endpoint STALL */
  575. if (ep->id > 0 && ep->id <= CFG_NUM_ENDPOINTS) {
  576. if (halt) {
  577. /* wait until all ep fifo empty */
  578. fotg210_cxwait(chip, 0xf00);
  579. /* stall */
  580. if (ep->desc->bEndpointAddress & USB_DIR_IN) {
  581. setbits_le32(&regs->iep[ep->id - 1],
  582. IEP_STALL);
  583. } else {
  584. setbits_le32(&regs->oep[ep->id - 1],
  585. OEP_STALL);
  586. }
  587. } else {
  588. if (ep->desc->bEndpointAddress & USB_DIR_IN) {
  589. clrbits_le32(&regs->iep[ep->id - 1],
  590. IEP_STALL);
  591. } else {
  592. clrbits_le32(&regs->oep[ep->id - 1],
  593. OEP_STALL);
  594. }
  595. }
  596. ret = 0;
  597. }
  598. return ret;
  599. }
  600. /*
  601. * activate/deactivate link with host.
  602. */
  603. static void pullup(struct fotg210_chip *chip, int is_on)
  604. {
  605. struct fotg210_regs *regs = chip->regs;
  606. if (is_on) {
  607. if (!chip->pullup) {
  608. chip->state = USB_STATE_POWERED;
  609. chip->pullup = 1;
  610. /* enable the chip */
  611. setbits_le32(&regs->dev_ctrl, DEVCTRL_EN);
  612. /* clear unplug bit (BIT0) */
  613. clrbits_le32(&regs->phy_tmsr, PHYTMSR_UNPLUG);
  614. }
  615. } else {
  616. chip->state = USB_STATE_NOTATTACHED;
  617. chip->pullup = 0;
  618. chip->addr = 0;
  619. writel(chip->addr, &regs->dev_addr);
  620. /* set unplug bit (BIT0) */
  621. setbits_le32(&regs->phy_tmsr, PHYTMSR_UNPLUG);
  622. /* disable the chip */
  623. clrbits_le32(&regs->dev_ctrl, DEVCTRL_EN);
  624. }
  625. }
  626. static int fotg210_pullup(struct usb_gadget *_gadget, int is_on)
  627. {
  628. struct fotg210_chip *chip;
  629. chip = container_of(_gadget, struct fotg210_chip, gadget);
  630. debug("fotg210: pullup=%d\n", is_on);
  631. pullup(chip, is_on);
  632. return 0;
  633. }
  634. static int fotg210_get_frame(struct usb_gadget *_gadget)
  635. {
  636. struct fotg210_chip *chip;
  637. struct fotg210_regs *regs;
  638. chip = container_of(_gadget, struct fotg210_chip, gadget);
  639. regs = chip->regs;
  640. return SOFFNR_FNR(readl(&regs->sof_fnr));
  641. }
  642. static struct usb_gadget_ops fotg210_gadget_ops = {
  643. .get_frame = fotg210_get_frame,
  644. .pullup = fotg210_pullup,
  645. };
  646. static struct usb_ep_ops fotg210_ep_ops = {
  647. .enable = fotg210_ep_enable,
  648. .disable = fotg210_ep_disable,
  649. .queue = fotg210_ep_queue,
  650. .dequeue = fotg210_ep_dequeue,
  651. .set_halt = fotg210_ep_halt,
  652. .alloc_request = fotg210_ep_alloc_request,
  653. .free_request = fotg210_ep_free_request,
  654. };
  655. static struct fotg210_chip controller = {
  656. .regs = (void __iomem *)CONFIG_FOTG210_BASE,
  657. .gadget = {
  658. .name = "fotg210_udc",
  659. .ops = &fotg210_gadget_ops,
  660. .ep0 = &controller.ep[0].ep,
  661. .speed = USB_SPEED_UNKNOWN,
  662. .is_dualspeed = 1,
  663. .is_otg = 0,
  664. .is_a_peripheral = 0,
  665. .b_hnp_enable = 0,
  666. .a_hnp_support = 0,
  667. .a_alt_hnp_support = 0,
  668. },
  669. .ep[0] = {
  670. .id = 0,
  671. .ep = {
  672. .name = "ep0",
  673. .ops = &fotg210_ep_ops,
  674. },
  675. .desc = &ep0_desc,
  676. .chip = &controller,
  677. .maxpacket = CFG_EP0_MAX_PACKET_SIZE,
  678. },
  679. .ep[1] = {
  680. .id = 1,
  681. .ep = {
  682. .name = "ep1",
  683. .ops = &fotg210_ep_ops,
  684. },
  685. .chip = &controller,
  686. .maxpacket = CFG_EPX_MAX_PACKET_SIZE,
  687. },
  688. .ep[2] = {
  689. .id = 2,
  690. .ep = {
  691. .name = "ep2",
  692. .ops = &fotg210_ep_ops,
  693. },
  694. .chip = &controller,
  695. .maxpacket = CFG_EPX_MAX_PACKET_SIZE,
  696. },
  697. .ep[3] = {
  698. .id = 3,
  699. .ep = {
  700. .name = "ep3",
  701. .ops = &fotg210_ep_ops,
  702. },
  703. .chip = &controller,
  704. .maxpacket = CFG_EPX_MAX_PACKET_SIZE,
  705. },
  706. .ep[4] = {
  707. .id = 4,
  708. .ep = {
  709. .name = "ep4",
  710. .ops = &fotg210_ep_ops,
  711. },
  712. .chip = &controller,
  713. .maxpacket = CFG_EPX_MAX_PACKET_SIZE,
  714. },
  715. };
  716. int usb_gadget_handle_interrupts(int index)
  717. {
  718. struct fotg210_chip *chip = &controller;
  719. struct fotg210_regs *regs = chip->regs;
  720. uint32_t id, st, isr, gisr;
  721. isr = readl(&regs->isr) & (~readl(&regs->imr));
  722. gisr = readl(&regs->gisr) & (~readl(&regs->gimr));
  723. if (!(isr & ISR_DEV) || !gisr)
  724. return 0;
  725. writel(ISR_DEV, &regs->isr);
  726. /* CX interrupts */
  727. if (gisr & GISR_GRP0) {
  728. st = readl(&regs->gisr0);
  729. /*
  730. * Write 1 and then 0 works for both W1C & RW.
  731. *
  732. * HW v1.11.0+: It's a W1C register (write 1 clear)
  733. * HW v1.10.0-: It's a R/W register (write 0 clear)
  734. */
  735. writel(st & GISR0_CXABORT, &regs->gisr0);
  736. writel(0, &regs->gisr0);
  737. if (st & GISR0_CXERR)
  738. printf("fotg210: cmd error\n");
  739. if (st & GISR0_CXABORT)
  740. printf("fotg210: cmd abort\n");
  741. if (st & GISR0_CXSETUP) /* setup */
  742. fotg210_setup(chip);
  743. else if (st & GISR0_CXEND) /* command finish */
  744. setbits_le32(&regs->cxfifo, CXFIFO_CXFIN);
  745. }
  746. /* FIFO interrupts */
  747. if (gisr & GISR_GRP1) {
  748. st = readl(&regs->gisr1);
  749. for (id = 0; id < 4; ++id) {
  750. if (st & GISR1_RX_FIFO(id))
  751. fotg210_recv(chip, fifo_to_ep(chip, id, 0));
  752. }
  753. }
  754. /* Device Status Interrupts */
  755. if (gisr & GISR_GRP2) {
  756. st = readl(&regs->gisr2);
  757. /*
  758. * Write 1 and then 0 works for both W1C & RW.
  759. *
  760. * HW v1.11.0+: It's a W1C register (write 1 clear)
  761. * HW v1.10.0-: It's a R/W register (write 0 clear)
  762. */
  763. writel(st, &regs->gisr2);
  764. writel(0, &regs->gisr2);
  765. if (st & GISR2_RESET)
  766. printf("fotg210: reset by host\n");
  767. else if (st & GISR2_SUSPEND)
  768. printf("fotg210: suspend/removed\n");
  769. else if (st & GISR2_RESUME)
  770. printf("fotg210: resume\n");
  771. /* Errors */
  772. if (st & GISR2_ISOCERR)
  773. printf("fotg210: iso error\n");
  774. if (st & GISR2_ISOCABT)
  775. printf("fotg210: iso abort\n");
  776. if (st & GISR2_DMAERR)
  777. printf("fotg210: dma error\n");
  778. }
  779. return 0;
  780. }
  781. int usb_gadget_register_driver(struct usb_gadget_driver *driver)
  782. {
  783. int i, ret = 0;
  784. struct fotg210_chip *chip = &controller;
  785. if (!driver || !driver->bind || !driver->setup) {
  786. puts("fotg210: bad parameter.\n");
  787. return -EINVAL;
  788. }
  789. INIT_LIST_HEAD(&chip->gadget.ep_list);
  790. for (i = 0; i < CFG_NUM_ENDPOINTS + 1; ++i) {
  791. struct fotg210_ep *ep = chip->ep + i;
  792. ep->ep.maxpacket = ep->maxpacket;
  793. INIT_LIST_HEAD(&ep->queue);
  794. if (ep->id == 0) {
  795. ep->stopped = 0;
  796. } else {
  797. ep->stopped = 1;
  798. list_add_tail(&ep->ep.ep_list, &chip->gadget.ep_list);
  799. }
  800. }
  801. if (fotg210_reset(chip)) {
  802. puts("fotg210: reset failed.\n");
  803. return -EINVAL;
  804. }
  805. ret = driver->bind(&chip->gadget);
  806. if (ret) {
  807. debug("fotg210: driver->bind() returned %d\n", ret);
  808. return ret;
  809. }
  810. chip->driver = driver;
  811. return ret;
  812. }
  813. int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
  814. {
  815. struct fotg210_chip *chip = &controller;
  816. driver->unbind(&chip->gadget);
  817. chip->driver = NULL;
  818. pullup(chip, 0);
  819. return 0;
  820. }