صفحهٔ اصلی گشت‌و‌گذار راهنما
ثبت نام ورود
RD_Software
/
linux-arkmicro
2
0
انشعاب 1
پرونده‌ها مشکلات 0 درخواست واکشی 0 ویکی
درخت: 54b20eeb90
شاخه‌ها تگ‌ها
linux-arkmicro
/
u-boot
/
arch
/
arm
/
include
/
asm
/
arch-am33xx
/
hardware_am33xx.h

hardware_am33xx.h 1.8 KB
تاريخچه خام

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576 
  1. /* SPDX-License-Identifier: GPL-2.0+ */
    2. 

  2. /*
    3. 

  3.  * hardware_am33xx.h
    4. 

  4.  *
    5. 

  5.  * AM33xx hardware specific header
    6. 

  6.  *
    7. 

  7.  * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
    8. 

  8.  */
    9. 

  9. 

  10. #ifndef __AM33XX_HARDWARE_AM33XX_H
    11. 

  11. #define __AM33XX_HARDWARE_AM33XX_H
    12. 

  12. 

  13. /* Module base addresses */
    14. 

  14. 

  15. /* UART Base Address */
    16. 

  16. #define UART0_BASE			0x44E09000
    17. 

  17. #define UART1_BASE			0x48022000
    18. 

  18. #define UART2_BASE			0x48024000
    19. 

  19. #define UART3_BASE			0x481A6000
    20. 

  20. #define UART4_BASE			0x481A8000
    21. 

  21. #define UART5_BASE			0x481AA000
    22. 

  22. 

  23. /* GPIO Base address */
    24. 

  24. #define GPIO2_BASE			0x481AC000
    25. 

  25. 

  26. /* Watchdog Timer */
    27. 

  27. #define WDT_BASE			0x44E35000
    28. 

  28. 

  29. /* Control Module Base Address */
    30. 

  30. #define CTRL_BASE			0x44E10000
    31. 

  31. #define CTRL_DEVICE_BASE		0x44E10600
    32. 

  32. 

  33. /* PRCM Base Address */
    34. 

  34. #define PRCM_BASE			0x44E00000
    35. 

  35. #define CM_PER				0x44E00000
    36. 

  36. #define CM_WKUP				0x44E00400
    37. 

  37. #define CM_DPLL				0x44E00500
    38. 

  38. #define CM_RTC				0x44E00800
    39. 

  39. 

  40. #define PRM_RSTCTRL			(PRCM_BASE + 0x0F00)
    41. 

  41. #define PRM_RSTST			(PRM_RSTCTRL + 8)
    42. 

  42. 

  43. /* VTP Base address */
    44. 

  44. #define VTP0_CTRL_ADDR			0x44E10E0C
    45. 

  45. #define VTP1_CTRL_ADDR			0x48140E10
    46. 

  46. #define PRM_DEVICE_INST			0x44E00F00
    47. 

  47. 

  48. /* DDR Base address */
    49. 

  49. #define DDR_PHY_CMD_ADDR		0x44E12000
    50. 

  50. #define DDR_PHY_DATA_ADDR		0x44E120C8
    51. 

  51. #define DDR_PHY_CMD_ADDR2		0x47C0C800
    52. 

  52. #define DDR_PHY_DATA_ADDR2		0x47C0C8C8
    53. 

  53. #define DDR_DATA_REGS_NR		2
    54. 

  54. 

  55. #define DDRPHY_0_CONFIG_BASE		(CTRL_BASE + 0x1400)
    56. 

  56. #define DDRPHY_CONFIG_BASE		DDRPHY_0_CONFIG_BASE
    57. 

  57. 

  58. /* CPSW Config space */
    59. 

  59. #define CPSW_MDIO_BASE			0x4A101000
    60. 

  60. 

  61. /* RTC base address */
    62. 

  62. #define RTC_BASE			0x44E3E000
    63. 

  63. 

  64. /* OTG */
    65. 

  65. #define USB0_OTG_BASE			0x47401000
    66. 

  66. #define USB1_OTG_BASE			0x47401800
    67. 

  67. 

  68. /* LCD Controller */
    69. 

  69. #define LCD_CNTL_BASE			0x4830E000
    70. 

  70. 

  71. /* PWMSS */
    72. 

  72. #define PWMSS0_BASE			0x48300000
    73. 

  73. #define AM33XX_ECAP0_BASE		0x48300100
    74. 

  74. #define AM33XX_EPWM_BASE		0x48300200
    75. 

  75. 

  76. #endif /* __AM33XX_HARDWARE_AM33XX_H */
    77.