mux_omap5.h 8.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2004-2009
  4. * Texas Instruments Incorporated
  5. * Richard Woodruff <r-woodruff2@ti.com>
  6. * Aneesh V <aneesh@ti.com>
  7. * Balaji Krishnamoorthy <balajitk@ti.com>
  8. */
  9. #ifndef _MUX_OMAP5_H_
  10. #define _MUX_OMAP5_H_
  11. #include <asm/types.h>
  12. #ifdef CONFIG_OFF_PADCONF
  13. #define OFF_PD (1 << 12)
  14. #define OFF_PU (3 << 12)
  15. #define OFF_OUT_PTD (0 << 10)
  16. #define OFF_OUT_PTU (2 << 10)
  17. #define OFF_IN (1 << 10)
  18. #define OFF_OUT (0 << 10)
  19. #define OFF_EN (1 << 9)
  20. #else
  21. #define OFF_PD (0 << 12)
  22. #define OFF_PU (0 << 12)
  23. #define OFF_OUT_PTD (0 << 10)
  24. #define OFF_OUT_PTU (0 << 10)
  25. #define OFF_IN (0 << 10)
  26. #define OFF_OUT (0 << 10)
  27. #define OFF_EN (0 << 9)
  28. #endif
  29. #define IEN (1 << 8)
  30. #define IDIS (0 << 8)
  31. #define PTU (3 << 3)
  32. #define PTD (1 << 3)
  33. #define EN (1 << 3)
  34. #define DIS (0 << 3)
  35. #define M0 0
  36. #define M1 1
  37. #define M2 2
  38. #define M3 3
  39. #define M4 4
  40. #define M5 5
  41. #define M6 6
  42. #define M7 7
  43. #define SAFE_MODE M7
  44. #ifdef CONFIG_OFF_PADCONF
  45. #define OFF_IN_PD (OFF_PD | OFF_IN | OFF_EN)
  46. #define OFF_IN_PU (OFF_PU | OFF_IN | OFF_EN)
  47. #define OFF_OUT_PD (OFF_OUT_PTD | OFF_OUT | OFF_EN)
  48. #define OFF_OUT_PU (OFF_OUT_PTU | OFF_OUT | OFF_EN)
  49. #else
  50. #define OFF_IN_PD 0
  51. #define OFF_IN_PU 0
  52. #define OFF_OUT_PD 0
  53. #define OFF_OUT_PU 0
  54. #endif
  55. #define CORE_REVISION 0x0000
  56. #define CORE_HWINFO 0x0004
  57. #define CORE_SYSCONFIG 0x0010
  58. #define EMMC_CLK 0x0040
  59. #define EMMC_CMD 0x0042
  60. #define EMMC_DATA0 0x0044
  61. #define EMMC_DATA1 0x0046
  62. #define EMMC_DATA2 0x0048
  63. #define EMMC_DATA3 0x004a
  64. #define EMMC_DATA4 0x004c
  65. #define EMMC_DATA5 0x004e
  66. #define EMMC_DATA6 0x0050
  67. #define EMMC_DATA7 0x0052
  68. #define C2C_CLKOUT0 0x0054
  69. #define C2C_CLKOUT1 0x0056
  70. #define C2C_CLKIN0 0x0058
  71. #define C2C_CLKIN1 0x005a
  72. #define C2C_DATAIN0 0x005c
  73. #define C2C_DATAIN1 0x005e
  74. #define C2C_DATAIN2 0x0060
  75. #define C2C_DATAIN3 0x0062
  76. #define C2C_DATAIN4 0x0064
  77. #define C2C_DATAIN5 0x0066
  78. #define C2C_DATAIN6 0x0068
  79. #define C2C_DATAIN7 0x006a
  80. #define C2C_DATAOUT0 0x006c
  81. #define C2C_DATAOUT1 0x006e
  82. #define C2C_DATAOUT2 0x0070
  83. #define C2C_DATAOUT3 0x0072
  84. #define C2C_DATAOUT4 0x0074
  85. #define C2C_DATAOUT5 0x0076
  86. #define C2C_DATAOUT6 0x0078
  87. #define C2C_DATAOUT7 0x007a
  88. #define C2C_DATA8 0x007c
  89. #define C2C_DATA9 0x007e
  90. #define C2C_DATA10 0x0080
  91. #define C2C_DATA11 0x0082
  92. #define C2C_DATA12 0x0084
  93. #define C2C_DATA13 0x0086
  94. #define C2C_DATA14 0x0088
  95. #define C2C_DATA15 0x008a
  96. #define LLIA_WAKEREQOUT 0x008c
  97. #define LLIB_WAKEREQOUT 0x008e
  98. #define HSI1_ACREADY 0x0090
  99. #define HSI1_CAREADY 0x0092
  100. #define HSI1_ACWAKE 0x0094
  101. #define HSI1_CAWAKE 0x0096
  102. #define HSI1_ACFLAG 0x0098
  103. #define HSI1_ACDATA 0x009a
  104. #define HSI1_CAFLAG 0x009c
  105. #define HSI1_CADATA 0x009e
  106. #define UART1_TX 0x00a0
  107. #define UART1_CTS 0x00a2
  108. #define UART1_RX 0x00a4
  109. #define UART1_RTS 0x00a6
  110. #define HSI2_CAREADY 0x00a8
  111. #define HSI2_ACREADY 0x00aa
  112. #define HSI2_CAWAKE 0x00ac
  113. #define HSI2_ACWAKE 0x00ae
  114. #define HSI2_CAFLAG 0x00b0
  115. #define HSI2_CADATA 0x00b2
  116. #define HSI2_ACFLAG 0x00b4
  117. #define HSI2_ACDATA 0x00b6
  118. #define UART2_RTS 0x00b8
  119. #define UART2_CTS 0x00ba
  120. #define UART2_RX 0x00bc
  121. #define UART2_TX 0x00be
  122. #define USBB1_HSIC_STROBE 0x00c0
  123. #define USBB1_HSIC_DATA 0x00c2
  124. #define USBB2_HSIC_STROBE 0x00c4
  125. #define USBB2_HSIC_DATA 0x00c6
  126. #define TIMER10_PWM_EVT 0x00c8
  127. #define DSIPORTA_TE0 0x00ca
  128. #define DSIPORTA_LANE0X 0x00cc
  129. #define DSIPORTA_LANE0Y 0x00ce
  130. #define DSIPORTA_LANE1X 0x00d0
  131. #define DSIPORTA_LANE1Y 0x00d2
  132. #define DSIPORTA_LANE2X 0x00d4
  133. #define DSIPORTA_LANE2Y 0x00d6
  134. #define DSIPORTA_LANE3X 0x00d8
  135. #define DSIPORTA_LANE3Y 0x00da
  136. #define DSIPORTA_LANE4X 0x00dc
  137. #define DSIPORTA_LANE4Y 0x00de
  138. #define DSIPORTC_LANE0X 0x00e0
  139. #define DSIPORTC_LANE0Y 0x00e2
  140. #define DSIPORTC_LANE1X 0x00e4
  141. #define DSIPORTC_LANE1Y 0x00e6
  142. #define DSIPORTC_LANE2X 0x00e8
  143. #define DSIPORTC_LANE2Y 0x00ea
  144. #define DSIPORTC_LANE3X 0x00ec
  145. #define DSIPORTC_LANE3Y 0x00ee
  146. #define DSIPORTC_LANE4X 0x00f0
  147. #define DSIPORTC_LANE4Y 0x00f2
  148. #define DSIPORTC_TE0 0x00f4
  149. #define TIMER9_PWM_EVT 0x00f6
  150. #define I2C4_SCL 0x00f8
  151. #define I2C4_SDA 0x00fa
  152. #define MCSPI2_CLK 0x00fc
  153. #define MCSPI2_SIMO 0x00fe
  154. #define MCSPI2_SOMI 0x0100
  155. #define MCSPI2_CS0 0x0102
  156. #define RFBI_DATA15 0x0104
  157. #define RFBI_DATA14 0x0106
  158. #define RFBI_DATA13 0x0108
  159. #define RFBI_DATA12 0x010a
  160. #define RFBI_DATA11 0x010c
  161. #define RFBI_DATA10 0x010e
  162. #define RFBI_DATA9 0x0110
  163. #define RFBI_DATA8 0x0112
  164. #define RFBI_DATA7 0x0114
  165. #define RFBI_DATA6 0x0116
  166. #define RFBI_DATA5 0x0118
  167. #define RFBI_DATA4 0x011a
  168. #define RFBI_DATA3 0x011c
  169. #define RFBI_DATA2 0x011e
  170. #define RFBI_DATA1 0x0120
  171. #define RFBI_DATA0 0x0122
  172. #define RFBI_WE 0x0124
  173. #define RFBI_CS0 0x0126
  174. #define RFBI_A0 0x0128
  175. #define RFBI_RE 0x012a
  176. #define RFBI_HSYNC0 0x012c
  177. #define RFBI_TE_VSYNC0 0x012e
  178. #define GPIO6_182 0x0130
  179. #define GPIO6_183 0x0132
  180. #define GPIO6_184 0x0134
  181. #define GPIO6_185 0x0136
  182. #define GPIO6_186 0x0138
  183. #define GPIO6_187 0x013a
  184. #define HDMI_CEC 0x013c
  185. #define HDMI_HPD 0x013e
  186. #define HDMI_DDC_SCL 0x0140
  187. #define HDMI_DDC_SDA 0x0142
  188. #define CSIPORTC_LANE0X 0x0144
  189. #define CSIPORTC_LANE0Y 0x0146
  190. #define CSIPORTC_LANE1X 0x0148
  191. #define CSIPORTC_LANE1Y 0x014a
  192. #define CSIPORTB_LANE0X 0x014c
  193. #define CSIPORTB_LANE0Y 0x014e
  194. #define CSIPORTB_LANE1X 0x0150
  195. #define CSIPORTB_LANE1Y 0x0152
  196. #define CSIPORTB_LANE2X 0x0154
  197. #define CSIPORTB_LANE2Y 0x0156
  198. #define CSIPORTA_LANE0X 0x0158
  199. #define CSIPORTA_LANE0Y 0x015a
  200. #define CSIPORTA_LANE1X 0x015c
  201. #define CSIPORTA_LANE1Y 0x015e
  202. #define CSIPORTA_LANE2X 0x0160
  203. #define CSIPORTA_LANE2Y 0x0162
  204. #define CSIPORTA_LANE3X 0x0164
  205. #define CSIPORTA_LANE3Y 0x0166
  206. #define CSIPORTA_LANE4X 0x0168
  207. #define CSIPORTA_LANE4Y 0x016a
  208. #define CAM_SHUTTER 0x016c
  209. #define CAM_STROBE 0x016e
  210. #define CAM_GLOBALRESET 0x0170
  211. #define TIMER11_PWM_EVT 0x0172
  212. #define TIMER5_PWM_EVT 0x0174
  213. #define TIMER6_PWM_EVT 0x0176
  214. #define TIMER8_PWM_EVT 0x0178
  215. #define I2C3_SCL 0x017a
  216. #define I2C3_SDA 0x017c
  217. #define GPIO8_233 0x017e
  218. #define GPIO8_234 0x0180
  219. #define ABE_CLKS 0x0182
  220. #define ABEDMIC_DIN1 0x0184
  221. #define ABEDMIC_DIN2 0x0186
  222. #define ABEDMIC_DIN3 0x0188
  223. #define ABEDMIC_CLK1 0x018a
  224. #define ABEDMIC_CLK2 0x018c
  225. #define ABEDMIC_CLK3 0x018e
  226. #define ABESLIMBUS1_CLOCK 0x0190
  227. #define ABESLIMBUS1_DATA 0x0192
  228. #define ABEMCBSP2_DR 0x0194
  229. #define ABEMCBSP2_DX 0x0196
  230. #define ABEMCBSP2_FSX 0x0198
  231. #define ABEMCBSP2_CLKX 0x019a
  232. #define ABEMCPDM_UL_DATA 0x019c
  233. #define ABEMCPDM_DL_DATA 0x019e
  234. #define ABEMCPDM_FRAME 0x01a0
  235. #define ABEMCPDM_LB_CLK 0x01a2
  236. #define WLSDIO_CLK 0x01a4
  237. #define WLSDIO_CMD 0x01a6
  238. #define WLSDIO_DATA0 0x01a8
  239. #define WLSDIO_DATA1 0x01aa
  240. #define WLSDIO_DATA2 0x01ac
  241. #define WLSDIO_DATA3 0x01ae
  242. #define UART5_RX 0x01b0
  243. #define UART5_TX 0x01b2
  244. #define UART5_CTS 0x01b4
  245. #define UART5_RTS 0x01b6
  246. #define I2C2_SCL 0x01b8
  247. #define I2C2_SDA 0x01ba
  248. #define MCSPI1_CLK 0x01bc
  249. #define MCSPI1_SOMI 0x01be
  250. #define MCSPI1_SIMO 0x01c0
  251. #define MCSPI1_CS0 0x01c2
  252. #define MCSPI1_CS1 0x01c4
  253. #define I2C5_SCL 0x01c6
  254. #define I2C5_SDA 0x01c8
  255. #define PERSLIMBUS2_CLOCK 0x01ca
  256. #define PERSLIMBUS2_DATA 0x01cc
  257. #define UART6_TX 0x01ce
  258. #define UART6_RX 0x01d0
  259. #define UART6_CTS 0x01d2
  260. #define UART6_RTS 0x01d4
  261. #define UART3_CTS_RCTX 0x01d6
  262. #define UART3_RTS_IRSD 0x01d8
  263. #define UART3_TX_IRTX 0x01da
  264. #define UART3_RX_IRRX 0x01dc
  265. #define USBB3_HSIC_STROBE 0x01de
  266. #define USBB3_HSIC_DATA 0x01e0
  267. #define SDCARD_CLK 0x01e2
  268. #define SDCARD_CMD 0x01e4
  269. #define SDCARD_DATA2 0x01e6
  270. #define SDCARD_DATA3 0x01e8
  271. #define SDCARD_DATA0 0x01ea
  272. #define SDCARD_DATA1 0x01ec
  273. #define USBD0_HS_DP 0x01ee
  274. #define USBD0_HS_DM 0x01f0
  275. #define I2C1_PMIC_SCL 0x01f2
  276. #define I2C1_PMIC_SDA 0x01f4
  277. #define USBD0_SS_RX 0x01f6
  278. #define LLIA_WAKEREQIN 0x0040
  279. #define LLIB_WAKEREQIN 0x0042
  280. #define DRM_EMU0 0x0044
  281. #define DRM_EMU1 0x0046
  282. #define JTAG_NTRST 0x0048
  283. #define JTAG_TCK 0x004a
  284. #define JTAG_RTCK 0x004c
  285. #define JTAG_TMSC 0x004e
  286. #define JTAG_TDI 0x0050
  287. #define JTAG_TDO 0x0052
  288. #define SYS_32K 0x0054
  289. #define FREF_CLK_IOREQ 0x0056
  290. #define FREF_CLK0_OUT 0x0058
  291. #define FREF_CLK1_OUT 0x005a
  292. #define FREF_CLK2_OUT 0x005c
  293. #define FREF_CLK2_REQ 0x005e
  294. #define FREF_CLK1_REQ 0x0060
  295. #define SYS_NRESPWRON 0x0062
  296. #define SYS_NRESWARM 0x0064
  297. #define SYS_PWR_REQ 0x0066
  298. #define SYS_NIRQ1 0x0068
  299. #define SYS_NIRQ2 0x006a
  300. #define SR_PMIC_SCL 0x006c
  301. #define SR_PMIC_SDA 0x006e
  302. #define SYS_BOOT0 0x0070
  303. #define SYS_BOOT1 0x0072
  304. #define SYS_BOOT2 0x0074
  305. #define SYS_BOOT3 0x0076
  306. #define SYS_BOOT4 0x0078
  307. #define SYS_BOOT5 0x007a
  308. #endif /* _MUX_OMAP5_H_ */