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ddr3.h

ddr3.h 1.9 KB
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  1. /* SPDX-License-Identifier: GPL-2.0+ */
    2. 

  2. /*
    3. 

  3.  * DDR3
    4. 

  4.  *
    5. 

  5.  * (C) Copyright 2014
    6. 

  6.  *     Texas Instruments Incorporated, <www.ti.com>
    7. 

  7.  */
    8. 

  8. 

  9. #ifndef _DDR3_H_
    10. 

  10. #define _DDR3_H_
    11. 

  11. 

  12. #include <asm/arch/hardware.h>
    13. 

  13. 

  14. struct ddr3_phy_config {
    15. 

  15. 	unsigned int pllcr;
    16. 

  16. 	unsigned int pgcr1_mask;
    17. 

  17. 	unsigned int pgcr1_val;
    18. 

  18. 	unsigned int ptr0;
    19. 

  19. 	unsigned int ptr1;
    20. 

  20. 	unsigned int ptr2;
    21. 

  21. 	unsigned int ptr3;
    22. 

  22. 	unsigned int ptr4;
    23. 

  23. 	unsigned int dcr_mask;
    24. 

  24. 	unsigned int dcr_val;
    25. 

  25. 	unsigned int dtpr0;
    26. 

  26. 	unsigned int dtpr1;
    27. 

  27. 	unsigned int dtpr2;
    28. 

  28. 	unsigned int mr0;
    29. 

  29. 	unsigned int mr1;
    30. 

  30. 	unsigned int mr2;
    31. 

  31. 	unsigned int dtcr;
    32. 

  32. 	unsigned int pgcr2;
    33. 

  33. 	unsigned int zq0cr1;
    34. 

  34. 	unsigned int zq1cr1;
    35. 

  35. 	unsigned int zq2cr1;
    36. 

  36. 	unsigned int pir_v1;
    37. 

  37. 	unsigned int datx8_2_mask;
    38. 

  38. 	unsigned int datx8_2_val;
    39. 

  39. 	unsigned int datx8_3_mask;
    40. 

  40. 	unsigned int datx8_3_val;
    41. 

  41. 	unsigned int datx8_4_mask;
    42. 

  42. 	unsigned int datx8_4_val;
    43. 

  43. 	unsigned int datx8_5_mask;
    44. 

  44. 	unsigned int datx8_5_val;
    45. 

  45. 	unsigned int datx8_6_mask;
    46. 

  46. 	unsigned int datx8_6_val;
    47. 

  47. 	unsigned int datx8_7_mask;
    48. 

  48. 	unsigned int datx8_7_val;
    49. 

  49. 	unsigned int datx8_8_mask;
    50. 

  50. 	unsigned int datx8_8_val;
    51. 

  51. 	unsigned int pir_v2;
    52. 

  52. };
    53. 

  53. 

  54. struct ddr3_emif_config {
    55. 

  55. 	unsigned int sdcfg;
    56. 

  56. 	unsigned int sdtim1;
    57. 

  57. 	unsigned int sdtim2;
    58. 

  58. 	unsigned int sdtim3;
    59. 

  59. 	unsigned int sdtim4;
    60. 

  60. 	unsigned int zqcfg;
    61. 

  61. 	unsigned int sdrfc;
    62. 

  62. };
    63. 

  63. 

  64. struct ddr3_spd_cb {
    65. 

  65. 	char   dimm_name[32];
    66. 

  66. 	struct ddr3_phy_config phy_cfg;
    67. 

  67. 	struct ddr3_emif_config emif_cfg;
    68. 

  68. 	unsigned int ddrspdclock;
    69. 

  69. 	int    ddr_size_gbyte;
    70. 

  70. };
    71. 

  71. 

  72. u32 ddr3_init(void);
    73. 

  73. void ddr3_reset_ddrphy(void);
    74. 

  74. void ddr3_init_ecc(u32 base, u32 ddr3_size);
    75. 

  75. void ddr3_disable_ecc(u32 base);
    76. 

  76. void ddr3_check_ecc_int(u32 base);
    77. 

  77. int ddr3_ecc_support_rmw(u32 base);
    78. 

  78. void ddr3_err_reset_workaround(void);
    79. 

  79. void ddr3_enable_ecc(u32 base, int test);
    80. 

  80. void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
    81. 

  81. void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
    82. 

  82. int ddr3_get_size(void);
    83. 

  83. 

  84. #endif
    85.