ark1668e_i2s.c 11 KB

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  1. /*
  2. * ark1668e_i2s.c -- ALSA SoC Audio Layer
  3. */
  4. #include <linux/init.h>
  5. #include <linux/module.h>
  6. #include <linux/io.h>
  7. #include <linux/slab.h>
  8. #include <linux/delay.h>
  9. #include <sound/core.h>
  10. #include <sound/pcm.h>
  11. #include <sound/pcm_params.h>
  12. #include <sound/soc.h>
  13. #include <sound/dmaengine_pcm.h>
  14. #include <linux/clk.h>
  15. #include "ark1668e_i2s.h"
  16. #define DRV_NAME "ark1668e-i2s"
  17. //struct ark1668e_i2s1_data_in i2s_data;
  18. int audio_codec_mode= SLAVE_MODE;////only for junjie
  19. struct ark1668e_i2s_dev {
  20. struct device *dev;
  21. void __iomem *base; //i2s_base
  22. struct clk *clk;
  23. int irq;
  24. u32 nco_reg;
  25. struct snd_dmaengine_dai_dma_data capture_dma_data;
  26. struct snd_dmaengine_dai_dma_data playback_dma_data;
  27. int master;
  28. u32 fmt;
  29. int full_duplex_en;
  30. };
  31. static void i2s_poweron(struct ark1668e_i2s_dev *i2s)
  32. {
  33. return;
  34. }
  35. static int ark1668e_i2s_startup(
  36. struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
  37. {
  38. struct ark1668e_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
  39. unsigned int sacr0 = 0;
  40. if(readl(i2s->base + I2S_SACR0) & SACR0_ENB)
  41. return 0;
  42. /* reset */
  43. writel(SACR0_RST, i2s->base + I2S_SACR0);
  44. udelay(1);
  45. writel(0, i2s->base + I2S_SACR0);
  46. if(i2s->full_duplex_en){
  47. sacr0 = SACR0_TLFIRST | SACR0_CH_LOCK | SACR0_TFTH(15) | SACR0_TDMAEN;
  48. sacr0 |= SACR0_RLFIRST | SACR0_CH_LOCK | SACR0_RFTH(16) | SACR0_RDMAEN;
  49. if (i2s->master)
  50. sacr0 |= SACR0_BCKD | SACR0_SYNCD;//ark1668e-i2s:Master mode
  51. else
  52. sacr0 &= ~(SACR0_BCKD | SACR0_SYNCD);//ark1668e-i2s:slave mode
  53. writel(sacr0, i2s->base + I2S_SACR0);
  54. writel(0x7f, i2s->base + I2S_SAICR);
  55. writel(0, i2s->base + I2S_SAICR);
  56. }else{
  57. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  58. /*i2s_regs_init*/
  59. sacr0 = SACR0_TLFIRST | SACR0_CH_LOCK | SACR0_TFTH(15) | SACR0_TDMAEN;
  60. if (i2s->master)
  61. sacr0 |= SACR0_BCKD | SACR0_SYNCD;//ark1668e-i2s:Master mode
  62. else
  63. sacr0 &= ~(SACR0_BCKD | SACR0_SYNCD);//ark1668e-i2s:slave mode
  64. writel(sacr0, i2s->base + I2S_SACR0);
  65. //writel(SAIMR_TUR, i2s->base + I2S_SAIMR);
  66. writel(0x7f, i2s->base + I2S_SAICR);
  67. writel(0, i2s->base + I2S_SAICR);
  68. } else if(substream->stream == SNDRV_PCM_STREAM_CAPTURE){
  69. /*i2s_regs_init*/
  70. sacr0 |= SACR0_RLFIRST | SACR0_CH_LOCK | SACR0_RFTH(16) | SACR0_RDMAEN;
  71. if (i2s->master)
  72. sacr0 |= SACR0_BCKD | SACR0_SYNCD;//ark1668e-i2s:Master mode
  73. else
  74. sacr0 &= ~(SACR0_BCKD | SACR0_SYNCD);//ark1668e-i2s:slave mode
  75. writel(sacr0, i2s->base + I2S_SACR0);
  76. //writel(SAIMR_ROR, i2s->base + I2S_SAIMR);
  77. writel(0x7f, i2s->base + I2S_SAICR);
  78. writel(0, i2s->base + I2S_SAICR);
  79. }
  80. }
  81. udelay(1);
  82. sacr0 &= ~SACR0_CH_LOCK;
  83. writel(sacr0, i2s->base + I2S_SACR0);
  84. return 0;
  85. }
  86. static int ark1668e_i2s_hw_params(
  87. struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params,
  88. struct snd_soc_dai *dai)
  89. {
  90. struct ark1668e_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
  91. u32 val;
  92. #ifndef BOARD_ARK1668E_FPGA
  93. u32 rate = params_rate(params);
  94. u32 step = 256 * 2, modulo;
  95. u32 freq;
  96. void *sysreg;
  97. if (!i2s->nco_reg)
  98. return 0;
  99. /* mclk = rate * 256, mclk = freq * step / (2 * modulo) */
  100. freq = clk_get_rate(i2s->clk);
  101. modulo = freq / rate;
  102. val = (step << 16) | modulo;
  103. sysreg = ioremap(i2s->nco_reg, 0x10);
  104. if (sysreg) {
  105. writel(val, sysreg);
  106. iounmap(sysreg);
  107. }
  108. #endif
  109. val = readl(i2s->base + I2S_SACR0);
  110. switch (params_format(params)) {
  111. case SNDRV_PCM_FORMAT_S16_LE:
  112. val &= ~SACR0_32BIT_MODE;
  113. break;
  114. case SNDRV_PCM_FORMAT_S24_LE:
  115. case SNDRV_PCM_FORMAT_S32_LE:
  116. val |= SACR0_32BIT_MODE;
  117. val &= ~(SACR0_RFTH_MASK | SACR0_TFTH_MASK);
  118. val |= SACR0_TFTH(7) | SACR0_RFTH(8);
  119. break;
  120. default:
  121. return -EINVAL;
  122. }
  123. if (params_channels(params) == 1)
  124. val |= SACR0_MOLO_MODE;
  125. writel(val, i2s->base + I2S_SACR0);
  126. return 0;
  127. }
  128. static int ark1668e_i2s_trigger(
  129. struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai)
  130. {
  131. struct ark1668e_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
  132. int ret = 0;
  133. switch (cmd) {
  134. case SNDRV_PCM_TRIGGER_START:
  135. if(!i2s->full_duplex_en){
  136. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  137. writel(readl(i2s->base + I2S_SACR1) & ~SACR1_DRPL, i2s->base + I2S_SACR1);
  138. else
  139. writel(readl(i2s->base + I2S_SACR1) & ~SACR1_DREC, i2s->base + I2S_SACR1);
  140. }else{
  141. writel(readl(i2s->base + I2S_SACR1) & ~SACR1_DRPL, i2s->base + I2S_SACR1);
  142. writel(readl(i2s->base + I2S_SACR1) & ~SACR1_DREC, i2s->base + I2S_SACR1);
  143. }
  144. writel(readl(i2s->base + I2S_SACR0) | SACR0_ENB, i2s->base + I2S_SACR0);
  145. break;
  146. case SNDRV_PCM_TRIGGER_STOP:
  147. /*if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  148. writel(readl(i2s->base + I2S_SACR1) | SACR1_DRPL, i2s->base + I2S_SACR1);
  149. else
  150. writel(readl(i2s->base + I2S_SACR1) | SACR1_DREC, i2s->base + I2S_SACR1);
  151. writel(readl(i2s->base + I2S_SACR0) & ~SACR0_ENB, i2s->base + I2S_SACR0); */
  152. break;
  153. case SNDRV_PCM_TRIGGER_RESUME:
  154. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  155. case SNDRV_PCM_TRIGGER_SUSPEND:
  156. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  157. break;
  158. default:
  159. ret = -EINVAL;
  160. }
  161. return ret;
  162. }
  163. static int ark1668e_i2s_set_fmt(
  164. struct snd_soc_dai *dai, unsigned int fmt)
  165. {
  166. struct ark1668e_i2s_dev *i2s =snd_soc_dai_get_drvdata(dai);
  167. /* interface format */
  168. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  169. case SND_SOC_DAIFMT_I2S:
  170. i2s->fmt = 0;
  171. break;
  172. }
  173. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  174. case SND_SOC_DAIFMT_CBS_CFS:
  175. dev_dbg(i2s->dev, "i2s master.\n");
  176. i2s->master = 1;
  177. break;
  178. case SND_SOC_DAIFMT_CBM_CFM:
  179. dev_dbg(i2s->dev, "i2s slave.\n");
  180. i2s->master = 0;
  181. break;
  182. default:
  183. break;
  184. }
  185. return 0;
  186. }
  187. static int ark1668e_i2s_probe(struct snd_soc_dai *dai)
  188. {
  189. struct ark1668e_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
  190. dai->capture_dma_data = &i2s->capture_dma_data;
  191. dai->playback_dma_data = &i2s->playback_dma_data;
  192. return 0;
  193. }
  194. /* I2S supported rate and format */
  195. #define ARK1668E_I2S_RATES \
  196. (SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
  197. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \
  198. SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | \
  199. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 | SNDRV_PCM_RATE_8000)
  200. static const struct snd_soc_dai_ops ark1668e_i2s_dai_ops = {
  201. .startup = ark1668e_i2s_startup,
  202. .trigger = ark1668e_i2s_trigger,
  203. .hw_params = ark1668e_i2s_hw_params,
  204. .set_fmt = ark1668e_i2s_set_fmt,
  205. };
  206. static struct snd_soc_dai_driver ark1668e_i2s_dai = {
  207. .probe = ark1668e_i2s_probe,
  208. .playback = {
  209. .channels_min = 1,
  210. .channels_max = 2,
  211. .rates = ARK1668E_I2S_RATES,
  212. .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
  213. SNDRV_PCM_FMTBIT_S32_LE,},
  214. .capture = {
  215. .channels_min = 2,
  216. .channels_max = 2,
  217. .rates = ARK1668E_I2S_RATES,
  218. .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
  219. SNDRV_PCM_FMTBIT_S32_LE,},
  220. .ops = &ark1668e_i2s_dai_ops,
  221. .symmetric_rates = 1,
  222. };
  223. static struct snd_pcm_hardware ark1668e_pcm_hardware = {
  224. .info = (SNDRV_PCM_INFO_MMAP |
  225. SNDRV_PCM_INFO_MMAP_VALID |
  226. SNDRV_PCM_INFO_PAUSE |
  227. SNDRV_PCM_INFO_RESUME |
  228. SNDRV_PCM_INFO_INTERLEAVED |
  229. SNDRV_PCM_INFO_BLOCK_TRANSFER),
  230. .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
  231. SNDRV_PCM_FMTBIT_S32_LE,
  232. .rates = (SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 |
  233. SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 |
  234. SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |
  235. SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 |
  236. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
  237. SNDRV_PCM_RATE_192000 | SNDRV_PCM_RATE_8000),
  238. .rate_min = 8000,
  239. .rate_max = 192000,
  240. .channels_min = 1,
  241. .channels_max = 2,
  242. .buffer_bytes_max = 64 * 65536,
  243. .period_bytes_min = 64,
  244. .period_bytes_max = 65536,
  245. .periods_min = 1,
  246. .periods_max = 64,
  247. };
  248. static const struct snd_dmaengine_pcm_config
  249. ark1668e_i2s_dmaengine_pcm_config = {
  250. .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
  251. .pcm_hardware = &ark1668e_pcm_hardware,
  252. };
  253. static const struct snd_soc_component_driver ark1668e_i2s_component = {
  254. .name = DRV_NAME,
  255. };
  256. static irqreturn_t ark1668e_i2s_interrupt(int irq, void *dev_id)
  257. {
  258. struct ark1668e_i2s_dev *i2s = dev_id;
  259. u32 status;
  260. status = readl(i2s->base + I2S_SASR0);
  261. dev_dbg(i2s->dev, "ark1668e_i2s_interrupt status=0x%x.0x%x.\n", status, readl(i2s->base + I2S_SACR0));
  262. //printk("ark1668e_i2s_interrupt status=0x%x.0x%x.\n", status, readl(i2s->base + I2S_SACR0));
  263. writel(status, i2s->base + I2S_SAICR);
  264. //writel(0, i2s->base + I2S_SAICR);
  265. return IRQ_HANDLED;
  266. }
  267. static int ark1668e_i2s_drv_probe(struct platform_device *pdev)
  268. {
  269. struct ark1668e_i2s_dev *i2s;
  270. struct resource *res;
  271. u32 val;
  272. int ret = 0;
  273. i2s = devm_kzalloc(&pdev->dev, sizeof(struct ark1668e_i2s_dev), GFP_KERNEL);
  274. if (!i2s)
  275. return -ENOMEM;
  276. i2s->dev = &pdev->dev;
  277. //i2s resource
  278. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  279. i2s->base = devm_ioremap_resource(&pdev->dev, res);
  280. if (IS_ERR(i2s->base))
  281. return PTR_ERR(i2s->base);
  282. if (!of_property_read_u32(pdev->dev.of_node, "nco-reg", &val))
  283. i2s->nco_reg = val;
  284. if (of_property_read_bool(pdev->dev.of_node, "full-duplex-mode"))
  285. i2s->full_duplex_en = 1;
  286. //printk(">>>>>>>>>>>>>>>>>>i2s->full_duplex_en = %d \n",i2s->full_duplex_en);
  287. i2s->clk = of_clk_get(pdev->dev.of_node, 0);
  288. if (IS_ERR(i2s->clk))
  289. return PTR_ERR(i2s->clk);
  290. i2s->irq = platform_get_irq(pdev, 0);
  291. if (i2s->irq < 0)
  292. return i2s->irq;
  293. ret = devm_request_irq(i2s->dev, i2s->irq, ark1668e_i2s_interrupt,
  294. IRQF_SHARED, KBUILD_MODNAME, i2s);
  295. if (ret)
  296. return ret;
  297. /* DMA parameters */
  298. i2s->playback_dma_data.addr = res->start + I2S_SADR;
  299. i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  300. i2s->playback_dma_data.maxburst = 16;
  301. i2s->capture_dma_data.addr = res->start + I2S_SADR;
  302. i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  303. i2s->capture_dma_data.maxburst = 16;
  304. dev_set_drvdata(&pdev->dev, i2s);
  305. ret = devm_snd_soc_register_component(&pdev->dev,
  306. &ark1668e_i2s_component,
  307. &ark1668e_i2s_dai, 1);
  308. if (ret) {
  309. dev_err(&pdev->dev, "Could not register DAI\n");
  310. return ret;
  311. }
  312. i2s_poweron(i2s);
  313. ret = devm_snd_dmaengine_pcm_register(&pdev->dev,
  314. &ark1668e_i2s_dmaengine_pcm_config,
  315. 0);
  316. if (ret) {
  317. dev_err(&pdev->dev, "Could not register PCM\n");
  318. return ret;
  319. }
  320. return 0;
  321. }
  322. static const struct of_device_id ark1668e_i2s_match[] = {
  323. { .compatible = "arkmicro,ark1668e-i2s", },
  324. {},
  325. };
  326. static struct platform_driver ark1668e_i2s_driver = {
  327. .probe = ark1668e_i2s_drv_probe,
  328. .driver = {
  329. .name = DRV_NAME,
  330. .of_match_table = of_match_ptr(ark1668e_i2s_match),
  331. },
  332. };
  333. module_platform_driver(ark1668e_i2s_driver);
  334. MODULE_DESCRIPTION("ARK I2S SoC Interface");
  335. MODULE_ALIAS("platform:" DRV_NAME);
  336. MODULE_AUTHOR("Sim");
  337. MODULE_LICENSE("GPL v2");