Kconfig 9.2 KB

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  1. # SPDX-License-Identifier: GPL-2.0
  2. menu "Platform support"
  3. source "arch/powerpc/platforms/powernv/Kconfig"
  4. source "arch/powerpc/platforms/pseries/Kconfig"
  5. source "arch/powerpc/platforms/chrp/Kconfig"
  6. source "arch/powerpc/platforms/512x/Kconfig"
  7. source "arch/powerpc/platforms/52xx/Kconfig"
  8. source "arch/powerpc/platforms/powermac/Kconfig"
  9. source "arch/powerpc/platforms/maple/Kconfig"
  10. source "arch/powerpc/platforms/pasemi/Kconfig"
  11. source "arch/powerpc/platforms/ps3/Kconfig"
  12. source "arch/powerpc/platforms/cell/Kconfig"
  13. source "arch/powerpc/platforms/8xx/Kconfig"
  14. source "arch/powerpc/platforms/82xx/Kconfig"
  15. source "arch/powerpc/platforms/83xx/Kconfig"
  16. source "arch/powerpc/platforms/85xx/Kconfig"
  17. source "arch/powerpc/platforms/86xx/Kconfig"
  18. source "arch/powerpc/platforms/embedded6xx/Kconfig"
  19. source "arch/powerpc/platforms/44x/Kconfig"
  20. source "arch/powerpc/platforms/40x/Kconfig"
  21. source "arch/powerpc/platforms/amigaone/Kconfig"
  22. config KVM_GUEST
  23. bool "KVM Guest support"
  24. default n
  25. select EPAPR_PARAVIRT
  26. ---help---
  27. This option enables various optimizations for running under the KVM
  28. hypervisor. Overhead for the kernel when not running inside KVM should
  29. be minimal.
  30. In case of doubt, say Y
  31. config EPAPR_PARAVIRT
  32. bool "ePAPR para-virtualization support"
  33. default n
  34. help
  35. Enables ePAPR para-virtualization support for guests.
  36. In case of doubt, say Y
  37. config PPC_NATIVE
  38. bool
  39. depends on 6xx || PPC64
  40. help
  41. Support for running natively on the hardware, i.e. without
  42. a hypervisor. This option is not user-selectable but should
  43. be selected by all platforms that need it.
  44. config PPC_OF_BOOT_TRAMPOLINE
  45. bool "Support booting from Open Firmware or yaboot"
  46. depends on 6xx || PPC64
  47. default y
  48. help
  49. Support from booting from Open Firmware or yaboot using an
  50. Open Firmware client interface. This enables the kernel to
  51. communicate with open firmware to retrieve system information
  52. such as the device tree.
  53. In case of doubt, say Y
  54. config PPC_DT_CPU_FTRS
  55. bool "Device-tree based CPU feature discovery & setup"
  56. depends on PPC_BOOK3S_64
  57. default y
  58. help
  59. This enables code to use a new device tree binding for describing CPU
  60. compatibility and features. Saying Y here will attempt to use the new
  61. binding if the firmware provides it. Currently only the skiboot
  62. firmware provides this binding.
  63. If you're not sure say Y.
  64. config UDBG_RTAS_CONSOLE
  65. bool "RTAS based debug console"
  66. depends on PPC_RTAS
  67. default n
  68. config PPC_SMP_MUXED_IPI
  69. bool
  70. help
  71. Select this option if your platform supports SMP and your
  72. interrupt controller provides less than 4 interrupts to each
  73. cpu. This will enable the generic code to multiplex the 4
  74. messages on to one ipi.
  75. config IPIC
  76. bool
  77. default n
  78. config MPIC
  79. bool
  80. default n
  81. config MPIC_TIMER
  82. bool "MPIC Global Timer"
  83. depends on MPIC && FSL_SOC
  84. default n
  85. help
  86. The MPIC global timer is a hardware timer inside the
  87. Freescale PIC complying with OpenPIC standard. When the
  88. specified interval times out, the hardware timer generates
  89. an interrupt. The driver currently is only tested on fsl
  90. chip, but it can potentially support other global timers
  91. complying with the OpenPIC standard.
  92. config FSL_MPIC_TIMER_WAKEUP
  93. tristate "Freescale MPIC global timer wakeup driver"
  94. depends on FSL_SOC && MPIC_TIMER && PM
  95. default n
  96. help
  97. The driver provides a way to wake up the system by MPIC
  98. timer.
  99. e.g. "echo 5 > /sys/devices/system/mpic/timer_wakeup"
  100. config PPC_EPAPR_HV_PIC
  101. bool
  102. default n
  103. select EPAPR_PARAVIRT
  104. config MPIC_WEIRD
  105. bool
  106. default n
  107. config MPIC_MSGR
  108. bool "MPIC message register support"
  109. depends on MPIC
  110. default n
  111. help
  112. Enables support for the MPIC message registers. These
  113. registers are used for inter-processor communication.
  114. config PPC_I8259
  115. bool
  116. default n
  117. config U3_DART
  118. bool
  119. depends on PPC64
  120. default n
  121. config PPC_RTAS
  122. bool
  123. default n
  124. config RTAS_ERROR_LOGGING
  125. bool
  126. depends on PPC_RTAS
  127. default n
  128. config PPC_RTAS_DAEMON
  129. bool
  130. depends on PPC_RTAS
  131. default n
  132. config RTAS_PROC
  133. bool "Proc interface to RTAS"
  134. depends on PPC_RTAS && PROC_FS
  135. default y
  136. config RTAS_FLASH
  137. tristate "Firmware flash interface"
  138. depends on PPC64 && RTAS_PROC
  139. config MMIO_NVRAM
  140. bool
  141. default n
  142. config MPIC_U3_HT_IRQS
  143. bool
  144. default n
  145. config MPIC_BROKEN_REGREAD
  146. bool
  147. depends on MPIC
  148. help
  149. This option enables a MPIC driver workaround for some chips
  150. that have a bug that causes some interrupt source information
  151. to not read back properly. It is safe to use on other chips as
  152. well, but enabling it uses about 8KB of memory to keep copies
  153. of the register contents in software.
  154. config EEH
  155. bool
  156. depends on (PPC_POWERNV || PPC_PSERIES) && PCI
  157. default y
  158. config PPC_MPC106
  159. bool
  160. default n
  161. config PPC_970_NAP
  162. bool
  163. default n
  164. config PPC_P7_NAP
  165. bool
  166. default n
  167. config PPC_INDIRECT_PIO
  168. bool
  169. select GENERIC_IOMAP
  170. config PPC_INDIRECT_MMIO
  171. bool
  172. config PPC_IO_WORKAROUNDS
  173. bool
  174. source "drivers/cpufreq/Kconfig"
  175. menu "CPUIdle driver"
  176. source "drivers/cpuidle/Kconfig"
  177. endmenu
  178. config PPC601_SYNC_FIX
  179. bool "Workarounds for PPC601 bugs"
  180. depends on 6xx && PPC_PMAC
  181. help
  182. Some versions of the PPC601 (the first PowerPC chip) have bugs which
  183. mean that extra synchronization instructions are required near
  184. certain instructions, typically those that make major changes to the
  185. CPU state. These extra instructions reduce performance slightly.
  186. If you say N here, these extra instructions will not be included,
  187. resulting in a kernel which will run faster but may not run at all
  188. on some systems with the PPC601 chip.
  189. If in doubt, say Y here.
  190. config TAU
  191. bool "On-chip CPU temperature sensor support"
  192. depends on 6xx
  193. help
  194. G3 and G4 processors have an on-chip temperature sensor called the
  195. 'Thermal Assist Unit (TAU)', which, in theory, can measure the on-die
  196. temperature within 2-4 degrees Celsius. This option shows the current
  197. on-die temperature in /proc/cpuinfo if the cpu supports it.
  198. Unfortunately, this sensor is very inaccurate when uncalibrated, so
  199. don't assume the cpu temp is actually what /proc/cpuinfo says it is.
  200. config TAU_INT
  201. bool "Interrupt driven TAU driver (EXPERIMENTAL)"
  202. depends on TAU
  203. ---help---
  204. The TAU supports an interrupt driven mode which causes an interrupt
  205. whenever the temperature goes out of range. This is the fastest way
  206. to get notified the temp has exceeded a range. With this option off,
  207. a timer is used to re-check the temperature periodically.
  208. If in doubt, say N here.
  209. config TAU_AVERAGE
  210. bool "Average high and low temp"
  211. depends on TAU
  212. ---help---
  213. The TAU hardware can compare the temperature to an upper and lower
  214. bound. The default behavior is to show both the upper and lower
  215. bound in /proc/cpuinfo. If the range is large, the temperature is
  216. either changing a lot, or the TAU hardware is broken (likely on some
  217. G4's). If the range is small (around 4 degrees), the temperature is
  218. relatively stable. If you say Y here, a single temperature value,
  219. halfway between the upper and lower bounds, will be reported in
  220. /proc/cpuinfo.
  221. If in doubt, say N here.
  222. config QE_GPIO
  223. bool "QE GPIO support"
  224. depends on QUICC_ENGINE
  225. select GPIOLIB
  226. help
  227. Say Y here if you're going to use hardware that connects to the
  228. QE GPIOs.
  229. config CPM2
  230. bool "Enable support for the CPM2 (Communications Processor Module)"
  231. depends on (FSL_SOC_BOOKE && PPC32) || 8260
  232. select CPM
  233. select PPC_PCI_CHOICE
  234. select GPIOLIB
  235. help
  236. The CPM2 (Communications Processor Module) is a coprocessor on
  237. embedded CPUs made by Freescale. Selecting this option means that
  238. you wish to build a kernel for a machine with a CPM2 coprocessor
  239. on it (826x, 827x, 8560).
  240. config FSL_ULI1575
  241. bool
  242. default n
  243. select GENERIC_ISA_DMA
  244. help
  245. Supports for the ULI1575 PCIe south bridge that exists on some
  246. Freescale reference boards. The boards all use the ULI in pretty
  247. much the same way.
  248. config CPM
  249. bool
  250. select GENERIC_ALLOCATOR
  251. config OF_RTC
  252. bool
  253. help
  254. Uses information from the OF or flattened device tree to instantiate
  255. platform devices for direct mapped RTC chips like the DS1742 or DS1743.
  256. config GEN_RTC
  257. bool "Use the platform RTC operations from user space"
  258. select RTC_CLASS
  259. select RTC_DRV_GENERIC
  260. help
  261. This option provides backwards compatibility with the old gen_rtc.ko
  262. module that was traditionally used for old PowerPC machines.
  263. Platforms should migrate to enabling the RTC_DRV_GENERIC by hand
  264. replacing their get_rtc_time/set_rtc_time callbacks with
  265. a proper RTC device driver.
  266. config SIMPLE_GPIO
  267. bool "Support for simple, memory-mapped GPIO controllers"
  268. depends on PPC
  269. select GPIOLIB
  270. help
  271. Say Y here to support simple, memory-mapped GPIO controllers.
  272. These are usually BCSRs used to control board's switches, LEDs,
  273. chip-selects, Ethernet/USB PHY's power and various other small
  274. on-board peripherals.
  275. config MCU_MPC8349EMITX
  276. bool "MPC8349E-mITX MCU driver"
  277. depends on I2C=y && PPC_83xx
  278. select GPIOLIB
  279. help
  280. Say Y here to enable soft power-off functionality on the Freescale
  281. boards with the MPC8349E-mITX-compatible MCU chips. This driver will
  282. also register MCU GPIOs with the generic GPIO API, so you'll able
  283. to use MCU pins as GPIOs.
  284. config XILINX_PCI
  285. bool "Xilinx PCI host bridge support"
  286. depends on PCI && XILINX_VIRTEX
  287. endmenu