ccu-sun8i-v3s.h 1.7 KB

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  1. /*
  2. * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz>
  3. *
  4. * Based on ccu-sun8i-h3.h, which is:
  5. * Copyright (c) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. */
  17. #ifndef _CCU_SUN8I_H3_H_
  18. #define _CCU_SUN8I_H3_H_
  19. #include <dt-bindings/clock/sun8i-v3s-ccu.h>
  20. #include <dt-bindings/reset/sun8i-v3s-ccu.h>
  21. #define CLK_PLL_CPU 0
  22. #define CLK_PLL_AUDIO_BASE 1
  23. #define CLK_PLL_AUDIO 2
  24. #define CLK_PLL_AUDIO_2X 3
  25. #define CLK_PLL_AUDIO_4X 4
  26. #define CLK_PLL_AUDIO_8X 5
  27. #define CLK_PLL_VIDEO 6
  28. #define CLK_PLL_VE 7
  29. #define CLK_PLL_DDR0 8
  30. #define CLK_PLL_PERIPH0 9
  31. #define CLK_PLL_PERIPH0_2X 10
  32. #define CLK_PLL_ISP 11
  33. #define CLK_PLL_PERIPH1 12
  34. /* Reserve one number for not implemented and not used PLL_DDR1 */
  35. /* The CPU clock is exported */
  36. #define CLK_AXI 15
  37. #define CLK_AHB1 16
  38. #define CLK_APB1 17
  39. #define CLK_APB2 18
  40. #define CLK_AHB2 19
  41. /* All the bus gates are exported */
  42. /* The first bunch of module clocks are exported */
  43. #define CLK_DRAM 58
  44. /* All the DRAM gates are exported */
  45. /* Some more module clocks are exported */
  46. #define CLK_MBUS 72
  47. /* And the GPU module clock is exported */
  48. #define CLK_PLL_DDR1 74
  49. #define CLK_NUMBER (CLK_PLL_DDR1 + 1)
  50. #endif /* _CCU_SUN8I_H3_H_ */