dbau1x00.c 2.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2003
  4. * Thomas.Lange@corelatus.se
  5. */
  6. #include <common.h>
  7. #include <command.h>
  8. #include <mach/au1x00.h>
  9. #include <asm/mipsregs.h>
  10. #include <asm/io.h>
  11. DECLARE_GLOBAL_DATA_PTR;
  12. int dram_init(void)
  13. {
  14. /* Sdram is setup by assembler code */
  15. /* If memory could be changed, we should return the true value here */
  16. gd->ram_size = MEM_SIZE * 1024 * 1024;
  17. return 0;
  18. }
  19. #define BCSR_PCMCIA_PC0DRVEN 0x0010
  20. #define BCSR_PCMCIA_PC0RST 0x0080
  21. /* In arch/mips/cpu/cpu.c */
  22. void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 );
  23. int checkboard (void)
  24. {
  25. #ifdef CONFIG_IDE_PCMCIA
  26. u16 status;
  27. volatile u32 *pcmcia_bcsr = (u32*)(DB1XX0_BCSR_ADDR+0x10);
  28. #endif /* CONFIG_IDE_PCMCIA */
  29. volatile u32 *phy = (u32*)(DB1XX0_BCSR_ADDR+0xC);
  30. volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL;
  31. u32 proc_id;
  32. *sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */
  33. proc_id = read_c0_prid();
  34. switch (proc_id >> 24) {
  35. case 0:
  36. puts ("Board: Merlot (DbAu1000)\n");
  37. printf ("CPU: Au1000 396 MHz, id: 0x%02x, rev: 0x%02x\n",
  38. (proc_id >> 8) & 0xFF, proc_id & 0xFF);
  39. break;
  40. case 1:
  41. puts ("Board: DbAu1500\n");
  42. printf ("CPU: Au1500, id: 0x%02x, rev: 0x%02x\n",
  43. (proc_id >> 8) & 0xFF, proc_id & 0xFF);
  44. break;
  45. case 2:
  46. puts ("Board: DbAu1100\n");
  47. printf ("CPU: Au1100, id: 0x%02x, rev: 0x%02x\n",
  48. (proc_id >> 8) & 0xFF, proc_id & 0xFF);
  49. break;
  50. case 3:
  51. puts ("Board: DbAu1550\n");
  52. printf ("CPU: Au1550, id: 0x%02x, rev: 0x%02x\n",
  53. (proc_id >> 8) & 0xFF, proc_id & 0xFF);
  54. break;
  55. default:
  56. printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
  57. }
  58. set_io_port_base(0);
  59. #ifdef CONFIG_IDE_PCMCIA
  60. /* Enable 3.3 V on slot 0 ( VCC )
  61. No 5V */
  62. status = 4;
  63. *pcmcia_bcsr = status;
  64. status |= BCSR_PCMCIA_PC0DRVEN;
  65. *pcmcia_bcsr = status;
  66. au_sync();
  67. udelay(300*1000);
  68. status |= BCSR_PCMCIA_PC0RST;
  69. *pcmcia_bcsr = status;
  70. au_sync();
  71. udelay(100*1000);
  72. /* PCMCIA is on a 36 bit physical address.
  73. We need to map it into a 32 bit addresses */
  74. #if 0
  75. /* We dont need theese unless we run whole pcmcia package */
  76. write_one_tlb(20, /* index */
  77. 0x01ffe000, /* Pagemask, 16 MB pages */
  78. CONFIG_SYS_PCMCIA_IO_BASE, /* Hi */
  79. 0x3C000017, /* Lo0 */
  80. 0x3C200017); /* Lo1 */
  81. write_one_tlb(21, /* index */
  82. 0x01ffe000, /* Pagemask, 16 MB pages */
  83. CONFIG_SYS_PCMCIA_ATTR_BASE, /* Hi */
  84. 0x3D000017, /* Lo0 */
  85. 0x3D200017); /* Lo1 */
  86. #endif /* 0 */
  87. write_one_tlb(22, /* index */
  88. 0x01ffe000, /* Pagemask, 16 MB pages */
  89. CONFIG_SYS_PCMCIA_MEM_ADDR, /* Hi */
  90. 0x3E000017, /* Lo0 */
  91. 0x3E200017); /* Lo1 */
  92. #endif /* CONFIG_IDE_PCMCIA */
  93. /* Release reset of ethernet PHY chips */
  94. /* Always do this, because linux does not know about it */
  95. *phy = 3;
  96. return 0;
  97. }