tegra210-p2597.dtsi 48 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. #include <dt-bindings/input/input.h>
  3. / {
  4. model = "NVIDIA Tegra210 P2597 I/O board";
  5. compatible = "nvidia,p2597", "nvidia,tegra210";
  6. host1x@50000000 {
  7. dpaux@54040000 {
  8. status = "okay";
  9. };
  10. sor@54580000 {
  11. status = "okay";
  12. avdd-io-supply = <&avdd_1v05>;
  13. vdd-pll-supply = <&vdd_1v8>;
  14. hdmi-supply = <&vdd_hdmi>;
  15. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  16. nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1)
  17. GPIO_ACTIVE_LOW>;
  18. };
  19. };
  20. pinmux: pinmux@700008d4 {
  21. pinctrl-names = "boot";
  22. pinctrl-0 = <&state_boot>;
  23. state_boot: pinmux {
  24. pex_l0_rst_n_pa0 {
  25. nvidia,pins = "pex_l0_rst_n_pa0";
  26. nvidia,function = "pe0";
  27. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  28. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  29. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  30. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  31. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  32. };
  33. pex_l0_clkreq_n_pa1 {
  34. nvidia,pins = "pex_l0_clkreq_n_pa1";
  35. nvidia,function = "pe0";
  36. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  37. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  38. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  39. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  40. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  41. };
  42. pex_wake_n_pa2 {
  43. nvidia,pins = "pex_wake_n_pa2";
  44. nvidia,function = "pe";
  45. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  46. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  47. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  48. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  49. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  50. };
  51. pex_l1_rst_n_pa3 {
  52. nvidia,pins = "pex_l1_rst_n_pa3";
  53. nvidia,function = "pe1";
  54. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  55. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  56. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  57. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  58. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  59. };
  60. pex_l1_clkreq_n_pa4 {
  61. nvidia,pins = "pex_l1_clkreq_n_pa4";
  62. nvidia,function = "pe1";
  63. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  64. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  65. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  66. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  67. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  68. };
  69. sata_led_active_pa5 {
  70. nvidia,pins = "sata_led_active_pa5";
  71. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  72. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  73. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  74. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  75. };
  76. pa6 {
  77. nvidia,pins = "pa6";
  78. nvidia,function = "sata";
  79. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  80. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  81. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  82. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  83. };
  84. dap1_fs_pb0 {
  85. nvidia,pins = "dap1_fs_pb0";
  86. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  87. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  88. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  89. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  90. };
  91. dap1_din_pb1 {
  92. nvidia,pins = "dap1_din_pb1";
  93. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  94. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  95. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  96. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  97. };
  98. dap1_dout_pb2 {
  99. nvidia,pins = "dap1_dout_pb2";
  100. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  101. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  102. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  103. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  104. };
  105. dap1_sclk_pb3 {
  106. nvidia,pins = "dap1_sclk_pb3";
  107. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  108. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  109. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  110. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  111. };
  112. spi2_mosi_pb4 {
  113. nvidia,pins = "spi2_mosi_pb4";
  114. nvidia,function = "spi2";
  115. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  116. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  117. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  118. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  119. };
  120. spi2_miso_pb5 {
  121. nvidia,pins = "spi2_miso_pb5";
  122. nvidia,function = "spi2";
  123. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  124. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  125. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  126. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  127. };
  128. spi2_sck_pb6 {
  129. nvidia,pins = "spi2_sck_pb6";
  130. nvidia,function = "spi2";
  131. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  132. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  133. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  134. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  135. };
  136. spi2_cs0_pb7 {
  137. nvidia,pins = "spi2_cs0_pb7";
  138. nvidia,function = "spi2";
  139. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  140. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  141. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  142. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  143. };
  144. spi1_mosi_pc0 {
  145. nvidia,pins = "spi1_mosi_pc0";
  146. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  147. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  148. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  149. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  150. };
  151. spi1_miso_pc1 {
  152. nvidia,pins = "spi1_miso_pc1";
  153. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  154. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  155. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  156. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  157. };
  158. spi1_sck_pc2 {
  159. nvidia,pins = "spi1_sck_pc2";
  160. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  161. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  162. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  163. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  164. };
  165. spi1_cs0_pc3 {
  166. nvidia,pins = "spi1_cs0_pc3";
  167. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  168. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  169. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  170. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  171. };
  172. spi1_cs1_pc4 {
  173. nvidia,pins = "spi1_cs1_pc4";
  174. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  175. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  176. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  177. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  178. };
  179. spi4_sck_pc5 {
  180. nvidia,pins = "spi4_sck_pc5";
  181. nvidia,function = "spi4";
  182. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  183. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  184. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  185. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  186. };
  187. spi4_cs0_pc6 {
  188. nvidia,pins = "spi4_cs0_pc6";
  189. nvidia,function = "spi4";
  190. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  191. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  192. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  193. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  194. };
  195. spi4_mosi_pc7 {
  196. nvidia,pins = "spi4_mosi_pc7";
  197. nvidia,function = "spi4";
  198. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  199. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  200. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  201. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  202. };
  203. spi4_miso_pd0 {
  204. nvidia,pins = "spi4_miso_pd0";
  205. nvidia,function = "spi4";
  206. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  207. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  208. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  209. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  210. };
  211. uart3_tx_pd1 {
  212. nvidia,pins = "uart3_tx_pd1";
  213. nvidia,function = "uartc";
  214. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  215. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  216. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  217. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  218. };
  219. uart3_rx_pd2 {
  220. nvidia,pins = "uart3_rx_pd2";
  221. nvidia,function = "uartc";
  222. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  223. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  224. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  225. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  226. };
  227. uart3_rts_pd3 {
  228. nvidia,pins = "uart3_rts_pd3";
  229. nvidia,function = "uartc";
  230. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  231. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  232. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  233. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  234. };
  235. uart3_cts_pd4 {
  236. nvidia,pins = "uart3_cts_pd4";
  237. nvidia,function = "uartc";
  238. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  239. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  240. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  241. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  242. };
  243. dmic1_clk_pe0 {
  244. nvidia,pins = "dmic1_clk_pe0";
  245. nvidia,function = "i2s3";
  246. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  247. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  248. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  249. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  250. };
  251. dmic1_dat_pe1 {
  252. nvidia,pins = "dmic1_dat_pe1";
  253. nvidia,function = "i2s3";
  254. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  255. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  256. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  257. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  258. };
  259. dmic2_clk_pe2 {
  260. nvidia,pins = "dmic2_clk_pe2";
  261. nvidia,function = "i2s3";
  262. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  263. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  264. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  265. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  266. };
  267. dmic2_dat_pe3 {
  268. nvidia,pins = "dmic2_dat_pe3";
  269. nvidia,function = "i2s3";
  270. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  271. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  272. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  273. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  274. };
  275. dmic3_clk_pe4 {
  276. nvidia,pins = "dmic3_clk_pe4";
  277. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  278. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  279. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  280. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  281. };
  282. dmic3_dat_pe5 {
  283. nvidia,pins = "dmic3_dat_pe5";
  284. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  285. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  286. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  287. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  288. };
  289. pe6 {
  290. nvidia,pins = "pe6";
  291. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  292. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  293. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  294. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  295. };
  296. pe7 {
  297. nvidia,pins = "pe7";
  298. nvidia,function = "pwm3";
  299. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  300. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  301. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  302. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  303. };
  304. gen3_i2c_scl_pf0 {
  305. nvidia,pins = "gen3_i2c_scl_pf0";
  306. nvidia,function = "i2c3";
  307. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  308. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  309. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  310. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  311. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  312. };
  313. gen3_i2c_sda_pf1 {
  314. nvidia,pins = "gen3_i2c_sda_pf1";
  315. nvidia,function = "i2c3";
  316. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  317. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  318. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  319. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  320. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  321. };
  322. uart2_tx_pg0 {
  323. nvidia,pins = "uart2_tx_pg0";
  324. nvidia,function = "uartb";
  325. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  326. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  327. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  328. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  329. };
  330. uart2_rx_pg1 {
  331. nvidia,pins = "uart2_rx_pg1";
  332. nvidia,function = "uartb";
  333. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  334. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  335. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  336. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  337. };
  338. uart2_rts_pg2 {
  339. nvidia,pins = "uart2_rts_pg2";
  340. nvidia,function = "uartb";
  341. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  342. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  343. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  344. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  345. };
  346. uart2_cts_pg3 {
  347. nvidia,pins = "uart2_cts_pg3";
  348. nvidia,function = "uartb";
  349. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  350. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  351. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  352. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  353. };
  354. wifi_en_ph0 {
  355. nvidia,pins = "wifi_en_ph0";
  356. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  357. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  358. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  359. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  360. };
  361. wifi_rst_ph1 {
  362. nvidia,pins = "wifi_rst_ph1";
  363. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  364. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  365. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  366. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  367. };
  368. wifi_wake_ap_ph2 {
  369. nvidia,pins = "wifi_wake_ap_ph2";
  370. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  371. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  372. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  373. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  374. };
  375. ap_wake_bt_ph3 {
  376. nvidia,pins = "ap_wake_bt_ph3";
  377. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  378. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  379. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  380. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  381. };
  382. bt_rst_ph4 {
  383. nvidia,pins = "bt_rst_ph4";
  384. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  385. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  386. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  387. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  388. };
  389. bt_wake_ap_ph5 {
  390. nvidia,pins = "bt_wake_ap_ph5";
  391. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  392. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  393. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  394. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  395. };
  396. ph6 {
  397. nvidia,pins = "ph6";
  398. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  399. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  400. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  401. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  402. };
  403. ap_wake_nfc_ph7 {
  404. nvidia,pins = "ap_wake_nfc_ph7";
  405. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  406. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  407. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  408. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  409. };
  410. nfc_en_pi0 {
  411. nvidia,pins = "nfc_en_pi0";
  412. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  413. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  414. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  415. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  416. };
  417. nfc_int_pi1 {
  418. nvidia,pins = "nfc_int_pi1";
  419. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  420. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  421. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  422. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  423. };
  424. gps_en_pi2 {
  425. nvidia,pins = "gps_en_pi2";
  426. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  427. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  428. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  429. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  430. };
  431. gps_rst_pi3 {
  432. nvidia,pins = "gps_rst_pi3";
  433. nvidia,function = "rsvd0";
  434. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  435. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  436. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  437. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  438. };
  439. uart4_tx_pi4 {
  440. nvidia,pins = "uart4_tx_pi4";
  441. nvidia,function = "uartd";
  442. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  443. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  444. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  445. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  446. };
  447. uart4_rx_pi5 {
  448. nvidia,pins = "uart4_rx_pi5";
  449. nvidia,function = "uartd";
  450. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  451. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  452. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  453. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  454. };
  455. uart4_rts_pi6 {
  456. nvidia,pins = "uart4_rts_pi6";
  457. nvidia,function = "uartd";
  458. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  459. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  460. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  461. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  462. };
  463. uart4_cts_pi7 {
  464. nvidia,pins = "uart4_cts_pi7";
  465. nvidia,function = "uartd";
  466. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  467. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  468. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  469. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  470. };
  471. gen1_i2c_sda_pj0 {
  472. nvidia,pins = "gen1_i2c_sda_pj0";
  473. nvidia,function = "i2c1";
  474. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  475. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  476. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  477. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  478. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  479. };
  480. gen1_i2c_scl_pj1 {
  481. nvidia,pins = "gen1_i2c_scl_pj1";
  482. nvidia,function = "i2c1";
  483. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  484. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  485. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  486. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  487. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  488. };
  489. gen2_i2c_scl_pj2 {
  490. nvidia,pins = "gen2_i2c_scl_pj2";
  491. nvidia,function = "i2c2";
  492. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  493. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  494. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  495. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  496. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  497. };
  498. gen2_i2c_sda_pj3 {
  499. nvidia,pins = "gen2_i2c_sda_pj3";
  500. nvidia,function = "i2c2";
  501. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  502. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  503. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  504. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  505. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  506. };
  507. dap4_fs_pj4 {
  508. nvidia,pins = "dap4_fs_pj4";
  509. nvidia,function = "i2s4b";
  510. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  511. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  512. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  513. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  514. };
  515. dap4_din_pj5 {
  516. nvidia,pins = "dap4_din_pj5";
  517. nvidia,function = "i2s4b";
  518. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  519. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  520. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  521. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  522. };
  523. dap4_dout_pj6 {
  524. nvidia,pins = "dap4_dout_pj6";
  525. nvidia,function = "i2s4b";
  526. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  527. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  528. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  529. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  530. };
  531. dap4_sclk_pj7 {
  532. nvidia,pins = "dap4_sclk_pj7";
  533. nvidia,function = "i2s4b";
  534. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  535. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  536. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  537. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  538. };
  539. pk0 {
  540. nvidia,pins = "pk0";
  541. nvidia,function = "i2s5b";
  542. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  543. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  544. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  545. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  546. };
  547. pk1 {
  548. nvidia,pins = "pk1";
  549. nvidia,function = "i2s5b";
  550. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  551. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  552. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  553. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  554. };
  555. pk2 {
  556. nvidia,pins = "pk2";
  557. nvidia,function = "i2s5b";
  558. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  559. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  560. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  561. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  562. };
  563. pk3 {
  564. nvidia,pins = "pk3";
  565. nvidia,function = "i2s5b";
  566. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  567. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  568. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  569. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  570. };
  571. pk4 {
  572. nvidia,pins = "pk4";
  573. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  574. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  575. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  576. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  577. };
  578. pk5 {
  579. nvidia,pins = "pk5";
  580. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  581. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  582. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  583. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  584. };
  585. pk6 {
  586. nvidia,pins = "pk6";
  587. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  588. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  589. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  590. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  591. };
  592. pk7 {
  593. nvidia,pins = "pk7";
  594. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  595. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  596. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  597. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  598. };
  599. pl0 {
  600. nvidia,pins = "pl0";
  601. nvidia,function = "rsvd0";
  602. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  603. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  604. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  605. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  606. };
  607. pl1 {
  608. nvidia,pins = "pl1";
  609. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  610. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  611. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  612. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  613. };
  614. sdmmc1_clk_pm0 {
  615. nvidia,pins = "sdmmc1_clk_pm0";
  616. nvidia,function = "sdmmc1";
  617. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  618. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  619. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  620. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  621. };
  622. sdmmc1_cmd_pm1 {
  623. nvidia,pins = "sdmmc1_cmd_pm1";
  624. nvidia,function = "sdmmc1";
  625. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  626. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  627. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  628. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  629. };
  630. sdmmc1_dat3_pm2 {
  631. nvidia,pins = "sdmmc1_dat3_pm2";
  632. nvidia,function = "sdmmc1";
  633. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  634. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  635. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  636. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  637. };
  638. sdmmc1_dat2_pm3 {
  639. nvidia,pins = "sdmmc1_dat2_pm3";
  640. nvidia,function = "sdmmc1";
  641. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  642. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  643. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  644. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  645. };
  646. sdmmc1_dat1_pm4 {
  647. nvidia,pins = "sdmmc1_dat1_pm4";
  648. nvidia,function = "sdmmc1";
  649. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  650. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  651. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  652. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  653. };
  654. sdmmc1_dat0_pm5 {
  655. nvidia,pins = "sdmmc1_dat0_pm5";
  656. nvidia,function = "sdmmc1";
  657. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  658. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  659. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  660. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  661. };
  662. sdmmc3_clk_pp0 {
  663. nvidia,pins = "sdmmc3_clk_pp0";
  664. nvidia,function = "sdmmc3";
  665. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  666. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  667. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  668. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  669. };
  670. sdmmc3_cmd_pp1 {
  671. nvidia,pins = "sdmmc3_cmd_pp1";
  672. nvidia,function = "sdmmc3";
  673. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  674. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  675. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  676. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  677. };
  678. sdmmc3_dat3_pp2 {
  679. nvidia,pins = "sdmmc3_dat3_pp2";
  680. nvidia,function = "sdmmc3";
  681. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  682. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  683. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  684. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  685. };
  686. sdmmc3_dat2_pp3 {
  687. nvidia,pins = "sdmmc3_dat2_pp3";
  688. nvidia,function = "sdmmc3";
  689. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  690. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  691. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  692. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  693. };
  694. sdmmc3_dat1_pp4 {
  695. nvidia,pins = "sdmmc3_dat1_pp4";
  696. nvidia,function = "sdmmc3";
  697. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  698. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  699. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  700. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  701. };
  702. sdmmc3_dat0_pp5 {
  703. nvidia,pins = "sdmmc3_dat0_pp5";
  704. nvidia,function = "sdmmc3";
  705. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  706. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  707. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  708. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  709. };
  710. cam1_mclk_ps0 {
  711. nvidia,pins = "cam1_mclk_ps0";
  712. nvidia,function = "extperiph3";
  713. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  714. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  715. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  716. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  717. };
  718. cam2_mclk_ps1 {
  719. nvidia,pins = "cam2_mclk_ps1";
  720. nvidia,function = "extperiph3";
  721. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  722. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  723. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  724. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  725. };
  726. cam_i2c_scl_ps2 {
  727. nvidia,pins = "cam_i2c_scl_ps2";
  728. nvidia,function = "i2cvi";
  729. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  730. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  731. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  732. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  733. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  734. };
  735. cam_i2c_sda_ps3 {
  736. nvidia,pins = "cam_i2c_sda_ps3";
  737. nvidia,function = "i2cvi";
  738. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  739. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  740. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  741. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  742. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  743. };
  744. cam_rst_ps4 {
  745. nvidia,pins = "cam_rst_ps4";
  746. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  747. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  748. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  749. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  750. };
  751. cam_af_en_ps5 {
  752. nvidia,pins = "cam_af_en_ps5";
  753. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  754. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  755. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  756. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  757. };
  758. cam_flash_en_ps6 {
  759. nvidia,pins = "cam_flash_en_ps6";
  760. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  761. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  762. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  763. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  764. };
  765. cam1_pwdn_ps7 {
  766. nvidia,pins = "cam1_pwdn_ps7";
  767. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  768. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  769. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  770. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  771. };
  772. cam2_pwdn_pt0 {
  773. nvidia,pins = "cam2_pwdn_pt0";
  774. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  775. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  776. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  777. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  778. };
  779. cam1_strobe_pt1 {
  780. nvidia,pins = "cam1_strobe_pt1";
  781. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  782. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  783. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  784. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  785. };
  786. uart1_tx_pu0 {
  787. nvidia,pins = "uart1_tx_pu0";
  788. nvidia,function = "uarta";
  789. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  790. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  791. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  792. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  793. };
  794. uart1_rx_pu1 {
  795. nvidia,pins = "uart1_rx_pu1";
  796. nvidia,function = "uarta";
  797. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  798. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  799. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  800. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  801. };
  802. uart1_rts_pu2 {
  803. nvidia,pins = "uart1_rts_pu2";
  804. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  805. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  806. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  807. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  808. };
  809. uart1_cts_pu3 {
  810. nvidia,pins = "uart1_cts_pu3";
  811. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  812. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  813. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  814. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  815. };
  816. lcd_bl_pwm_pv0 {
  817. nvidia,pins = "lcd_bl_pwm_pv0";
  818. nvidia,function = "pwm0";
  819. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  820. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  821. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  822. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  823. };
  824. lcd_bl_en_pv1 {
  825. nvidia,pins = "lcd_bl_en_pv1";
  826. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  827. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  828. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  829. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  830. };
  831. lcd_rst_pv2 {
  832. nvidia,pins = "lcd_rst_pv2";
  833. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  834. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  835. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  836. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  837. };
  838. lcd_gpio1_pv3 {
  839. nvidia,pins = "lcd_gpio1_pv3";
  840. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  841. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  842. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  843. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  844. };
  845. lcd_gpio2_pv4 {
  846. nvidia,pins = "lcd_gpio2_pv4";
  847. nvidia,function = "pwm1";
  848. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  849. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  850. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  851. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  852. };
  853. ap_ready_pv5 {
  854. nvidia,pins = "ap_ready_pv5";
  855. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  856. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  857. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  858. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  859. };
  860. touch_rst_pv6 {
  861. nvidia,pins = "touch_rst_pv6";
  862. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  863. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  864. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  865. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  866. };
  867. touch_clk_pv7 {
  868. nvidia,pins = "touch_clk_pv7";
  869. nvidia,function = "touch";
  870. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  871. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  872. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  873. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  874. };
  875. modem_wake_ap_px0 {
  876. nvidia,pins = "modem_wake_ap_px0";
  877. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  878. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  879. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  880. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  881. };
  882. touch_int_px1 {
  883. nvidia,pins = "touch_int_px1";
  884. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  885. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  886. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  887. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  888. };
  889. motion_int_px2 {
  890. nvidia,pins = "motion_int_px2";
  891. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  892. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  893. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  894. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  895. };
  896. als_prox_int_px3 {
  897. nvidia,pins = "als_prox_int_px3";
  898. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  899. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  900. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  901. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  902. };
  903. temp_alert_px4 {
  904. nvidia,pins = "temp_alert_px4";
  905. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  906. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  907. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  908. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  909. };
  910. button_power_on_px5 {
  911. nvidia,pins = "button_power_on_px5";
  912. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  913. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  914. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  915. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  916. };
  917. button_vol_up_px6 {
  918. nvidia,pins = "button_vol_up_px6";
  919. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  920. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  921. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  922. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  923. };
  924. button_vol_down_px7 {
  925. nvidia,pins = "button_vol_down_px7";
  926. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  927. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  928. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  929. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  930. };
  931. button_slide_sw_py0 {
  932. nvidia,pins = "button_slide_sw_py0";
  933. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  934. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  935. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  936. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  937. };
  938. button_home_py1 {
  939. nvidia,pins = "button_home_py1";
  940. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  941. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  942. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  943. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  944. };
  945. lcd_te_py2 {
  946. nvidia,pins = "lcd_te_py2";
  947. nvidia,function = "displaya";
  948. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  949. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  950. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  951. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  952. };
  953. pwr_i2c_scl_py3 {
  954. nvidia,pins = "pwr_i2c_scl_py3";
  955. nvidia,function = "i2cpmu";
  956. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  957. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  958. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  959. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  960. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  961. };
  962. pwr_i2c_sda_py4 {
  963. nvidia,pins = "pwr_i2c_sda_py4";
  964. nvidia,function = "i2cpmu";
  965. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  966. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  967. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  968. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  969. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  970. };
  971. clk_32k_out_py5 {
  972. nvidia,pins = "clk_32k_out_py5";
  973. nvidia,function = "soc";
  974. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  975. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  976. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  977. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  978. };
  979. pz0 {
  980. nvidia,pins = "pz0";
  981. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  982. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  983. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  984. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  985. };
  986. pz1 {
  987. nvidia,pins = "pz1";
  988. nvidia,function = "sdmmc1";
  989. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  990. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  991. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  992. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  993. };
  994. pz2 {
  995. nvidia,pins = "pz2";
  996. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  997. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  998. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  999. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1000. };
  1001. pz3 {
  1002. nvidia,pins = "pz3";
  1003. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1004. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1005. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1006. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1007. };
  1008. pz4 {
  1009. nvidia,pins = "pz4";
  1010. nvidia,function = "sdmmc1";
  1011. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1012. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1013. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1014. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1015. };
  1016. pz5 {
  1017. nvidia,pins = "pz5";
  1018. nvidia,function = "soc";
  1019. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1020. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1021. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1022. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1023. };
  1024. dap2_fs_paa0 {
  1025. nvidia,pins = "dap2_fs_paa0";
  1026. nvidia,function = "i2s2";
  1027. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1028. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1029. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1030. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1031. };
  1032. dap2_sclk_paa1 {
  1033. nvidia,pins = "dap2_sclk_paa1";
  1034. nvidia,function = "i2s2";
  1035. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1036. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1037. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1038. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1039. };
  1040. dap2_din_paa2 {
  1041. nvidia,pins = "dap2_din_paa2";
  1042. nvidia,function = "i2s2";
  1043. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1044. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1045. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1046. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1047. };
  1048. dap2_dout_paa3 {
  1049. nvidia,pins = "dap2_dout_paa3";
  1050. nvidia,function = "i2s2";
  1051. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1052. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1053. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1054. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1055. };
  1056. aud_mclk_pbb0 {
  1057. nvidia,pins = "aud_mclk_pbb0";
  1058. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1059. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1060. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1061. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1062. };
  1063. dvfs_pwm_pbb1 {
  1064. nvidia,pins = "dvfs_pwm_pbb1";
  1065. nvidia,function = "cldvfs";
  1066. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1067. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1068. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1069. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1070. };
  1071. dvfs_clk_pbb2 {
  1072. nvidia,pins = "dvfs_clk_pbb2";
  1073. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1074. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1075. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1076. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1077. };
  1078. gpio_x1_aud_pbb3 {
  1079. nvidia,pins = "gpio_x1_aud_pbb3";
  1080. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1081. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1082. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1083. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1084. };
  1085. gpio_x3_aud_pbb4 {
  1086. nvidia,pins = "gpio_x3_aud_pbb4";
  1087. nvidia,function = "rsvd0";
  1088. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1089. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1090. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1091. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1092. };
  1093. hdmi_cec_pcc0 {
  1094. nvidia,pins = "hdmi_cec_pcc0";
  1095. nvidia,function = "cec";
  1096. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1097. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1098. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1099. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1100. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  1101. };
  1102. hdmi_int_dp_hpd_pcc1 {
  1103. nvidia,pins = "hdmi_int_dp_hpd_pcc1";
  1104. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1105. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1106. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1107. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1108. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  1109. };
  1110. spdif_out_pcc2 {
  1111. nvidia,pins = "spdif_out_pcc2";
  1112. nvidia,function = "rsvd1";
  1113. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1114. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1115. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1116. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1117. };
  1118. spdif_in_pcc3 {
  1119. nvidia,pins = "spdif_in_pcc3";
  1120. nvidia,function = "rsvd1";
  1121. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1122. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1123. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1124. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1125. };
  1126. usb_vbus_en0_pcc4 {
  1127. nvidia,pins = "usb_vbus_en0_pcc4";
  1128. nvidia,function = "usb";
  1129. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1130. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1131. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1132. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1133. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  1134. };
  1135. usb_vbus_en1_pcc5 {
  1136. nvidia,pins = "usb_vbus_en1_pcc5";
  1137. nvidia,function = "usb";
  1138. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1139. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1140. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1141. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1142. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  1143. };
  1144. dp_hpd0_pcc6 {
  1145. nvidia,pins = "dp_hpd0_pcc6";
  1146. nvidia,function = "dp";
  1147. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1148. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1149. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1150. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1151. };
  1152. pcc7 {
  1153. nvidia,pins = "pcc7";
  1154. nvidia,function = "rsvd0";
  1155. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1156. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1157. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1158. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1159. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  1160. };
  1161. spi2_cs1_pdd0 {
  1162. nvidia,pins = "spi2_cs1_pdd0";
  1163. nvidia,function = "spi2";
  1164. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1165. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1166. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1167. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1168. };
  1169. qspi_sck_pee0 {
  1170. nvidia,pins = "qspi_sck_pee0";
  1171. nvidia,function = "rsvd1";
  1172. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1173. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1174. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1175. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1176. };
  1177. qspi_cs_n_pee1 {
  1178. nvidia,pins = "qspi_cs_n_pee1";
  1179. nvidia,function = "rsvd1";
  1180. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1181. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1182. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1183. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1184. };
  1185. qspi_io0_pee2 {
  1186. nvidia,pins = "qspi_io0_pee2";
  1187. nvidia,function = "rsvd1";
  1188. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1189. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1190. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1191. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1192. };
  1193. qspi_io1_pee3 {
  1194. nvidia,pins = "qspi_io1_pee3";
  1195. nvidia,function = "rsvd1";
  1196. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1197. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1198. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1199. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1200. };
  1201. qspi_io2_pee4 {
  1202. nvidia,pins = "qspi_io2_pee4";
  1203. nvidia,function = "rsvd1";
  1204. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1205. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1206. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1207. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1208. };
  1209. qspi_io3_pee5 {
  1210. nvidia,pins = "qspi_io3_pee5";
  1211. nvidia,function = "rsvd1";
  1212. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1213. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1214. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1215. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1216. };
  1217. core_pwr_req {
  1218. nvidia,pins = "core_pwr_req";
  1219. nvidia,function = "core";
  1220. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1221. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1222. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1223. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1224. };
  1225. cpu_pwr_req {
  1226. nvidia,pins = "cpu_pwr_req";
  1227. nvidia,function = "cpu";
  1228. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1229. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1230. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1231. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1232. };
  1233. pwr_int_n {
  1234. nvidia,pins = "pwr_int_n";
  1235. nvidia,function = "pmi";
  1236. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1237. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1238. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1239. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1240. };
  1241. clk_32k_in {
  1242. nvidia,pins = "clk_32k_in";
  1243. nvidia,function = "clk";
  1244. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1245. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1246. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1247. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1248. };
  1249. jtag_rtck {
  1250. nvidia,pins = "jtag_rtck";
  1251. nvidia,function = "jtag";
  1252. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1253. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1254. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1255. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1256. };
  1257. clk_req {
  1258. nvidia,pins = "clk_req";
  1259. nvidia,function = "rsvd1";
  1260. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1261. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1262. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1263. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1264. };
  1265. shutdown {
  1266. nvidia,pins = "shutdown";
  1267. nvidia,function = "shutdown";
  1268. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1269. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1270. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1271. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1272. };
  1273. };
  1274. };
  1275. pwm@7000a000 {
  1276. status = "okay";
  1277. };
  1278. i2c@7000c400 {
  1279. status = "okay";
  1280. clock-frequency = <100000>;
  1281. exp1: gpio@74 {
  1282. compatible = "ti,tca9539";
  1283. reg = <0x74>;
  1284. #gpio-cells = <2>;
  1285. gpio-controller;
  1286. };
  1287. };
  1288. /* HDMI DDC */
  1289. hdmi_ddc: i2c@7000c700 {
  1290. status = "okay";
  1291. clock-frequency = <100000>;
  1292. };
  1293. usb@70090000 {
  1294. phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
  1295. <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>,
  1296. <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,
  1297. <&{/padctl@7009f000/pads/usb2/lanes/usb2-3}>,
  1298. <&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>,
  1299. <&{/padctl@7009f000/pads/pcie/lanes/pcie-5}>;
  1300. phy-names = "usb2-0", "usb2-1", "usb2-2", "usb2-3", "usb3-0",
  1301. "usb3-1";
  1302. dvddio-pex-supply = <&vdd_pex_1v05>;
  1303. hvddio-pex-supply = <&vdd_1v8>;
  1304. avdd-usb-supply = <&vdd_3v3_sys>;
  1305. /* XXX what are these? */
  1306. avdd-pll-utmip-supply = <&vdd_1v8>;
  1307. avdd-pll-uerefe-supply = <&vdd_pex_1v05>;
  1308. dvdd-usb-ss-pll-supply = <&vdd_pex_1v05>;
  1309. hvdd-usb-ss-pll-e-supply = <&vdd_1v8>;
  1310. status = "okay";
  1311. };
  1312. sata@70020000 {
  1313. status = "okay";
  1314. phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;
  1315. };
  1316. padctl@7009f000 {
  1317. status = "okay";
  1318. pads {
  1319. usb2 {
  1320. status = "okay";
  1321. lanes {
  1322. usb2-0 {
  1323. nvidia,function = "xusb";
  1324. status = "okay";
  1325. };
  1326. usb2-1 {
  1327. nvidia,function = "xusb";
  1328. status = "okay";
  1329. };
  1330. usb2-2 {
  1331. nvidia,function = "xusb";
  1332. status = "okay";
  1333. };
  1334. usb2-3 {
  1335. nvidia,function = "xusb";
  1336. status = "okay";
  1337. };
  1338. };
  1339. };
  1340. pcie {
  1341. status = "okay";
  1342. lanes {
  1343. pcie-0 {
  1344. nvidia,function = "pcie-x1";
  1345. status = "okay";
  1346. };
  1347. pcie-1 {
  1348. nvidia,function = "pcie-x4";
  1349. status = "okay";
  1350. };
  1351. pcie-2 {
  1352. nvidia,function = "pcie-x4";
  1353. status = "okay";
  1354. };
  1355. pcie-3 {
  1356. nvidia,function = "pcie-x4";
  1357. status = "okay";
  1358. };
  1359. pcie-4 {
  1360. nvidia,function = "pcie-x4";
  1361. status = "okay";
  1362. };
  1363. pcie-5 {
  1364. nvidia,function = "usb3-ss";
  1365. status = "okay";
  1366. };
  1367. pcie-6 {
  1368. nvidia,function = "usb3-ss";
  1369. status = "okay";
  1370. };
  1371. };
  1372. };
  1373. sata {
  1374. status = "okay";
  1375. lanes {
  1376. sata-0 {
  1377. nvidia,function = "sata";
  1378. status = "okay";
  1379. };
  1380. };
  1381. };
  1382. };
  1383. ports {
  1384. usb2-0 {
  1385. status = "okay";
  1386. mode = "otg";
  1387. };
  1388. usb2-1 {
  1389. status = "okay";
  1390. vbus-supply = <&vdd_5v0_rtl>;
  1391. mode = "host";
  1392. };
  1393. usb2-2 {
  1394. status = "okay";
  1395. vbus-supply = <&vdd_usb_vbus>;
  1396. mode = "host";
  1397. };
  1398. usb2-3 {
  1399. status = "okay";
  1400. mode = "host";
  1401. };
  1402. usb3-0 {
  1403. nvidia,usb2-companion = <1>;
  1404. status = "okay";
  1405. };
  1406. usb3-1 {
  1407. nvidia,usb2-companion = <2>;
  1408. status = "okay";
  1409. };
  1410. };
  1411. };
  1412. /* MMC/SD */
  1413. sdhci@700b0000 {
  1414. status = "okay";
  1415. bus-width = <4>;
  1416. no-1-8-v;
  1417. cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
  1418. vqmmc-supply = <&vddio_sdmmc>;
  1419. vmmc-supply = <&vdd_3v3_sd>;
  1420. };
  1421. regulators {
  1422. compatible = "simple-bus";
  1423. #address-cells = <1>;
  1424. #size-cells = <0>;
  1425. vdd_sys_mux: regulator@0 {
  1426. compatible = "regulator-fixed";
  1427. reg = <0>;
  1428. regulator-name = "VDD_SYS_MUX";
  1429. regulator-min-microvolt = <5000000>;
  1430. regulator-max-microvolt = <5000000>;
  1431. regulator-always-on;
  1432. regulator-boot-on;
  1433. };
  1434. vdd_5v0_sys: regulator@1 {
  1435. compatible = "regulator-fixed";
  1436. reg = <1>;
  1437. regulator-name = "VDD_5V0_SYS";
  1438. regulator-min-microvolt = <5000000>;
  1439. regulator-max-microvolt = <5000000>;
  1440. regulator-always-on;
  1441. regulator-boot-on;
  1442. gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
  1443. enable-active-high;
  1444. vin-supply = <&vdd_sys_mux>;
  1445. };
  1446. vdd_3v3_sys: regulator@2 {
  1447. compatible = "regulator-fixed";
  1448. reg = <2>;
  1449. regulator-name = "VDD_3V3_SYS";
  1450. regulator-min-microvolt = <3300000>;
  1451. regulator-max-microvolt = <3300000>;
  1452. regulator-always-on;
  1453. regulator-boot-on;
  1454. gpio = <&pmic 3 GPIO_ACTIVE_HIGH>;
  1455. enable-active-high;
  1456. vin-supply = <&vdd_sys_mux>;
  1457. regulator-enable-ramp-delay = <160>;
  1458. regulator-disable-ramp-delay = <10000>;
  1459. };
  1460. vdd_5v0_io: regulator@3 {
  1461. compatible = "regulator-fixed";
  1462. reg = <3>;
  1463. regulator-name = "VDD_5V0_IO_SYS";
  1464. regulator-min-microvolt = <5000000>;
  1465. regulator-max-microvolt = <5000000>;
  1466. regulator-always-on;
  1467. regulator-boot-on;
  1468. };
  1469. vdd_3v3_sd: regulator@4 {
  1470. compatible = "regulator-fixed";
  1471. reg = <4>;
  1472. regulator-name = "VDD_3V3_SD";
  1473. regulator-min-microvolt = <3300000>;
  1474. regulator-max-microvolt = <3300000>;
  1475. gpio = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
  1476. enable-active-high;
  1477. vin-supply = <&vdd_3v3_sys>;
  1478. regulator-enable-ramp-delay = <472>;
  1479. regulator-disable-ramp-delay = <4880>;
  1480. };
  1481. vdd_dsi_csi: regulator@5 {
  1482. compatible = "regulator-fixed";
  1483. reg = <5>;
  1484. regulator-name = "AVDD_DSI_CSI_1V2";
  1485. regulator-min-microvolt = <1200000>;
  1486. regulator-max-microvolt = <1200000>;
  1487. vin-supply = <&vdd_sys_1v2>;
  1488. };
  1489. vdd_3v3_dis: regulator@6 {
  1490. compatible = "regulator-fixed";
  1491. reg = <6>;
  1492. regulator-name = "VDD_DIS_3V3_LCD";
  1493. regulator-min-microvolt = <3300000>;
  1494. regulator-max-microvolt = <3300000>;
  1495. regulator-always-on;
  1496. gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
  1497. enable-active-high;
  1498. vin-supply = <&vdd_3v3_sys>;
  1499. };
  1500. vdd_1v8_dis: regulator@7 {
  1501. compatible = "regulator-fixed";
  1502. reg = <7>;
  1503. regulator-name = "VDD_LCD_1V8_DIS";
  1504. regulator-min-microvolt = <1800000>;
  1505. regulator-max-microvolt = <1800000>;
  1506. regulator-always-on;
  1507. gpio = <&exp1 14 GPIO_ACTIVE_HIGH>;
  1508. enable-active-high;
  1509. vin-supply = <&vdd_1v8>;
  1510. };
  1511. vdd_5v0_rtl: regulator@8 {
  1512. compatible = "regulator-fixed";
  1513. reg = <8>;
  1514. regulator-name = "RTL_5V";
  1515. regulator-min-microvolt = <5000000>;
  1516. regulator-max-microvolt = <5000000>;
  1517. gpio = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
  1518. enable-active-high;
  1519. vin-supply = <&vdd_5v0_sys>;
  1520. };
  1521. vdd_usb_vbus: regulator@9 {
  1522. compatible = "regulator-fixed";
  1523. reg = <9>;
  1524. regulator-name = "USB_VBUS_EN1";
  1525. regulator-min-microvolt = <5000000>;
  1526. regulator-max-microvolt = <5000000>;
  1527. gpio = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>;
  1528. enable-active-high;
  1529. vin-supply = <&vdd_5v0_sys>;
  1530. };
  1531. vdd_hdmi: regulator@10 {
  1532. compatible = "regulator-fixed";
  1533. reg = <10>;
  1534. regulator-name = "VDD_HDMI_5V0";
  1535. regulator-min-microvolt = <5000000>;
  1536. regulator-max-microvolt = <5000000>;
  1537. gpio = <&exp1 12 GPIO_ACTIVE_HIGH>;
  1538. enable-active-high;
  1539. vin-supply = <&vdd_5v0_sys>;
  1540. };
  1541. };
  1542. gpio-keys {
  1543. compatible = "gpio-keys";
  1544. label = "gpio-keys";
  1545. power {
  1546. label = "Power";
  1547. gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>;
  1548. linux,code = <KEY_POWER>;
  1549. wakeup-source;
  1550. };
  1551. volume_down {
  1552. label = "Volume Down";
  1553. gpios = <&gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_LOW>;
  1554. linux,code = <KEY_VOLUMEDOWN>;
  1555. };
  1556. volume_up {
  1557. label = "Volume Up";
  1558. gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
  1559. linux,code = <KEY_VOLUMEUP>;
  1560. };
  1561. };
  1562. };