pci-sysfs.c 43 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * (C) Copyright 2002-2004 Greg Kroah-Hartman <greg@kroah.com>
  4. * (C) Copyright 2002-2004 IBM Corp.
  5. * (C) Copyright 2003 Matthew Wilcox
  6. * (C) Copyright 2003 Hewlett-Packard
  7. * (C) Copyright 2004 Jon Smirl <jonsmirl@yahoo.com>
  8. * (C) Copyright 2004 Silicon Graphics, Inc. Jesse Barnes <jbarnes@sgi.com>
  9. *
  10. * File attributes for PCI devices
  11. *
  12. * Modeled after usb's driverfs.c
  13. */
  14. #include <linux/kernel.h>
  15. #include <linux/sched.h>
  16. #include <linux/pci.h>
  17. #include <linux/stat.h>
  18. #include <linux/export.h>
  19. #include <linux/topology.h>
  20. #include <linux/mm.h>
  21. #include <linux/fs.h>
  22. #include <linux/capability.h>
  23. #include <linux/security.h>
  24. #include <linux/slab.h>
  25. #include <linux/vgaarb.h>
  26. #include <linux/pm_runtime.h>
  27. #include <linux/of.h>
  28. #include "pci.h"
  29. static int sysfs_initialized; /* = 0 */
  30. /* show configuration fields */
  31. #define pci_config_attr(field, format_string) \
  32. static ssize_t \
  33. field##_show(struct device *dev, struct device_attribute *attr, char *buf) \
  34. { \
  35. struct pci_dev *pdev; \
  36. \
  37. pdev = to_pci_dev(dev); \
  38. return sprintf(buf, format_string, pdev->field); \
  39. } \
  40. static DEVICE_ATTR_RO(field)
  41. pci_config_attr(vendor, "0x%04x\n");
  42. pci_config_attr(device, "0x%04x\n");
  43. pci_config_attr(subsystem_vendor, "0x%04x\n");
  44. pci_config_attr(subsystem_device, "0x%04x\n");
  45. pci_config_attr(revision, "0x%02x\n");
  46. pci_config_attr(class, "0x%06x\n");
  47. pci_config_attr(irq, "%u\n");
  48. static ssize_t broken_parity_status_show(struct device *dev,
  49. struct device_attribute *attr,
  50. char *buf)
  51. {
  52. struct pci_dev *pdev = to_pci_dev(dev);
  53. return sprintf(buf, "%u\n", pdev->broken_parity_status);
  54. }
  55. static ssize_t broken_parity_status_store(struct device *dev,
  56. struct device_attribute *attr,
  57. const char *buf, size_t count)
  58. {
  59. struct pci_dev *pdev = to_pci_dev(dev);
  60. unsigned long val;
  61. if (kstrtoul(buf, 0, &val) < 0)
  62. return -EINVAL;
  63. pdev->broken_parity_status = !!val;
  64. return count;
  65. }
  66. static DEVICE_ATTR_RW(broken_parity_status);
  67. static ssize_t pci_dev_show_local_cpu(struct device *dev, bool list,
  68. struct device_attribute *attr, char *buf)
  69. {
  70. const struct cpumask *mask;
  71. #ifdef CONFIG_NUMA
  72. mask = (dev_to_node(dev) == -1) ? cpu_online_mask :
  73. cpumask_of_node(dev_to_node(dev));
  74. #else
  75. mask = cpumask_of_pcibus(to_pci_dev(dev)->bus);
  76. #endif
  77. return cpumap_print_to_pagebuf(list, buf, mask);
  78. }
  79. static ssize_t local_cpus_show(struct device *dev,
  80. struct device_attribute *attr, char *buf)
  81. {
  82. return pci_dev_show_local_cpu(dev, false, attr, buf);
  83. }
  84. static DEVICE_ATTR_RO(local_cpus);
  85. static ssize_t local_cpulist_show(struct device *dev,
  86. struct device_attribute *attr, char *buf)
  87. {
  88. return pci_dev_show_local_cpu(dev, true, attr, buf);
  89. }
  90. static DEVICE_ATTR_RO(local_cpulist);
  91. /*
  92. * PCI Bus Class Devices
  93. */
  94. static ssize_t cpuaffinity_show(struct device *dev,
  95. struct device_attribute *attr, char *buf)
  96. {
  97. const struct cpumask *cpumask = cpumask_of_pcibus(to_pci_bus(dev));
  98. return cpumap_print_to_pagebuf(false, buf, cpumask);
  99. }
  100. static DEVICE_ATTR_RO(cpuaffinity);
  101. static ssize_t cpulistaffinity_show(struct device *dev,
  102. struct device_attribute *attr, char *buf)
  103. {
  104. const struct cpumask *cpumask = cpumask_of_pcibus(to_pci_bus(dev));
  105. return cpumap_print_to_pagebuf(true, buf, cpumask);
  106. }
  107. static DEVICE_ATTR_RO(cpulistaffinity);
  108. /* show resources */
  109. static ssize_t resource_show(struct device *dev, struct device_attribute *attr,
  110. char *buf)
  111. {
  112. struct pci_dev *pci_dev = to_pci_dev(dev);
  113. char *str = buf;
  114. int i;
  115. int max;
  116. resource_size_t start, end;
  117. if (pci_dev->subordinate)
  118. max = DEVICE_COUNT_RESOURCE;
  119. else
  120. max = PCI_BRIDGE_RESOURCES;
  121. for (i = 0; i < max; i++) {
  122. struct resource *res = &pci_dev->resource[i];
  123. pci_resource_to_user(pci_dev, i, res, &start, &end);
  124. str += sprintf(str, "0x%016llx 0x%016llx 0x%016llx\n",
  125. (unsigned long long)start,
  126. (unsigned long long)end,
  127. (unsigned long long)res->flags);
  128. }
  129. return (str - buf);
  130. }
  131. static DEVICE_ATTR_RO(resource);
  132. static ssize_t max_link_speed_show(struct device *dev,
  133. struct device_attribute *attr, char *buf)
  134. {
  135. struct pci_dev *pdev = to_pci_dev(dev);
  136. return sprintf(buf, "%s\n", PCIE_SPEED2STR(pcie_get_speed_cap(pdev)));
  137. }
  138. static DEVICE_ATTR_RO(max_link_speed);
  139. static ssize_t max_link_width_show(struct device *dev,
  140. struct device_attribute *attr, char *buf)
  141. {
  142. struct pci_dev *pdev = to_pci_dev(dev);
  143. return sprintf(buf, "%u\n", pcie_get_width_cap(pdev));
  144. }
  145. static DEVICE_ATTR_RO(max_link_width);
  146. static ssize_t current_link_speed_show(struct device *dev,
  147. struct device_attribute *attr, char *buf)
  148. {
  149. struct pci_dev *pci_dev = to_pci_dev(dev);
  150. u16 linkstat;
  151. int err;
  152. const char *speed;
  153. err = pcie_capability_read_word(pci_dev, PCI_EXP_LNKSTA, &linkstat);
  154. if (err)
  155. return -EINVAL;
  156. switch (linkstat & PCI_EXP_LNKSTA_CLS) {
  157. case PCI_EXP_LNKSTA_CLS_16_0GB:
  158. speed = "16 GT/s";
  159. break;
  160. case PCI_EXP_LNKSTA_CLS_8_0GB:
  161. speed = "8 GT/s";
  162. break;
  163. case PCI_EXP_LNKSTA_CLS_5_0GB:
  164. speed = "5 GT/s";
  165. break;
  166. case PCI_EXP_LNKSTA_CLS_2_5GB:
  167. speed = "2.5 GT/s";
  168. break;
  169. default:
  170. speed = "Unknown speed";
  171. }
  172. return sprintf(buf, "%s\n", speed);
  173. }
  174. static DEVICE_ATTR_RO(current_link_speed);
  175. static ssize_t current_link_width_show(struct device *dev,
  176. struct device_attribute *attr, char *buf)
  177. {
  178. struct pci_dev *pci_dev = to_pci_dev(dev);
  179. u16 linkstat;
  180. int err;
  181. err = pcie_capability_read_word(pci_dev, PCI_EXP_LNKSTA, &linkstat);
  182. if (err)
  183. return -EINVAL;
  184. return sprintf(buf, "%u\n",
  185. (linkstat & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT);
  186. }
  187. static DEVICE_ATTR_RO(current_link_width);
  188. static ssize_t secondary_bus_number_show(struct device *dev,
  189. struct device_attribute *attr,
  190. char *buf)
  191. {
  192. struct pci_dev *pci_dev = to_pci_dev(dev);
  193. u8 sec_bus;
  194. int err;
  195. err = pci_read_config_byte(pci_dev, PCI_SECONDARY_BUS, &sec_bus);
  196. if (err)
  197. return -EINVAL;
  198. return sprintf(buf, "%u\n", sec_bus);
  199. }
  200. static DEVICE_ATTR_RO(secondary_bus_number);
  201. static ssize_t subordinate_bus_number_show(struct device *dev,
  202. struct device_attribute *attr,
  203. char *buf)
  204. {
  205. struct pci_dev *pci_dev = to_pci_dev(dev);
  206. u8 sub_bus;
  207. int err;
  208. err = pci_read_config_byte(pci_dev, PCI_SUBORDINATE_BUS, &sub_bus);
  209. if (err)
  210. return -EINVAL;
  211. return sprintf(buf, "%u\n", sub_bus);
  212. }
  213. static DEVICE_ATTR_RO(subordinate_bus_number);
  214. static ssize_t ari_enabled_show(struct device *dev,
  215. struct device_attribute *attr,
  216. char *buf)
  217. {
  218. struct pci_dev *pci_dev = to_pci_dev(dev);
  219. return sprintf(buf, "%u\n", pci_ari_enabled(pci_dev->bus));
  220. }
  221. static DEVICE_ATTR_RO(ari_enabled);
  222. static ssize_t modalias_show(struct device *dev, struct device_attribute *attr,
  223. char *buf)
  224. {
  225. struct pci_dev *pci_dev = to_pci_dev(dev);
  226. return sprintf(buf, "pci:v%08Xd%08Xsv%08Xsd%08Xbc%02Xsc%02Xi%02X\n",
  227. pci_dev->vendor, pci_dev->device,
  228. pci_dev->subsystem_vendor, pci_dev->subsystem_device,
  229. (u8)(pci_dev->class >> 16), (u8)(pci_dev->class >> 8),
  230. (u8)(pci_dev->class));
  231. }
  232. static DEVICE_ATTR_RO(modalias);
  233. static ssize_t enable_store(struct device *dev, struct device_attribute *attr,
  234. const char *buf, size_t count)
  235. {
  236. struct pci_dev *pdev = to_pci_dev(dev);
  237. unsigned long val;
  238. ssize_t result = kstrtoul(buf, 0, &val);
  239. if (result < 0)
  240. return result;
  241. /* this can crash the machine when done on the "wrong" device */
  242. if (!capable(CAP_SYS_ADMIN))
  243. return -EPERM;
  244. device_lock(dev);
  245. if (dev->driver)
  246. result = -EBUSY;
  247. else if (val)
  248. result = pci_enable_device(pdev);
  249. else if (pci_is_enabled(pdev))
  250. pci_disable_device(pdev);
  251. else
  252. result = -EIO;
  253. device_unlock(dev);
  254. return result < 0 ? result : count;
  255. }
  256. static ssize_t enable_show(struct device *dev, struct device_attribute *attr,
  257. char *buf)
  258. {
  259. struct pci_dev *pdev;
  260. pdev = to_pci_dev(dev);
  261. return sprintf(buf, "%u\n", atomic_read(&pdev->enable_cnt));
  262. }
  263. static DEVICE_ATTR_RW(enable);
  264. #ifdef CONFIG_NUMA
  265. static ssize_t numa_node_store(struct device *dev,
  266. struct device_attribute *attr, const char *buf,
  267. size_t count)
  268. {
  269. struct pci_dev *pdev = to_pci_dev(dev);
  270. int node, ret;
  271. if (!capable(CAP_SYS_ADMIN))
  272. return -EPERM;
  273. ret = kstrtoint(buf, 0, &node);
  274. if (ret)
  275. return ret;
  276. if ((node < 0 && node != NUMA_NO_NODE) || node >= MAX_NUMNODES)
  277. return -EINVAL;
  278. if (node != NUMA_NO_NODE && !node_online(node))
  279. return -EINVAL;
  280. add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
  281. pci_alert(pdev, FW_BUG "Overriding NUMA node to %d. Contact your vendor for updates.",
  282. node);
  283. dev->numa_node = node;
  284. return count;
  285. }
  286. static ssize_t numa_node_show(struct device *dev, struct device_attribute *attr,
  287. char *buf)
  288. {
  289. return sprintf(buf, "%d\n", dev->numa_node);
  290. }
  291. static DEVICE_ATTR_RW(numa_node);
  292. #endif
  293. static ssize_t dma_mask_bits_show(struct device *dev,
  294. struct device_attribute *attr, char *buf)
  295. {
  296. struct pci_dev *pdev = to_pci_dev(dev);
  297. return sprintf(buf, "%d\n", fls64(pdev->dma_mask));
  298. }
  299. static DEVICE_ATTR_RO(dma_mask_bits);
  300. static ssize_t consistent_dma_mask_bits_show(struct device *dev,
  301. struct device_attribute *attr,
  302. char *buf)
  303. {
  304. return sprintf(buf, "%d\n", fls64(dev->coherent_dma_mask));
  305. }
  306. static DEVICE_ATTR_RO(consistent_dma_mask_bits);
  307. static ssize_t msi_bus_show(struct device *dev, struct device_attribute *attr,
  308. char *buf)
  309. {
  310. struct pci_dev *pdev = to_pci_dev(dev);
  311. struct pci_bus *subordinate = pdev->subordinate;
  312. return sprintf(buf, "%u\n", subordinate ?
  313. !(subordinate->bus_flags & PCI_BUS_FLAGS_NO_MSI)
  314. : !pdev->no_msi);
  315. }
  316. static ssize_t msi_bus_store(struct device *dev, struct device_attribute *attr,
  317. const char *buf, size_t count)
  318. {
  319. struct pci_dev *pdev = to_pci_dev(dev);
  320. struct pci_bus *subordinate = pdev->subordinate;
  321. unsigned long val;
  322. if (kstrtoul(buf, 0, &val) < 0)
  323. return -EINVAL;
  324. if (!capable(CAP_SYS_ADMIN))
  325. return -EPERM;
  326. /*
  327. * "no_msi" and "bus_flags" only affect what happens when a driver
  328. * requests MSI or MSI-X. They don't affect any drivers that have
  329. * already requested MSI or MSI-X.
  330. */
  331. if (!subordinate) {
  332. pdev->no_msi = !val;
  333. pci_info(pdev, "MSI/MSI-X %s for future drivers\n",
  334. val ? "allowed" : "disallowed");
  335. return count;
  336. }
  337. if (val)
  338. subordinate->bus_flags &= ~PCI_BUS_FLAGS_NO_MSI;
  339. else
  340. subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
  341. dev_info(&subordinate->dev, "MSI/MSI-X %s for future drivers of devices on this bus\n",
  342. val ? "allowed" : "disallowed");
  343. return count;
  344. }
  345. static DEVICE_ATTR_RW(msi_bus);
  346. static ssize_t bus_rescan_store(struct bus_type *bus, const char *buf,
  347. size_t count)
  348. {
  349. unsigned long val;
  350. struct pci_bus *b = NULL;
  351. if (kstrtoul(buf, 0, &val) < 0)
  352. return -EINVAL;
  353. if (val) {
  354. pci_lock_rescan_remove();
  355. while ((b = pci_find_next_bus(b)) != NULL)
  356. pci_rescan_bus(b);
  357. pci_unlock_rescan_remove();
  358. }
  359. return count;
  360. }
  361. static BUS_ATTR(rescan, (S_IWUSR|S_IWGRP), NULL, bus_rescan_store);
  362. static struct attribute *pci_bus_attrs[] = {
  363. &bus_attr_rescan.attr,
  364. NULL,
  365. };
  366. static const struct attribute_group pci_bus_group = {
  367. .attrs = pci_bus_attrs,
  368. };
  369. const struct attribute_group *pci_bus_groups[] = {
  370. &pci_bus_group,
  371. NULL,
  372. };
  373. static ssize_t dev_rescan_store(struct device *dev,
  374. struct device_attribute *attr, const char *buf,
  375. size_t count)
  376. {
  377. unsigned long val;
  378. struct pci_dev *pdev = to_pci_dev(dev);
  379. if (kstrtoul(buf, 0, &val) < 0)
  380. return -EINVAL;
  381. if (val) {
  382. pci_lock_rescan_remove();
  383. pci_rescan_bus(pdev->bus);
  384. pci_unlock_rescan_remove();
  385. }
  386. return count;
  387. }
  388. static struct device_attribute dev_rescan_attr = __ATTR(rescan,
  389. (S_IWUSR|S_IWGRP),
  390. NULL, dev_rescan_store);
  391. static ssize_t remove_store(struct device *dev, struct device_attribute *attr,
  392. const char *buf, size_t count)
  393. {
  394. unsigned long val;
  395. if (kstrtoul(buf, 0, &val) < 0)
  396. return -EINVAL;
  397. if (val && device_remove_file_self(dev, attr))
  398. pci_stop_and_remove_bus_device_locked(to_pci_dev(dev));
  399. return count;
  400. }
  401. static struct device_attribute dev_remove_attr = __ATTR_IGNORE_LOCKDEP(remove,
  402. (S_IWUSR|S_IWGRP),
  403. NULL, remove_store);
  404. static ssize_t dev_bus_rescan_store(struct device *dev,
  405. struct device_attribute *attr,
  406. const char *buf, size_t count)
  407. {
  408. unsigned long val;
  409. struct pci_bus *bus = to_pci_bus(dev);
  410. if (kstrtoul(buf, 0, &val) < 0)
  411. return -EINVAL;
  412. if (val) {
  413. pci_lock_rescan_remove();
  414. if (!pci_is_root_bus(bus) && list_empty(&bus->devices))
  415. pci_rescan_bus_bridge_resize(bus->self);
  416. else
  417. pci_rescan_bus(bus);
  418. pci_unlock_rescan_remove();
  419. }
  420. return count;
  421. }
  422. static DEVICE_ATTR(rescan, (S_IWUSR|S_IWGRP), NULL, dev_bus_rescan_store);
  423. #if defined(CONFIG_PM) && defined(CONFIG_ACPI)
  424. static ssize_t d3cold_allowed_store(struct device *dev,
  425. struct device_attribute *attr,
  426. const char *buf, size_t count)
  427. {
  428. struct pci_dev *pdev = to_pci_dev(dev);
  429. unsigned long val;
  430. if (kstrtoul(buf, 0, &val) < 0)
  431. return -EINVAL;
  432. pdev->d3cold_allowed = !!val;
  433. if (pdev->d3cold_allowed)
  434. pci_d3cold_enable(pdev);
  435. else
  436. pci_d3cold_disable(pdev);
  437. pm_runtime_resume(dev);
  438. return count;
  439. }
  440. static ssize_t d3cold_allowed_show(struct device *dev,
  441. struct device_attribute *attr, char *buf)
  442. {
  443. struct pci_dev *pdev = to_pci_dev(dev);
  444. return sprintf(buf, "%u\n", pdev->d3cold_allowed);
  445. }
  446. static DEVICE_ATTR_RW(d3cold_allowed);
  447. #endif
  448. #ifdef CONFIG_OF
  449. static ssize_t devspec_show(struct device *dev,
  450. struct device_attribute *attr, char *buf)
  451. {
  452. struct pci_dev *pdev = to_pci_dev(dev);
  453. struct device_node *np = pci_device_to_OF_node(pdev);
  454. if (np == NULL)
  455. return 0;
  456. return sprintf(buf, "%pOF", np);
  457. }
  458. static DEVICE_ATTR_RO(devspec);
  459. #endif
  460. #ifdef CONFIG_PCI_IOV
  461. static ssize_t sriov_totalvfs_show(struct device *dev,
  462. struct device_attribute *attr,
  463. char *buf)
  464. {
  465. struct pci_dev *pdev = to_pci_dev(dev);
  466. return sprintf(buf, "%u\n", pci_sriov_get_totalvfs(pdev));
  467. }
  468. static ssize_t sriov_numvfs_show(struct device *dev,
  469. struct device_attribute *attr,
  470. char *buf)
  471. {
  472. struct pci_dev *pdev = to_pci_dev(dev);
  473. return sprintf(buf, "%u\n", pdev->sriov->num_VFs);
  474. }
  475. /*
  476. * num_vfs > 0; number of VFs to enable
  477. * num_vfs = 0; disable all VFs
  478. *
  479. * Note: SRIOV spec doesn't allow partial VF
  480. * disable, so it's all or none.
  481. */
  482. static ssize_t sriov_numvfs_store(struct device *dev,
  483. struct device_attribute *attr,
  484. const char *buf, size_t count)
  485. {
  486. struct pci_dev *pdev = to_pci_dev(dev);
  487. int ret;
  488. u16 num_vfs;
  489. ret = kstrtou16(buf, 0, &num_vfs);
  490. if (ret < 0)
  491. return ret;
  492. if (num_vfs > pci_sriov_get_totalvfs(pdev))
  493. return -ERANGE;
  494. device_lock(&pdev->dev);
  495. if (num_vfs == pdev->sriov->num_VFs)
  496. goto exit;
  497. /* is PF driver loaded w/callback */
  498. if (!pdev->driver || !pdev->driver->sriov_configure) {
  499. pci_info(pdev, "Driver doesn't support SRIOV configuration via sysfs\n");
  500. ret = -ENOENT;
  501. goto exit;
  502. }
  503. if (num_vfs == 0) {
  504. /* disable VFs */
  505. ret = pdev->driver->sriov_configure(pdev, 0);
  506. goto exit;
  507. }
  508. /* enable VFs */
  509. if (pdev->sriov->num_VFs) {
  510. pci_warn(pdev, "%d VFs already enabled. Disable before enabling %d VFs\n",
  511. pdev->sriov->num_VFs, num_vfs);
  512. ret = -EBUSY;
  513. goto exit;
  514. }
  515. ret = pdev->driver->sriov_configure(pdev, num_vfs);
  516. if (ret < 0)
  517. goto exit;
  518. if (ret != num_vfs)
  519. pci_warn(pdev, "%d VFs requested; only %d enabled\n",
  520. num_vfs, ret);
  521. exit:
  522. device_unlock(&pdev->dev);
  523. if (ret < 0)
  524. return ret;
  525. return count;
  526. }
  527. static ssize_t sriov_offset_show(struct device *dev,
  528. struct device_attribute *attr,
  529. char *buf)
  530. {
  531. struct pci_dev *pdev = to_pci_dev(dev);
  532. return sprintf(buf, "%u\n", pdev->sriov->offset);
  533. }
  534. static ssize_t sriov_stride_show(struct device *dev,
  535. struct device_attribute *attr,
  536. char *buf)
  537. {
  538. struct pci_dev *pdev = to_pci_dev(dev);
  539. return sprintf(buf, "%u\n", pdev->sriov->stride);
  540. }
  541. static ssize_t sriov_vf_device_show(struct device *dev,
  542. struct device_attribute *attr,
  543. char *buf)
  544. {
  545. struct pci_dev *pdev = to_pci_dev(dev);
  546. return sprintf(buf, "%x\n", pdev->sriov->vf_device);
  547. }
  548. static ssize_t sriov_drivers_autoprobe_show(struct device *dev,
  549. struct device_attribute *attr,
  550. char *buf)
  551. {
  552. struct pci_dev *pdev = to_pci_dev(dev);
  553. return sprintf(buf, "%u\n", pdev->sriov->drivers_autoprobe);
  554. }
  555. static ssize_t sriov_drivers_autoprobe_store(struct device *dev,
  556. struct device_attribute *attr,
  557. const char *buf, size_t count)
  558. {
  559. struct pci_dev *pdev = to_pci_dev(dev);
  560. bool drivers_autoprobe;
  561. if (kstrtobool(buf, &drivers_autoprobe) < 0)
  562. return -EINVAL;
  563. pdev->sriov->drivers_autoprobe = drivers_autoprobe;
  564. return count;
  565. }
  566. static struct device_attribute sriov_totalvfs_attr = __ATTR_RO(sriov_totalvfs);
  567. static struct device_attribute sriov_numvfs_attr =
  568. __ATTR(sriov_numvfs, (S_IRUGO|S_IWUSR|S_IWGRP),
  569. sriov_numvfs_show, sriov_numvfs_store);
  570. static struct device_attribute sriov_offset_attr = __ATTR_RO(sriov_offset);
  571. static struct device_attribute sriov_stride_attr = __ATTR_RO(sriov_stride);
  572. static struct device_attribute sriov_vf_device_attr = __ATTR_RO(sriov_vf_device);
  573. static struct device_attribute sriov_drivers_autoprobe_attr =
  574. __ATTR(sriov_drivers_autoprobe, (S_IRUGO|S_IWUSR|S_IWGRP),
  575. sriov_drivers_autoprobe_show, sriov_drivers_autoprobe_store);
  576. #endif /* CONFIG_PCI_IOV */
  577. static ssize_t driver_override_store(struct device *dev,
  578. struct device_attribute *attr,
  579. const char *buf, size_t count)
  580. {
  581. struct pci_dev *pdev = to_pci_dev(dev);
  582. char *driver_override, *old, *cp;
  583. /* We need to keep extra room for a newline */
  584. if (count >= (PAGE_SIZE - 1))
  585. return -EINVAL;
  586. driver_override = kstrndup(buf, count, GFP_KERNEL);
  587. if (!driver_override)
  588. return -ENOMEM;
  589. cp = strchr(driver_override, '\n');
  590. if (cp)
  591. *cp = '\0';
  592. device_lock(dev);
  593. old = pdev->driver_override;
  594. if (strlen(driver_override)) {
  595. pdev->driver_override = driver_override;
  596. } else {
  597. kfree(driver_override);
  598. pdev->driver_override = NULL;
  599. }
  600. device_unlock(dev);
  601. kfree(old);
  602. return count;
  603. }
  604. static ssize_t driver_override_show(struct device *dev,
  605. struct device_attribute *attr, char *buf)
  606. {
  607. struct pci_dev *pdev = to_pci_dev(dev);
  608. ssize_t len;
  609. device_lock(dev);
  610. len = snprintf(buf, PAGE_SIZE, "%s\n", pdev->driver_override);
  611. device_unlock(dev);
  612. return len;
  613. }
  614. static DEVICE_ATTR_RW(driver_override);
  615. static struct attribute *pci_dev_attrs[] = {
  616. &dev_attr_resource.attr,
  617. &dev_attr_vendor.attr,
  618. &dev_attr_device.attr,
  619. &dev_attr_subsystem_vendor.attr,
  620. &dev_attr_subsystem_device.attr,
  621. &dev_attr_revision.attr,
  622. &dev_attr_class.attr,
  623. &dev_attr_irq.attr,
  624. &dev_attr_local_cpus.attr,
  625. &dev_attr_local_cpulist.attr,
  626. &dev_attr_modalias.attr,
  627. #ifdef CONFIG_NUMA
  628. &dev_attr_numa_node.attr,
  629. #endif
  630. &dev_attr_dma_mask_bits.attr,
  631. &dev_attr_consistent_dma_mask_bits.attr,
  632. &dev_attr_enable.attr,
  633. &dev_attr_broken_parity_status.attr,
  634. &dev_attr_msi_bus.attr,
  635. #if defined(CONFIG_PM) && defined(CONFIG_ACPI)
  636. &dev_attr_d3cold_allowed.attr,
  637. #endif
  638. #ifdef CONFIG_OF
  639. &dev_attr_devspec.attr,
  640. #endif
  641. &dev_attr_driver_override.attr,
  642. &dev_attr_ari_enabled.attr,
  643. NULL,
  644. };
  645. static struct attribute *pci_bridge_attrs[] = {
  646. &dev_attr_subordinate_bus_number.attr,
  647. &dev_attr_secondary_bus_number.attr,
  648. NULL,
  649. };
  650. static struct attribute *pcie_dev_attrs[] = {
  651. &dev_attr_current_link_speed.attr,
  652. &dev_attr_current_link_width.attr,
  653. &dev_attr_max_link_width.attr,
  654. &dev_attr_max_link_speed.attr,
  655. NULL,
  656. };
  657. static struct attribute *pcibus_attrs[] = {
  658. &dev_attr_rescan.attr,
  659. &dev_attr_cpuaffinity.attr,
  660. &dev_attr_cpulistaffinity.attr,
  661. NULL,
  662. };
  663. static const struct attribute_group pcibus_group = {
  664. .attrs = pcibus_attrs,
  665. };
  666. const struct attribute_group *pcibus_groups[] = {
  667. &pcibus_group,
  668. NULL,
  669. };
  670. static ssize_t boot_vga_show(struct device *dev, struct device_attribute *attr,
  671. char *buf)
  672. {
  673. struct pci_dev *pdev = to_pci_dev(dev);
  674. struct pci_dev *vga_dev = vga_default_device();
  675. if (vga_dev)
  676. return sprintf(buf, "%u\n", (pdev == vga_dev));
  677. return sprintf(buf, "%u\n",
  678. !!(pdev->resource[PCI_ROM_RESOURCE].flags &
  679. IORESOURCE_ROM_SHADOW));
  680. }
  681. static struct device_attribute vga_attr = __ATTR_RO(boot_vga);
  682. static ssize_t pci_read_config(struct file *filp, struct kobject *kobj,
  683. struct bin_attribute *bin_attr, char *buf,
  684. loff_t off, size_t count)
  685. {
  686. struct pci_dev *dev = to_pci_dev(kobj_to_dev(kobj));
  687. unsigned int size = 64;
  688. loff_t init_off = off;
  689. u8 *data = (u8 *) buf;
  690. /* Several chips lock up trying to read undefined config space */
  691. if (file_ns_capable(filp, &init_user_ns, CAP_SYS_ADMIN))
  692. size = dev->cfg_size;
  693. else if (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
  694. size = 128;
  695. if (off > size)
  696. return 0;
  697. if (off + count > size) {
  698. size -= off;
  699. count = size;
  700. } else {
  701. size = count;
  702. }
  703. pci_config_pm_runtime_get(dev);
  704. if ((off & 1) && size) {
  705. u8 val;
  706. pci_user_read_config_byte(dev, off, &val);
  707. data[off - init_off] = val;
  708. off++;
  709. size--;
  710. }
  711. if ((off & 3) && size > 2) {
  712. u16 val;
  713. pci_user_read_config_word(dev, off, &val);
  714. data[off - init_off] = val & 0xff;
  715. data[off - init_off + 1] = (val >> 8) & 0xff;
  716. off += 2;
  717. size -= 2;
  718. }
  719. while (size > 3) {
  720. u32 val;
  721. pci_user_read_config_dword(dev, off, &val);
  722. data[off - init_off] = val & 0xff;
  723. data[off - init_off + 1] = (val >> 8) & 0xff;
  724. data[off - init_off + 2] = (val >> 16) & 0xff;
  725. data[off - init_off + 3] = (val >> 24) & 0xff;
  726. off += 4;
  727. size -= 4;
  728. }
  729. if (size >= 2) {
  730. u16 val;
  731. pci_user_read_config_word(dev, off, &val);
  732. data[off - init_off] = val & 0xff;
  733. data[off - init_off + 1] = (val >> 8) & 0xff;
  734. off += 2;
  735. size -= 2;
  736. }
  737. if (size > 0) {
  738. u8 val;
  739. pci_user_read_config_byte(dev, off, &val);
  740. data[off - init_off] = val;
  741. off++;
  742. --size;
  743. }
  744. pci_config_pm_runtime_put(dev);
  745. return count;
  746. }
  747. static ssize_t pci_write_config(struct file *filp, struct kobject *kobj,
  748. struct bin_attribute *bin_attr, char *buf,
  749. loff_t off, size_t count)
  750. {
  751. struct pci_dev *dev = to_pci_dev(kobj_to_dev(kobj));
  752. unsigned int size = count;
  753. loff_t init_off = off;
  754. u8 *data = (u8 *) buf;
  755. if (off > dev->cfg_size)
  756. return 0;
  757. if (off + count > dev->cfg_size) {
  758. size = dev->cfg_size - off;
  759. count = size;
  760. }
  761. pci_config_pm_runtime_get(dev);
  762. if ((off & 1) && size) {
  763. pci_user_write_config_byte(dev, off, data[off - init_off]);
  764. off++;
  765. size--;
  766. }
  767. if ((off & 3) && size > 2) {
  768. u16 val = data[off - init_off];
  769. val |= (u16) data[off - init_off + 1] << 8;
  770. pci_user_write_config_word(dev, off, val);
  771. off += 2;
  772. size -= 2;
  773. }
  774. while (size > 3) {
  775. u32 val = data[off - init_off];
  776. val |= (u32) data[off - init_off + 1] << 8;
  777. val |= (u32) data[off - init_off + 2] << 16;
  778. val |= (u32) data[off - init_off + 3] << 24;
  779. pci_user_write_config_dword(dev, off, val);
  780. off += 4;
  781. size -= 4;
  782. }
  783. if (size >= 2) {
  784. u16 val = data[off - init_off];
  785. val |= (u16) data[off - init_off + 1] << 8;
  786. pci_user_write_config_word(dev, off, val);
  787. off += 2;
  788. size -= 2;
  789. }
  790. if (size) {
  791. pci_user_write_config_byte(dev, off, data[off - init_off]);
  792. off++;
  793. --size;
  794. }
  795. pci_config_pm_runtime_put(dev);
  796. return count;
  797. }
  798. #ifdef HAVE_PCI_LEGACY
  799. /**
  800. * pci_read_legacy_io - read byte(s) from legacy I/O port space
  801. * @filp: open sysfs file
  802. * @kobj: kobject corresponding to file to read from
  803. * @bin_attr: struct bin_attribute for this file
  804. * @buf: buffer to store results
  805. * @off: offset into legacy I/O port space
  806. * @count: number of bytes to read
  807. *
  808. * Reads 1, 2, or 4 bytes from legacy I/O port space using an arch specific
  809. * callback routine (pci_legacy_read).
  810. */
  811. static ssize_t pci_read_legacy_io(struct file *filp, struct kobject *kobj,
  812. struct bin_attribute *bin_attr, char *buf,
  813. loff_t off, size_t count)
  814. {
  815. struct pci_bus *bus = to_pci_bus(kobj_to_dev(kobj));
  816. /* Only support 1, 2 or 4 byte accesses */
  817. if (count != 1 && count != 2 && count != 4)
  818. return -EINVAL;
  819. return pci_legacy_read(bus, off, (u32 *)buf, count);
  820. }
  821. /**
  822. * pci_write_legacy_io - write byte(s) to legacy I/O port space
  823. * @filp: open sysfs file
  824. * @kobj: kobject corresponding to file to read from
  825. * @bin_attr: struct bin_attribute for this file
  826. * @buf: buffer containing value to be written
  827. * @off: offset into legacy I/O port space
  828. * @count: number of bytes to write
  829. *
  830. * Writes 1, 2, or 4 bytes from legacy I/O port space using an arch specific
  831. * callback routine (pci_legacy_write).
  832. */
  833. static ssize_t pci_write_legacy_io(struct file *filp, struct kobject *kobj,
  834. struct bin_attribute *bin_attr, char *buf,
  835. loff_t off, size_t count)
  836. {
  837. struct pci_bus *bus = to_pci_bus(kobj_to_dev(kobj));
  838. /* Only support 1, 2 or 4 byte accesses */
  839. if (count != 1 && count != 2 && count != 4)
  840. return -EINVAL;
  841. return pci_legacy_write(bus, off, *(u32 *)buf, count);
  842. }
  843. /**
  844. * pci_mmap_legacy_mem - map legacy PCI memory into user memory space
  845. * @filp: open sysfs file
  846. * @kobj: kobject corresponding to device to be mapped
  847. * @attr: struct bin_attribute for this file
  848. * @vma: struct vm_area_struct passed to mmap
  849. *
  850. * Uses an arch specific callback, pci_mmap_legacy_mem_page_range, to mmap
  851. * legacy memory space (first meg of bus space) into application virtual
  852. * memory space.
  853. */
  854. static int pci_mmap_legacy_mem(struct file *filp, struct kobject *kobj,
  855. struct bin_attribute *attr,
  856. struct vm_area_struct *vma)
  857. {
  858. struct pci_bus *bus = to_pci_bus(kobj_to_dev(kobj));
  859. return pci_mmap_legacy_page_range(bus, vma, pci_mmap_mem);
  860. }
  861. /**
  862. * pci_mmap_legacy_io - map legacy PCI IO into user memory space
  863. * @filp: open sysfs file
  864. * @kobj: kobject corresponding to device to be mapped
  865. * @attr: struct bin_attribute for this file
  866. * @vma: struct vm_area_struct passed to mmap
  867. *
  868. * Uses an arch specific callback, pci_mmap_legacy_io_page_range, to mmap
  869. * legacy IO space (first meg of bus space) into application virtual
  870. * memory space. Returns -ENOSYS if the operation isn't supported
  871. */
  872. static int pci_mmap_legacy_io(struct file *filp, struct kobject *kobj,
  873. struct bin_attribute *attr,
  874. struct vm_area_struct *vma)
  875. {
  876. struct pci_bus *bus = to_pci_bus(kobj_to_dev(kobj));
  877. return pci_mmap_legacy_page_range(bus, vma, pci_mmap_io);
  878. }
  879. /**
  880. * pci_adjust_legacy_attr - adjustment of legacy file attributes
  881. * @b: bus to create files under
  882. * @mmap_type: I/O port or memory
  883. *
  884. * Stub implementation. Can be overridden by arch if necessary.
  885. */
  886. void __weak pci_adjust_legacy_attr(struct pci_bus *b,
  887. enum pci_mmap_state mmap_type)
  888. {
  889. }
  890. /**
  891. * pci_create_legacy_files - create legacy I/O port and memory files
  892. * @b: bus to create files under
  893. *
  894. * Some platforms allow access to legacy I/O port and ISA memory space on
  895. * a per-bus basis. This routine creates the files and ties them into
  896. * their associated read, write and mmap files from pci-sysfs.c
  897. *
  898. * On error unwind, but don't propagate the error to the caller
  899. * as it is ok to set up the PCI bus without these files.
  900. */
  901. void pci_create_legacy_files(struct pci_bus *b)
  902. {
  903. int error;
  904. b->legacy_io = kcalloc(2, sizeof(struct bin_attribute),
  905. GFP_ATOMIC);
  906. if (!b->legacy_io)
  907. goto kzalloc_err;
  908. sysfs_bin_attr_init(b->legacy_io);
  909. b->legacy_io->attr.name = "legacy_io";
  910. b->legacy_io->size = 0xffff;
  911. b->legacy_io->attr.mode = S_IRUSR | S_IWUSR;
  912. b->legacy_io->read = pci_read_legacy_io;
  913. b->legacy_io->write = pci_write_legacy_io;
  914. b->legacy_io->mmap = pci_mmap_legacy_io;
  915. pci_adjust_legacy_attr(b, pci_mmap_io);
  916. error = device_create_bin_file(&b->dev, b->legacy_io);
  917. if (error)
  918. goto legacy_io_err;
  919. /* Allocated above after the legacy_io struct */
  920. b->legacy_mem = b->legacy_io + 1;
  921. sysfs_bin_attr_init(b->legacy_mem);
  922. b->legacy_mem->attr.name = "legacy_mem";
  923. b->legacy_mem->size = 1024*1024;
  924. b->legacy_mem->attr.mode = S_IRUSR | S_IWUSR;
  925. b->legacy_mem->mmap = pci_mmap_legacy_mem;
  926. pci_adjust_legacy_attr(b, pci_mmap_mem);
  927. error = device_create_bin_file(&b->dev, b->legacy_mem);
  928. if (error)
  929. goto legacy_mem_err;
  930. return;
  931. legacy_mem_err:
  932. device_remove_bin_file(&b->dev, b->legacy_io);
  933. legacy_io_err:
  934. kfree(b->legacy_io);
  935. b->legacy_io = NULL;
  936. kzalloc_err:
  937. printk(KERN_WARNING "pci: warning: could not create legacy I/O port and ISA memory resources to sysfs\n");
  938. return;
  939. }
  940. void pci_remove_legacy_files(struct pci_bus *b)
  941. {
  942. if (b->legacy_io) {
  943. device_remove_bin_file(&b->dev, b->legacy_io);
  944. device_remove_bin_file(&b->dev, b->legacy_mem);
  945. kfree(b->legacy_io); /* both are allocated here */
  946. }
  947. }
  948. #endif /* HAVE_PCI_LEGACY */
  949. #if defined(HAVE_PCI_MMAP) || defined(ARCH_GENERIC_PCI_MMAP_RESOURCE)
  950. int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vma,
  951. enum pci_mmap_api mmap_api)
  952. {
  953. unsigned long nr, start, size;
  954. resource_size_t pci_start = 0, pci_end;
  955. if (pci_resource_len(pdev, resno) == 0)
  956. return 0;
  957. nr = vma_pages(vma);
  958. start = vma->vm_pgoff;
  959. size = ((pci_resource_len(pdev, resno) - 1) >> PAGE_SHIFT) + 1;
  960. if (mmap_api == PCI_MMAP_PROCFS) {
  961. pci_resource_to_user(pdev, resno, &pdev->resource[resno],
  962. &pci_start, &pci_end);
  963. pci_start >>= PAGE_SHIFT;
  964. }
  965. if (start >= pci_start && start < pci_start + size &&
  966. start + nr <= pci_start + size)
  967. return 1;
  968. return 0;
  969. }
  970. /**
  971. * pci_mmap_resource - map a PCI resource into user memory space
  972. * @kobj: kobject for mapping
  973. * @attr: struct bin_attribute for the file being mapped
  974. * @vma: struct vm_area_struct passed into the mmap
  975. * @write_combine: 1 for write_combine mapping
  976. *
  977. * Use the regular PCI mapping routines to map a PCI resource into userspace.
  978. */
  979. static int pci_mmap_resource(struct kobject *kobj, struct bin_attribute *attr,
  980. struct vm_area_struct *vma, int write_combine)
  981. {
  982. struct pci_dev *pdev = to_pci_dev(kobj_to_dev(kobj));
  983. int bar = (unsigned long)attr->private;
  984. enum pci_mmap_state mmap_type;
  985. struct resource *res = &pdev->resource[bar];
  986. if (res->flags & IORESOURCE_MEM && iomem_is_exclusive(res->start))
  987. return -EINVAL;
  988. if (!pci_mmap_fits(pdev, bar, vma, PCI_MMAP_SYSFS))
  989. return -EINVAL;
  990. mmap_type = res->flags & IORESOURCE_MEM ? pci_mmap_mem : pci_mmap_io;
  991. return pci_mmap_resource_range(pdev, bar, vma, mmap_type, write_combine);
  992. }
  993. static int pci_mmap_resource_uc(struct file *filp, struct kobject *kobj,
  994. struct bin_attribute *attr,
  995. struct vm_area_struct *vma)
  996. {
  997. return pci_mmap_resource(kobj, attr, vma, 0);
  998. }
  999. static int pci_mmap_resource_wc(struct file *filp, struct kobject *kobj,
  1000. struct bin_attribute *attr,
  1001. struct vm_area_struct *vma)
  1002. {
  1003. return pci_mmap_resource(kobj, attr, vma, 1);
  1004. }
  1005. static ssize_t pci_resource_io(struct file *filp, struct kobject *kobj,
  1006. struct bin_attribute *attr, char *buf,
  1007. loff_t off, size_t count, bool write)
  1008. {
  1009. struct pci_dev *pdev = to_pci_dev(kobj_to_dev(kobj));
  1010. int bar = (unsigned long)attr->private;
  1011. unsigned long port = off;
  1012. port += pci_resource_start(pdev, bar);
  1013. if (port > pci_resource_end(pdev, bar))
  1014. return 0;
  1015. if (port + count - 1 > pci_resource_end(pdev, bar))
  1016. return -EINVAL;
  1017. switch (count) {
  1018. case 1:
  1019. if (write)
  1020. outb(*(u8 *)buf, port);
  1021. else
  1022. *(u8 *)buf = inb(port);
  1023. return 1;
  1024. case 2:
  1025. if (write)
  1026. outw(*(u16 *)buf, port);
  1027. else
  1028. *(u16 *)buf = inw(port);
  1029. return 2;
  1030. case 4:
  1031. if (write)
  1032. outl(*(u32 *)buf, port);
  1033. else
  1034. *(u32 *)buf = inl(port);
  1035. return 4;
  1036. }
  1037. return -EINVAL;
  1038. }
  1039. static ssize_t pci_read_resource_io(struct file *filp, struct kobject *kobj,
  1040. struct bin_attribute *attr, char *buf,
  1041. loff_t off, size_t count)
  1042. {
  1043. return pci_resource_io(filp, kobj, attr, buf, off, count, false);
  1044. }
  1045. static ssize_t pci_write_resource_io(struct file *filp, struct kobject *kobj,
  1046. struct bin_attribute *attr, char *buf,
  1047. loff_t off, size_t count)
  1048. {
  1049. return pci_resource_io(filp, kobj, attr, buf, off, count, true);
  1050. }
  1051. /**
  1052. * pci_remove_resource_files - cleanup resource files
  1053. * @pdev: dev to cleanup
  1054. *
  1055. * If we created resource files for @pdev, remove them from sysfs and
  1056. * free their resources.
  1057. */
  1058. static void pci_remove_resource_files(struct pci_dev *pdev)
  1059. {
  1060. int i;
  1061. for (i = 0; i < PCI_ROM_RESOURCE; i++) {
  1062. struct bin_attribute *res_attr;
  1063. res_attr = pdev->res_attr[i];
  1064. if (res_attr) {
  1065. sysfs_remove_bin_file(&pdev->dev.kobj, res_attr);
  1066. kfree(res_attr);
  1067. }
  1068. res_attr = pdev->res_attr_wc[i];
  1069. if (res_attr) {
  1070. sysfs_remove_bin_file(&pdev->dev.kobj, res_attr);
  1071. kfree(res_attr);
  1072. }
  1073. }
  1074. }
  1075. static int pci_create_attr(struct pci_dev *pdev, int num, int write_combine)
  1076. {
  1077. /* allocate attribute structure, piggyback attribute name */
  1078. int name_len = write_combine ? 13 : 10;
  1079. struct bin_attribute *res_attr;
  1080. char *res_attr_name;
  1081. int retval;
  1082. res_attr = kzalloc(sizeof(*res_attr) + name_len, GFP_ATOMIC);
  1083. if (!res_attr)
  1084. return -ENOMEM;
  1085. res_attr_name = (char *)(res_attr + 1);
  1086. sysfs_bin_attr_init(res_attr);
  1087. if (write_combine) {
  1088. pdev->res_attr_wc[num] = res_attr;
  1089. sprintf(res_attr_name, "resource%d_wc", num);
  1090. res_attr->mmap = pci_mmap_resource_wc;
  1091. } else {
  1092. pdev->res_attr[num] = res_attr;
  1093. sprintf(res_attr_name, "resource%d", num);
  1094. if (pci_resource_flags(pdev, num) & IORESOURCE_IO) {
  1095. res_attr->read = pci_read_resource_io;
  1096. res_attr->write = pci_write_resource_io;
  1097. if (arch_can_pci_mmap_io())
  1098. res_attr->mmap = pci_mmap_resource_uc;
  1099. } else {
  1100. res_attr->mmap = pci_mmap_resource_uc;
  1101. }
  1102. }
  1103. res_attr->attr.name = res_attr_name;
  1104. res_attr->attr.mode = S_IRUSR | S_IWUSR;
  1105. res_attr->size = pci_resource_len(pdev, num);
  1106. res_attr->private = (void *)(unsigned long)num;
  1107. retval = sysfs_create_bin_file(&pdev->dev.kobj, res_attr);
  1108. if (retval)
  1109. kfree(res_attr);
  1110. return retval;
  1111. }
  1112. /**
  1113. * pci_create_resource_files - create resource files in sysfs for @dev
  1114. * @pdev: dev in question
  1115. *
  1116. * Walk the resources in @pdev creating files for each resource available.
  1117. */
  1118. static int pci_create_resource_files(struct pci_dev *pdev)
  1119. {
  1120. int i;
  1121. int retval;
  1122. /* Expose the PCI resources from this device as files */
  1123. for (i = 0; i < PCI_ROM_RESOURCE; i++) {
  1124. /* skip empty resources */
  1125. if (!pci_resource_len(pdev, i))
  1126. continue;
  1127. retval = pci_create_attr(pdev, i, 0);
  1128. /* for prefetchable resources, create a WC mappable file */
  1129. if (!retval && arch_can_pci_mmap_wc() &&
  1130. pdev->resource[i].flags & IORESOURCE_PREFETCH)
  1131. retval = pci_create_attr(pdev, i, 1);
  1132. if (retval) {
  1133. pci_remove_resource_files(pdev);
  1134. return retval;
  1135. }
  1136. }
  1137. return 0;
  1138. }
  1139. #else /* !HAVE_PCI_MMAP */
  1140. int __weak pci_create_resource_files(struct pci_dev *dev) { return 0; }
  1141. void __weak pci_remove_resource_files(struct pci_dev *dev) { return; }
  1142. #endif /* HAVE_PCI_MMAP */
  1143. /**
  1144. * pci_write_rom - used to enable access to the PCI ROM display
  1145. * @filp: sysfs file
  1146. * @kobj: kernel object handle
  1147. * @bin_attr: struct bin_attribute for this file
  1148. * @buf: user input
  1149. * @off: file offset
  1150. * @count: number of byte in input
  1151. *
  1152. * writing anything except 0 enables it
  1153. */
  1154. static ssize_t pci_write_rom(struct file *filp, struct kobject *kobj,
  1155. struct bin_attribute *bin_attr, char *buf,
  1156. loff_t off, size_t count)
  1157. {
  1158. struct pci_dev *pdev = to_pci_dev(kobj_to_dev(kobj));
  1159. if ((off == 0) && (*buf == '0') && (count == 2))
  1160. pdev->rom_attr_enabled = 0;
  1161. else
  1162. pdev->rom_attr_enabled = 1;
  1163. return count;
  1164. }
  1165. /**
  1166. * pci_read_rom - read a PCI ROM
  1167. * @filp: sysfs file
  1168. * @kobj: kernel object handle
  1169. * @bin_attr: struct bin_attribute for this file
  1170. * @buf: where to put the data we read from the ROM
  1171. * @off: file offset
  1172. * @count: number of bytes to read
  1173. *
  1174. * Put @count bytes starting at @off into @buf from the ROM in the PCI
  1175. * device corresponding to @kobj.
  1176. */
  1177. static ssize_t pci_read_rom(struct file *filp, struct kobject *kobj,
  1178. struct bin_attribute *bin_attr, char *buf,
  1179. loff_t off, size_t count)
  1180. {
  1181. struct pci_dev *pdev = to_pci_dev(kobj_to_dev(kobj));
  1182. void __iomem *rom;
  1183. size_t size;
  1184. if (!pdev->rom_attr_enabled)
  1185. return -EINVAL;
  1186. rom = pci_map_rom(pdev, &size); /* size starts out as PCI window size */
  1187. if (!rom || !size)
  1188. return -EIO;
  1189. if (off >= size)
  1190. count = 0;
  1191. else {
  1192. if (off + count > size)
  1193. count = size - off;
  1194. memcpy_fromio(buf, rom + off, count);
  1195. }
  1196. pci_unmap_rom(pdev, rom);
  1197. return count;
  1198. }
  1199. static const struct bin_attribute pci_config_attr = {
  1200. .attr = {
  1201. .name = "config",
  1202. .mode = S_IRUGO | S_IWUSR,
  1203. },
  1204. .size = PCI_CFG_SPACE_SIZE,
  1205. .read = pci_read_config,
  1206. .write = pci_write_config,
  1207. };
  1208. static const struct bin_attribute pcie_config_attr = {
  1209. .attr = {
  1210. .name = "config",
  1211. .mode = S_IRUGO | S_IWUSR,
  1212. },
  1213. .size = PCI_CFG_SPACE_EXP_SIZE,
  1214. .read = pci_read_config,
  1215. .write = pci_write_config,
  1216. };
  1217. static ssize_t reset_store(struct device *dev, struct device_attribute *attr,
  1218. const char *buf, size_t count)
  1219. {
  1220. struct pci_dev *pdev = to_pci_dev(dev);
  1221. unsigned long val;
  1222. ssize_t result = kstrtoul(buf, 0, &val);
  1223. if (result < 0)
  1224. return result;
  1225. if (val != 1)
  1226. return -EINVAL;
  1227. pm_runtime_get_sync(dev);
  1228. result = pci_reset_function(pdev);
  1229. pm_runtime_put(dev);
  1230. if (result < 0)
  1231. return result;
  1232. return count;
  1233. }
  1234. static struct device_attribute reset_attr = __ATTR(reset, 0200, NULL, reset_store);
  1235. static int pci_create_capabilities_sysfs(struct pci_dev *dev)
  1236. {
  1237. int retval;
  1238. pcie_vpd_create_sysfs_dev_files(dev);
  1239. pcie_aspm_create_sysfs_dev_files(dev);
  1240. if (dev->reset_fn) {
  1241. retval = device_create_file(&dev->dev, &reset_attr);
  1242. if (retval)
  1243. goto error;
  1244. }
  1245. return 0;
  1246. error:
  1247. pcie_aspm_remove_sysfs_dev_files(dev);
  1248. pcie_vpd_remove_sysfs_dev_files(dev);
  1249. return retval;
  1250. }
  1251. int __must_check pci_create_sysfs_dev_files(struct pci_dev *pdev)
  1252. {
  1253. int retval;
  1254. int rom_size;
  1255. struct bin_attribute *attr;
  1256. if (!sysfs_initialized)
  1257. return -EACCES;
  1258. if (pdev->cfg_size > PCI_CFG_SPACE_SIZE)
  1259. retval = sysfs_create_bin_file(&pdev->dev.kobj, &pcie_config_attr);
  1260. else
  1261. retval = sysfs_create_bin_file(&pdev->dev.kobj, &pci_config_attr);
  1262. if (retval)
  1263. goto err;
  1264. retval = pci_create_resource_files(pdev);
  1265. if (retval)
  1266. goto err_config_file;
  1267. /* If the device has a ROM, try to expose it in sysfs. */
  1268. rom_size = pci_resource_len(pdev, PCI_ROM_RESOURCE);
  1269. if (rom_size) {
  1270. attr = kzalloc(sizeof(*attr), GFP_ATOMIC);
  1271. if (!attr) {
  1272. retval = -ENOMEM;
  1273. goto err_resource_files;
  1274. }
  1275. sysfs_bin_attr_init(attr);
  1276. attr->size = rom_size;
  1277. attr->attr.name = "rom";
  1278. attr->attr.mode = S_IRUSR | S_IWUSR;
  1279. attr->read = pci_read_rom;
  1280. attr->write = pci_write_rom;
  1281. retval = sysfs_create_bin_file(&pdev->dev.kobj, attr);
  1282. if (retval) {
  1283. kfree(attr);
  1284. goto err_resource_files;
  1285. }
  1286. pdev->rom_attr = attr;
  1287. }
  1288. /* add sysfs entries for various capabilities */
  1289. retval = pci_create_capabilities_sysfs(pdev);
  1290. if (retval)
  1291. goto err_rom_file;
  1292. pci_create_firmware_label_files(pdev);
  1293. return 0;
  1294. err_rom_file:
  1295. if (pdev->rom_attr) {
  1296. sysfs_remove_bin_file(&pdev->dev.kobj, pdev->rom_attr);
  1297. kfree(pdev->rom_attr);
  1298. pdev->rom_attr = NULL;
  1299. }
  1300. err_resource_files:
  1301. pci_remove_resource_files(pdev);
  1302. err_config_file:
  1303. if (pdev->cfg_size > PCI_CFG_SPACE_SIZE)
  1304. sysfs_remove_bin_file(&pdev->dev.kobj, &pcie_config_attr);
  1305. else
  1306. sysfs_remove_bin_file(&pdev->dev.kobj, &pci_config_attr);
  1307. err:
  1308. return retval;
  1309. }
  1310. static void pci_remove_capabilities_sysfs(struct pci_dev *dev)
  1311. {
  1312. pcie_vpd_remove_sysfs_dev_files(dev);
  1313. pcie_aspm_remove_sysfs_dev_files(dev);
  1314. if (dev->reset_fn) {
  1315. device_remove_file(&dev->dev, &reset_attr);
  1316. dev->reset_fn = 0;
  1317. }
  1318. }
  1319. /**
  1320. * pci_remove_sysfs_dev_files - cleanup PCI specific sysfs files
  1321. * @pdev: device whose entries we should free
  1322. *
  1323. * Cleanup when @pdev is removed from sysfs.
  1324. */
  1325. void pci_remove_sysfs_dev_files(struct pci_dev *pdev)
  1326. {
  1327. if (!sysfs_initialized)
  1328. return;
  1329. pci_remove_capabilities_sysfs(pdev);
  1330. if (pdev->cfg_size > PCI_CFG_SPACE_SIZE)
  1331. sysfs_remove_bin_file(&pdev->dev.kobj, &pcie_config_attr);
  1332. else
  1333. sysfs_remove_bin_file(&pdev->dev.kobj, &pci_config_attr);
  1334. pci_remove_resource_files(pdev);
  1335. if (pdev->rom_attr) {
  1336. sysfs_remove_bin_file(&pdev->dev.kobj, pdev->rom_attr);
  1337. kfree(pdev->rom_attr);
  1338. pdev->rom_attr = NULL;
  1339. }
  1340. pci_remove_firmware_label_files(pdev);
  1341. }
  1342. static int __init pci_sysfs_init(void)
  1343. {
  1344. struct pci_dev *pdev = NULL;
  1345. int retval;
  1346. sysfs_initialized = 1;
  1347. for_each_pci_dev(pdev) {
  1348. retval = pci_create_sysfs_dev_files(pdev);
  1349. if (retval) {
  1350. pci_dev_put(pdev);
  1351. return retval;
  1352. }
  1353. }
  1354. return 0;
  1355. }
  1356. late_initcall(pci_sysfs_init);
  1357. static struct attribute *pci_dev_dev_attrs[] = {
  1358. &vga_attr.attr,
  1359. NULL,
  1360. };
  1361. static umode_t pci_dev_attrs_are_visible(struct kobject *kobj,
  1362. struct attribute *a, int n)
  1363. {
  1364. struct device *dev = kobj_to_dev(kobj);
  1365. struct pci_dev *pdev = to_pci_dev(dev);
  1366. if (a == &vga_attr.attr)
  1367. if ((pdev->class >> 8) != PCI_CLASS_DISPLAY_VGA)
  1368. return 0;
  1369. return a->mode;
  1370. }
  1371. static struct attribute *pci_dev_hp_attrs[] = {
  1372. &dev_remove_attr.attr,
  1373. &dev_rescan_attr.attr,
  1374. NULL,
  1375. };
  1376. static umode_t pci_dev_hp_attrs_are_visible(struct kobject *kobj,
  1377. struct attribute *a, int n)
  1378. {
  1379. struct device *dev = kobj_to_dev(kobj);
  1380. struct pci_dev *pdev = to_pci_dev(dev);
  1381. if (pdev->is_virtfn)
  1382. return 0;
  1383. return a->mode;
  1384. }
  1385. static umode_t pci_bridge_attrs_are_visible(struct kobject *kobj,
  1386. struct attribute *a, int n)
  1387. {
  1388. struct device *dev = kobj_to_dev(kobj);
  1389. struct pci_dev *pdev = to_pci_dev(dev);
  1390. if (pci_is_bridge(pdev))
  1391. return a->mode;
  1392. return 0;
  1393. }
  1394. static umode_t pcie_dev_attrs_are_visible(struct kobject *kobj,
  1395. struct attribute *a, int n)
  1396. {
  1397. struct device *dev = kobj_to_dev(kobj);
  1398. struct pci_dev *pdev = to_pci_dev(dev);
  1399. if (pci_is_pcie(pdev))
  1400. return a->mode;
  1401. return 0;
  1402. }
  1403. static const struct attribute_group pci_dev_group = {
  1404. .attrs = pci_dev_attrs,
  1405. };
  1406. const struct attribute_group *pci_dev_groups[] = {
  1407. &pci_dev_group,
  1408. NULL,
  1409. };
  1410. static const struct attribute_group pci_bridge_group = {
  1411. .attrs = pci_bridge_attrs,
  1412. };
  1413. const struct attribute_group *pci_bridge_groups[] = {
  1414. &pci_bridge_group,
  1415. NULL,
  1416. };
  1417. static const struct attribute_group pcie_dev_group = {
  1418. .attrs = pcie_dev_attrs,
  1419. };
  1420. const struct attribute_group *pcie_dev_groups[] = {
  1421. &pcie_dev_group,
  1422. NULL,
  1423. };
  1424. static const struct attribute_group pci_dev_hp_attr_group = {
  1425. .attrs = pci_dev_hp_attrs,
  1426. .is_visible = pci_dev_hp_attrs_are_visible,
  1427. };
  1428. #ifdef CONFIG_PCI_IOV
  1429. static struct attribute *sriov_dev_attrs[] = {
  1430. &sriov_totalvfs_attr.attr,
  1431. &sriov_numvfs_attr.attr,
  1432. &sriov_offset_attr.attr,
  1433. &sriov_stride_attr.attr,
  1434. &sriov_vf_device_attr.attr,
  1435. &sriov_drivers_autoprobe_attr.attr,
  1436. NULL,
  1437. };
  1438. static umode_t sriov_attrs_are_visible(struct kobject *kobj,
  1439. struct attribute *a, int n)
  1440. {
  1441. struct device *dev = kobj_to_dev(kobj);
  1442. if (!dev_is_pf(dev))
  1443. return 0;
  1444. return a->mode;
  1445. }
  1446. static const struct attribute_group sriov_dev_attr_group = {
  1447. .attrs = sriov_dev_attrs,
  1448. .is_visible = sriov_attrs_are_visible,
  1449. };
  1450. #endif /* CONFIG_PCI_IOV */
  1451. static const struct attribute_group pci_dev_attr_group = {
  1452. .attrs = pci_dev_dev_attrs,
  1453. .is_visible = pci_dev_attrs_are_visible,
  1454. };
  1455. static const struct attribute_group pci_bridge_attr_group = {
  1456. .attrs = pci_bridge_attrs,
  1457. .is_visible = pci_bridge_attrs_are_visible,
  1458. };
  1459. static const struct attribute_group pcie_dev_attr_group = {
  1460. .attrs = pcie_dev_attrs,
  1461. .is_visible = pcie_dev_attrs_are_visible,
  1462. };
  1463. static const struct attribute_group *pci_dev_attr_groups[] = {
  1464. &pci_dev_attr_group,
  1465. &pci_dev_hp_attr_group,
  1466. #ifdef CONFIG_PCI_IOV
  1467. &sriov_dev_attr_group,
  1468. #endif
  1469. &pci_bridge_attr_group,
  1470. &pcie_dev_attr_group,
  1471. #ifdef CONFIG_PCIEAER
  1472. &aer_stats_attr_group,
  1473. #endif
  1474. NULL,
  1475. };
  1476. const struct device_type pci_dev_type = {
  1477. .groups = pci_dev_attr_groups,
  1478. };