psu_spl_init.c 1.4 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2018 Xilinx, Inc.
  4. *
  5. * Michal Simek <michal.simek@xilinx.com>
  6. */
  7. #include <common.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/psu_init_gpl.h>
  10. #define PSU_MASK_POLL_TIME 1100000
  11. int __maybe_unused mask_pollonvalue(unsigned long add, u32 mask, u32 value)
  12. {
  13. int i = 0;
  14. while ((__raw_readl(add) & mask) != value) {
  15. if (i == PSU_MASK_POLL_TIME)
  16. return 0;
  17. i++;
  18. }
  19. return 1;
  20. }
  21. __weak int mask_poll(u32 add, u32 mask)
  22. {
  23. int i = 0;
  24. unsigned long addr = add;
  25. while (!(__raw_readl(addr) & mask)) {
  26. if (i == PSU_MASK_POLL_TIME)
  27. return 0;
  28. i++;
  29. }
  30. return 1;
  31. }
  32. __weak u32 mask_read(u32 add, u32 mask)
  33. {
  34. unsigned long addr = add;
  35. return __raw_readl(addr) & mask;
  36. }
  37. __weak void mask_delay(u32 delay)
  38. {
  39. udelay(delay);
  40. }
  41. __weak void psu_mask_write(unsigned long offset, unsigned long mask,
  42. unsigned long val)
  43. {
  44. unsigned long regval = 0;
  45. regval = readl(offset);
  46. regval &= ~(mask);
  47. regval |= (val & mask);
  48. writel(regval, offset);
  49. }
  50. __weak void prog_reg(unsigned long addr, unsigned long mask,
  51. unsigned long shift, unsigned long value)
  52. {
  53. int rdata = 0;
  54. rdata = readl(addr);
  55. rdata = rdata & (~mask);
  56. rdata = rdata | (value << shift);
  57. writel(rdata, addr);
  58. }
  59. __weak int psu_init(void)
  60. {
  61. /*
  62. * This function is overridden by the one in
  63. * board/xilinx/zynqmp/(platform)/psu_init_gpl.c, if it exists.
  64. */
  65. return -1;
  66. }