soc.c 2.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007
  4. * Sascha Hauer, Pengutronix
  5. *
  6. * (C) Copyright 2009 Freescale Semiconductor, Inc.
  7. */
  8. #include <common.h>
  9. #include <asm/arch/imx-regs.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/arch/sys_proto.h>
  12. #include <linux/errno.h>
  13. #include <asm/io.h>
  14. #include <asm/mach-imx/boot_mode.h>
  15. #if !(defined(CONFIG_MX51) || defined(CONFIG_MX53))
  16. #error "CPU_TYPE not defined"
  17. #endif
  18. u32 get_cpu_rev(void)
  19. {
  20. #ifdef CONFIG_MX51
  21. int system_rev = 0x51000;
  22. #else
  23. int system_rev = 0x53000;
  24. #endif
  25. int reg = __raw_readl(ROM_SI_REV);
  26. #if defined(CONFIG_MX51)
  27. switch (reg) {
  28. case 0x02:
  29. system_rev |= CHIP_REV_1_1;
  30. break;
  31. case 0x10:
  32. if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0)
  33. system_rev |= CHIP_REV_2_5;
  34. else
  35. system_rev |= CHIP_REV_2_0;
  36. break;
  37. case 0x20:
  38. system_rev |= CHIP_REV_3_0;
  39. break;
  40. default:
  41. system_rev |= CHIP_REV_1_0;
  42. break;
  43. }
  44. #else
  45. if (reg < 0x20)
  46. system_rev |= CHIP_REV_1_0;
  47. else
  48. system_rev |= reg;
  49. #endif
  50. return system_rev;
  51. }
  52. #ifdef CONFIG_REVISION_TAG
  53. u32 __weak get_board_rev(void)
  54. {
  55. return get_cpu_rev();
  56. }
  57. #endif
  58. #ifndef CONFIG_SYS_DCACHE_OFF
  59. void enable_caches(void)
  60. {
  61. /* Enable D-cache. I-cache is already enabled in start.S */
  62. dcache_enable();
  63. }
  64. #endif
  65. #if defined(CONFIG_FEC_MXC)
  66. void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
  67. {
  68. int i;
  69. struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
  70. struct fuse_bank *bank = &iim->bank[1];
  71. struct fuse_bank1_regs *fuse =
  72. (struct fuse_bank1_regs *)bank->fuse_regs;
  73. for (i = 0; i < 6; i++)
  74. mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
  75. }
  76. #endif
  77. #ifdef CONFIG_MX53
  78. void boot_mode_apply(unsigned cfg_val)
  79. {
  80. writel(cfg_val, &((struct srtc_regs *)SRTC_BASE_ADDR)->lpgr);
  81. }
  82. /*
  83. * cfg_val will be used for
  84. * Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
  85. *
  86. * If bit 28 of LPGR is set upon watchdog reset,
  87. * bits[25:0] of LPGR will move to SBMR.
  88. */
  89. const struct boot_mode soc_boot_modes[] = {
  90. {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
  91. /* usb or serial download */
  92. {"usb", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x13)},
  93. {"sata", MAKE_CFGVAL(0x28, 0x00, 0x00, 0x12)},
  94. {"escpi1:0", MAKE_CFGVAL(0x38, 0x20, 0x00, 0x12)},
  95. {"escpi1:1", MAKE_CFGVAL(0x38, 0x20, 0x04, 0x12)},
  96. {"escpi1:2", MAKE_CFGVAL(0x38, 0x20, 0x08, 0x12)},
  97. {"escpi1:3", MAKE_CFGVAL(0x38, 0x20, 0x0c, 0x12)},
  98. /* 4 bit bus width */
  99. {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)},
  100. {"esdhc2", MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)},
  101. {"esdhc3", MAKE_CFGVAL(0x40, 0x20, 0x10, 0x12)},
  102. {"esdhc4", MAKE_CFGVAL(0x40, 0x20, 0x18, 0x12)},
  103. {NULL, 0},
  104. };
  105. #endif