cpu.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de>
  4. */
  5. #include <common.h>
  6. #include <ahci.h>
  7. #include <linux/mbus.h>
  8. #include <asm/io.h>
  9. #include <asm/pl310.h>
  10. #include <asm/arch/cpu.h>
  11. #include <asm/arch/soc.h>
  12. #include <sdhci.h>
  13. #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
  14. #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
  15. static struct mbus_win windows[] = {
  16. /* SPI */
  17. { MBUS_SPI_BASE, MBUS_SPI_SIZE,
  18. CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPIFLASH },
  19. /* NOR */
  20. { MBUS_BOOTROM_BASE, MBUS_BOOTROM_SIZE,
  21. CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM },
  22. };
  23. void lowlevel_init(void)
  24. {
  25. /*
  26. * Dummy implementation, we only need LOWLEVEL_INIT
  27. * on Armada to configure CP15 in start.S / cpu_init_cp15()
  28. */
  29. }
  30. void reset_cpu(unsigned long ignored)
  31. {
  32. struct mvebu_system_registers *reg =
  33. (struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE;
  34. writel(readl(&reg->rstoutn_mask) | 1, &reg->rstoutn_mask);
  35. writel(readl(&reg->sys_soft_rst) | 1, &reg->sys_soft_rst);
  36. while (1)
  37. ;
  38. }
  39. int mvebu_soc_family(void)
  40. {
  41. u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
  42. switch (devid) {
  43. case SOC_MV78230_ID:
  44. case SOC_MV78260_ID:
  45. case SOC_MV78460_ID:
  46. return MVEBU_SOC_AXP;
  47. case SOC_88F6720_ID:
  48. return MVEBU_SOC_A375;
  49. case SOC_88F6810_ID:
  50. case SOC_88F6820_ID:
  51. case SOC_88F6828_ID:
  52. return MVEBU_SOC_A38X;
  53. case SOC_98DX3236_ID:
  54. case SOC_98DX3336_ID:
  55. case SOC_98DX4251_ID:
  56. return MVEBU_SOC_MSYS;
  57. }
  58. return MVEBU_SOC_UNKNOWN;
  59. }
  60. #if defined(CONFIG_DISPLAY_CPUINFO)
  61. #if defined(CONFIG_ARMADA_375)
  62. /* SAR frequency values for Armada 375 */
  63. static const struct sar_freq_modes sar_freq_tab[] = {
  64. { 0, 0x0, 266, 133, 266 },
  65. { 1, 0x0, 333, 167, 167 },
  66. { 2, 0x0, 333, 167, 222 },
  67. { 3, 0x0, 333, 167, 333 },
  68. { 4, 0x0, 400, 200, 200 },
  69. { 5, 0x0, 400, 200, 267 },
  70. { 6, 0x0, 400, 200, 400 },
  71. { 7, 0x0, 500, 250, 250 },
  72. { 8, 0x0, 500, 250, 334 },
  73. { 9, 0x0, 500, 250, 500 },
  74. { 10, 0x0, 533, 267, 267 },
  75. { 11, 0x0, 533, 267, 356 },
  76. { 12, 0x0, 533, 267, 533 },
  77. { 13, 0x0, 600, 300, 300 },
  78. { 14, 0x0, 600, 300, 400 },
  79. { 15, 0x0, 600, 300, 600 },
  80. { 16, 0x0, 666, 333, 333 },
  81. { 17, 0x0, 666, 333, 444 },
  82. { 18, 0x0, 666, 333, 666 },
  83. { 19, 0x0, 800, 400, 267 },
  84. { 20, 0x0, 800, 400, 400 },
  85. { 21, 0x0, 800, 400, 534 },
  86. { 22, 0x0, 900, 450, 300 },
  87. { 23, 0x0, 900, 450, 450 },
  88. { 24, 0x0, 900, 450, 600 },
  89. { 25, 0x0, 1000, 500, 500 },
  90. { 26, 0x0, 1000, 500, 667 },
  91. { 27, 0x0, 1000, 333, 500 },
  92. { 28, 0x0, 400, 400, 400 },
  93. { 29, 0x0, 1100, 550, 550 },
  94. { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
  95. };
  96. #elif defined(CONFIG_ARMADA_38X)
  97. /* SAR frequency values for Armada 38x */
  98. static const struct sar_freq_modes sar_freq_tab[] = {
  99. { 0x0, 0x0, 666, 333, 333 },
  100. { 0x2, 0x0, 800, 400, 400 },
  101. { 0x4, 0x0, 1066, 533, 533 },
  102. { 0x6, 0x0, 1200, 600, 600 },
  103. { 0x8, 0x0, 1332, 666, 666 },
  104. { 0xc, 0x0, 1600, 800, 800 },
  105. { 0x10, 0x0, 1866, 933, 933 },
  106. { 0x13, 0x0, 2000, 1000, 933 },
  107. { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
  108. };
  109. #else
  110. /* SAR frequency values for Armada XP */
  111. static const struct sar_freq_modes sar_freq_tab[] = {
  112. { 0xa, 0x5, 800, 400, 400 },
  113. { 0x1, 0x5, 1066, 533, 533 },
  114. { 0x2, 0x5, 1200, 600, 600 },
  115. { 0x2, 0x9, 1200, 600, 400 },
  116. { 0x3, 0x5, 1333, 667, 667 },
  117. { 0x4, 0x5, 1500, 750, 750 },
  118. { 0x4, 0x9, 1500, 750, 500 },
  119. { 0xb, 0x9, 1600, 800, 533 },
  120. { 0xb, 0xa, 1600, 800, 640 },
  121. { 0xb, 0x5, 1600, 800, 800 },
  122. { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
  123. };
  124. #endif
  125. void get_sar_freq(struct sar_freq_modes *sar_freq)
  126. {
  127. u32 val;
  128. u32 freq;
  129. int i;
  130. #if defined(CONFIG_ARMADA_375)
  131. val = readl(CONFIG_SAR2_REG); /* SAR - Sample At Reset */
  132. #else
  133. val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */
  134. #endif
  135. freq = (val & SAR_CPU_FREQ_MASK) >> SAR_CPU_FREQ_OFFS;
  136. #if defined(SAR2_CPU_FREQ_MASK)
  137. /*
  138. * Shift CPU0 clock frequency select bit from SAR2 register
  139. * into correct position
  140. */
  141. freq |= ((readl(CONFIG_SAR2_REG) & SAR2_CPU_FREQ_MASK)
  142. >> SAR2_CPU_FREQ_OFFS) << 3;
  143. #endif
  144. for (i = 0; sar_freq_tab[i].val != 0xff; i++) {
  145. if (sar_freq_tab[i].val == freq) {
  146. #if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_38X)
  147. *sar_freq = sar_freq_tab[i];
  148. return;
  149. #else
  150. int k;
  151. u8 ffc;
  152. ffc = (val & SAR_FFC_FREQ_MASK) >>
  153. SAR_FFC_FREQ_OFFS;
  154. for (k = i; sar_freq_tab[k].ffc != 0xff; k++) {
  155. if (sar_freq_tab[k].ffc == ffc) {
  156. *sar_freq = sar_freq_tab[k];
  157. return;
  158. }
  159. }
  160. i = k;
  161. #endif
  162. }
  163. }
  164. /* SAR value not found, return 0 for frequencies */
  165. *sar_freq = sar_freq_tab[i - 1];
  166. }
  167. int print_cpuinfo(void)
  168. {
  169. u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
  170. u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff;
  171. struct sar_freq_modes sar_freq;
  172. puts("SoC: ");
  173. switch (devid) {
  174. case SOC_MV78230_ID:
  175. puts("MV78230-");
  176. break;
  177. case SOC_MV78260_ID:
  178. puts("MV78260-");
  179. break;
  180. case SOC_MV78460_ID:
  181. puts("MV78460-");
  182. break;
  183. case SOC_88F6720_ID:
  184. puts("MV88F6720-");
  185. break;
  186. case SOC_88F6810_ID:
  187. puts("MV88F6810-");
  188. break;
  189. case SOC_88F6820_ID:
  190. puts("MV88F6820-");
  191. break;
  192. case SOC_88F6828_ID:
  193. puts("MV88F6828-");
  194. break;
  195. case SOC_98DX3236_ID:
  196. puts("98DX3236-");
  197. break;
  198. case SOC_98DX3336_ID:
  199. puts("98DX3336-");
  200. break;
  201. case SOC_98DX4251_ID:
  202. puts("98DX4251-");
  203. break;
  204. default:
  205. puts("Unknown-");
  206. break;
  207. }
  208. if (mvebu_soc_family() == MVEBU_SOC_AXP) {
  209. switch (revid) {
  210. case 1:
  211. puts("A0");
  212. break;
  213. case 2:
  214. puts("B0");
  215. break;
  216. default:
  217. printf("?? (%x)", revid);
  218. break;
  219. }
  220. }
  221. if (mvebu_soc_family() == MVEBU_SOC_A375) {
  222. switch (revid) {
  223. case MV_88F67XX_A0_ID:
  224. puts("A0");
  225. break;
  226. default:
  227. printf("?? (%x)", revid);
  228. break;
  229. }
  230. }
  231. if (mvebu_soc_family() == MVEBU_SOC_A38X) {
  232. switch (revid) {
  233. case MV_88F68XX_Z1_ID:
  234. puts("Z1");
  235. break;
  236. case MV_88F68XX_A0_ID:
  237. puts("A0");
  238. break;
  239. default:
  240. printf("?? (%x)", revid);
  241. break;
  242. }
  243. }
  244. get_sar_freq(&sar_freq);
  245. printf(" at %d MHz\n", sar_freq.p_clk);
  246. return 0;
  247. }
  248. #endif /* CONFIG_DISPLAY_CPUINFO */
  249. /*
  250. * This function initialize Controller DRAM Fastpath windows.
  251. * It takes the CS size information from the 0x1500 scratch registers
  252. * and sets the correct windows sizes and base addresses accordingly.
  253. *
  254. * These values are set in the scratch registers by the Marvell
  255. * DDR3 training code, which is executed by the BootROM before the
  256. * main payload (U-Boot) is executed. This training code is currently
  257. * only available in the Marvell U-Boot version. It needs to be
  258. * ported to mainline U-Boot SPL at some point.
  259. */
  260. static void update_sdram_window_sizes(void)
  261. {
  262. u64 base = 0;
  263. u32 size, temp;
  264. int i;
  265. for (i = 0; i < SDRAM_MAX_CS; i++) {
  266. size = readl((MVEBU_SDRAM_SCRATCH + (i * 8))) & SDRAM_ADDR_MASK;
  267. if (size != 0) {
  268. size |= ~(SDRAM_ADDR_MASK);
  269. /* Set Base Address */
  270. temp = (base & 0xFF000000ll) | ((base >> 32) & 0xF);
  271. writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i));
  272. /*
  273. * Check if out of max window size and resize
  274. * the window
  275. */
  276. temp = (readl(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)) &
  277. ~(SDRAM_ADDR_MASK)) | 1;
  278. temp |= (size & SDRAM_ADDR_MASK);
  279. writel(temp, MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i));
  280. base += ((u64)size + 1);
  281. } else {
  282. /*
  283. * Disable window if not used, otherwise this
  284. * leads to overlapping enabled windows with
  285. * pretty strange results
  286. */
  287. clrbits_le32(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i), 1);
  288. }
  289. }
  290. }
  291. void mmu_disable(void)
  292. {
  293. asm volatile(
  294. "mrc p15, 0, r0, c1, c0, 0\n"
  295. "bic r0, #1\n"
  296. "mcr p15, 0, r0, c1, c0, 0\n");
  297. }
  298. #ifdef CONFIG_ARCH_CPU_INIT
  299. static void set_cbar(u32 addr)
  300. {
  301. asm("mcr p15, 4, %0, c15, c0" : : "r" (addr));
  302. }
  303. #define MV_USB_PHY_BASE (MVEBU_AXP_USB_BASE + 0x800)
  304. #define MV_USB_PHY_PLL_REG(reg) (MV_USB_PHY_BASE | (((reg) & 0xF) << 2))
  305. #define MV_USB_X3_BASE(addr) (MVEBU_AXP_USB_BASE | BIT(11) | \
  306. (((addr) & 0xF) << 6))
  307. #define MV_USB_X3_PHY_CHANNEL(dev, reg) (MV_USB_X3_BASE((dev) + 1) | \
  308. (((reg) & 0xF) << 2))
  309. static void setup_usb_phys(void)
  310. {
  311. int dev;
  312. /*
  313. * USB PLL init
  314. */
  315. /* Setup PLL frequency */
  316. /* USB REF frequency = 25 MHz */
  317. clrsetbits_le32(MV_USB_PHY_PLL_REG(1), 0x3ff, 0x605);
  318. /* Power up PLL and PHY channel */
  319. setbits_le32(MV_USB_PHY_PLL_REG(2), BIT(9));
  320. /* Assert VCOCAL_START */
  321. setbits_le32(MV_USB_PHY_PLL_REG(1), BIT(21));
  322. mdelay(1);
  323. /*
  324. * USB PHY init (change from defaults) specific for 40nm (78X30 78X60)
  325. */
  326. for (dev = 0; dev < 3; dev++) {
  327. setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 3), BIT(15));
  328. /* Assert REG_RCAL_START in channel REG 1 */
  329. setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12));
  330. udelay(40);
  331. clrbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12));
  332. }
  333. }
  334. /*
  335. * This function is not called from the SPL U-Boot version
  336. */
  337. int arch_cpu_init(void)
  338. {
  339. struct pl310_regs *const pl310 =
  340. (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  341. /*
  342. * Only with disabled MMU its possible to switch the base
  343. * register address on Armada 38x. Without this the SDRAM
  344. * located at >= 0x4000.0000 is also not accessible, as its
  345. * still locked to cache.
  346. */
  347. mmu_disable();
  348. /* Linux expects the internal registers to be at 0xf1000000 */
  349. writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
  350. set_cbar(SOC_REGS_PHY_BASE + 0xC000);
  351. /*
  352. * From this stage on, the SoC detection is working. As we have
  353. * configured the internal register base to the value used
  354. * in the macros / defines in the U-Boot header (soc.h).
  355. */
  356. if (mvebu_soc_family() == MVEBU_SOC_A38X) {
  357. /*
  358. * To fully release / unlock this area from cache, we need
  359. * to flush all caches and disable the L2 cache.
  360. */
  361. icache_disable();
  362. dcache_disable();
  363. clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  364. }
  365. /*
  366. * We need to call mvebu_mbus_probe() before calling
  367. * update_sdram_window_sizes() as it disables all previously
  368. * configured mbus windows and then configures them as
  369. * required for U-Boot. Calling update_sdram_window_sizes()
  370. * without this configuration will not work, as the internal
  371. * registers can't be accessed reliably because of potenial
  372. * double mapping.
  373. * After updating the SDRAM access windows we need to call
  374. * mvebu_mbus_probe() again, as this now correctly configures
  375. * the SDRAM areas that are later used by the MVEBU drivers
  376. * (e.g. USB, NETA).
  377. */
  378. /*
  379. * First disable all windows
  380. */
  381. mvebu_mbus_probe(NULL, 0);
  382. if (mvebu_soc_family() == MVEBU_SOC_AXP) {
  383. /*
  384. * Now the SDRAM access windows can be reconfigured using
  385. * the information in the SDRAM scratch pad registers
  386. */
  387. update_sdram_window_sizes();
  388. }
  389. /*
  390. * Finally the mbus windows can be configured with the
  391. * updated SDRAM sizes
  392. */
  393. mvebu_mbus_probe(windows, ARRAY_SIZE(windows));
  394. if (mvebu_soc_family() == MVEBU_SOC_AXP) {
  395. /* Enable GBE0, GBE1, LCD and NFC PUP */
  396. clrsetbits_le32(ARMADA_XP_PUP_ENABLE, 0,
  397. GE0_PUP_EN | GE1_PUP_EN | LCD_PUP_EN |
  398. NAND_PUP_EN | SPI_PUP_EN);
  399. /* Configure USB PLL and PHYs on AXP */
  400. setup_usb_phys();
  401. }
  402. /* Enable NAND and NAND arbiter */
  403. clrsetbits_le32(MVEBU_SOC_DEV_MUX_REG, 0, NAND_EN | NAND_ARBITER_EN);
  404. /* Disable MBUS error propagation */
  405. clrsetbits_le32(SOC_COHERENCY_FABRIC_CTRL_REG, MBUS_ERR_PROP_EN, 0);
  406. return 0;
  407. }
  408. #endif /* CONFIG_ARCH_CPU_INIT */
  409. u32 mvebu_get_nand_clock(void)
  410. {
  411. u32 reg;
  412. if (mvebu_soc_family() == MVEBU_SOC_A38X)
  413. reg = MVEBU_DFX_DIV_CLK_CTRL(1);
  414. else
  415. reg = MVEBU_CORE_DIV_CLK_CTRL(1);
  416. return CONFIG_SYS_MVEBU_PLL_CLOCK /
  417. ((readl(reg) &
  418. NAND_ECC_DIVCKL_RATIO_MASK) >> NAND_ECC_DIVCKL_RATIO_OFFS);
  419. }
  420. /*
  421. * SOC specific misc init
  422. */
  423. #if defined(CONFIG_ARCH_MISC_INIT)
  424. int arch_misc_init(void)
  425. {
  426. /* Nothing yet, perhaps we need something here later */
  427. return 0;
  428. }
  429. #endif /* CONFIG_ARCH_MISC_INIT */
  430. #ifdef CONFIG_MMC_SDHCI_MV
  431. int board_mmc_init(bd_t *bis)
  432. {
  433. mv_sdh_init(MVEBU_SDIO_BASE, 0, 0,
  434. SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD);
  435. return 0;
  436. }
  437. #endif
  438. #ifdef CONFIG_SCSI_AHCI_PLAT
  439. #define AHCI_VENDOR_SPECIFIC_0_ADDR 0xa0
  440. #define AHCI_VENDOR_SPECIFIC_0_DATA 0xa4
  441. #define AHCI_WINDOW_CTRL(win) (0x60 + ((win) << 4))
  442. #define AHCI_WINDOW_BASE(win) (0x64 + ((win) << 4))
  443. #define AHCI_WINDOW_SIZE(win) (0x68 + ((win) << 4))
  444. static void ahci_mvebu_mbus_config(void __iomem *base)
  445. {
  446. const struct mbus_dram_target_info *dram;
  447. int i;
  448. dram = mvebu_mbus_dram_info();
  449. for (i = 0; i < 4; i++) {
  450. writel(0, base + AHCI_WINDOW_CTRL(i));
  451. writel(0, base + AHCI_WINDOW_BASE(i));
  452. writel(0, base + AHCI_WINDOW_SIZE(i));
  453. }
  454. for (i = 0; i < dram->num_cs; i++) {
  455. const struct mbus_dram_window *cs = dram->cs + i;
  456. writel((cs->mbus_attr << 8) |
  457. (dram->mbus_dram_target_id << 4) | 1,
  458. base + AHCI_WINDOW_CTRL(i));
  459. writel(cs->base >> 16, base + AHCI_WINDOW_BASE(i));
  460. writel(((cs->size - 1) & 0xffff0000),
  461. base + AHCI_WINDOW_SIZE(i));
  462. }
  463. }
  464. static void ahci_mvebu_regret_option(void __iomem *base)
  465. {
  466. /*
  467. * Enable the regret bit to allow the SATA unit to regret a
  468. * request that didn't receive an acknowlegde and avoid a
  469. * deadlock
  470. */
  471. writel(0x4, base + AHCI_VENDOR_SPECIFIC_0_ADDR);
  472. writel(0x80, base + AHCI_VENDOR_SPECIFIC_0_DATA);
  473. }
  474. void scsi_init(void)
  475. {
  476. printf("MVEBU SATA INIT\n");
  477. ahci_mvebu_mbus_config((void __iomem *)MVEBU_SATA0_BASE);
  478. ahci_mvebu_regret_option((void __iomem *)MVEBU_SATA0_BASE);
  479. ahci_init((void __iomem *)MVEBU_SATA0_BASE);
  480. }
  481. #endif
  482. #ifdef CONFIG_USB_XHCI_MVEBU
  483. #define USB3_MAX_WINDOWS 4
  484. #define USB3_WIN_CTRL(w) (0x0 + ((w) * 8))
  485. #define USB3_WIN_BASE(w) (0x4 + ((w) * 8))
  486. static void xhci_mvebu_mbus_config(void __iomem *base,
  487. const struct mbus_dram_target_info *dram)
  488. {
  489. int i;
  490. for (i = 0; i < USB3_MAX_WINDOWS; i++) {
  491. writel(0, base + USB3_WIN_CTRL(i));
  492. writel(0, base + USB3_WIN_BASE(i));
  493. }
  494. for (i = 0; i < dram->num_cs; i++) {
  495. const struct mbus_dram_window *cs = dram->cs + i;
  496. /* Write size, attributes and target id to control register */
  497. writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
  498. (dram->mbus_dram_target_id << 4) | 1,
  499. base + USB3_WIN_CTRL(i));
  500. /* Write base address to base register */
  501. writel((cs->base & 0xffff0000), base + USB3_WIN_BASE(i));
  502. }
  503. }
  504. int board_xhci_enable(fdt_addr_t base)
  505. {
  506. const struct mbus_dram_target_info *dram;
  507. printf("MVEBU XHCI INIT controller @ 0x%lx\n", base);
  508. dram = mvebu_mbus_dram_info();
  509. xhci_mvebu_mbus_config((void __iomem *)base, dram);
  510. return 0;
  511. }
  512. #endif
  513. void enable_caches(void)
  514. {
  515. /* Avoid problem with e.g. neta ethernet driver */
  516. invalidate_dcache_all();
  517. /*
  518. * Armada 375 still has some problems with d-cache enabled in the
  519. * ethernet driver (mvpp2). So lets keep the d-cache disabled
  520. * until this is solved.
  521. */
  522. if (mvebu_soc_family() != MVEBU_SOC_A375) {
  523. /* Enable D-cache. I-cache is already enabled in start.S */
  524. dcache_enable();
  525. }
  526. }
  527. void v7_outer_cache_enable(void)
  528. {
  529. if (mvebu_soc_family() == MVEBU_SOC_AXP) {
  530. struct pl310_regs *const pl310 =
  531. (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  532. u32 u;
  533. /* The L2 cache is already disabled at this point */
  534. /*
  535. * For Aurora cache in no outer mode, enable via the CP15
  536. * coprocessor broadcasting of cache commands to L2.
  537. */
  538. asm volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (u));
  539. u |= BIT(8); /* Set the FW bit */
  540. asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u));
  541. isb();
  542. /* Enable the L2 cache */
  543. setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  544. }
  545. }
  546. void v7_outer_cache_disable(void)
  547. {
  548. struct pl310_regs *const pl310 =
  549. (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  550. clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  551. }