ti816x_emif4.c 6.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * ti816x_emif4.c
  4. *
  5. * TI816x emif4 configuration file
  6. *
  7. * Copyright (C) 2017, Konsulko Group
  8. */
  9. #include <common.h>
  10. #include <asm/arch/cpu.h>
  11. #include <asm/arch/ddr_defs.h>
  12. #include <asm/arch/hardware.h>
  13. #include <asm/arch/clock.h>
  14. #include <asm/arch/sys_proto.h>
  15. #include <asm/io.h>
  16. #include <asm/emif.h>
  17. /*********************************************************************
  18. * Init DDR3 on TI816X EVM
  19. *********************************************************************/
  20. static void ddr_init_settings(const struct cmd_control *ctrl, int emif)
  21. {
  22. /*
  23. * setup use_rank_delays to 1. This is only necessary when
  24. * multiple ranks are in use. Though the EVM does not have
  25. * multiple ranks, this is a good value to set.
  26. */
  27. writel(1, DDRPHY_CONFIG_BASE + 0x134); // DATA0_REG_PHY_USE_RANK0_DELAYS
  28. writel(1, DDRPHY_CONFIG_BASE + 0x1d8); // DATA1_REG_PHY_USE_RANK0_DELAYS
  29. writel(1, DDRPHY_CONFIG_BASE + 0x27c); // DATA2_REG_PHY_USE_RANK0_DELAYS
  30. writel(1, DDRPHY_CONFIG_BASE + 0x320); // DATA3_REG_PHY_USE_RANK0_DELAYS
  31. config_cmd_ctrl(ctrl, emif);
  32. /* for ddr3 this needs to be set to 1 */
  33. writel(0x1, DDRPHY_CONFIG_BASE + 0x0F8); /* init mode */
  34. writel(0x1, DDRPHY_CONFIG_BASE + 0x104);
  35. writel(0x1, DDRPHY_CONFIG_BASE + 0x19C);
  36. writel(0x1, DDRPHY_CONFIG_BASE + 0x1A8);
  37. writel(0x1, DDRPHY_CONFIG_BASE + 0x240);
  38. writel(0x1, DDRPHY_CONFIG_BASE + 0x24C);
  39. writel(0x1, DDRPHY_CONFIG_BASE + 0x2E4);
  40. writel(0x1, DDRPHY_CONFIG_BASE + 0x2F0);
  41. /*
  42. * This represents the initial value for the leveling process. The
  43. * value is a ratio - so 0x100 represents one cycle. The real delay
  44. * is determined through the leveling process.
  45. *
  46. * During the leveling process, 0x20 is subtracted from the value, so
  47. * we have added that to the value we want to set. We also set the
  48. * values such that byte3 completes leveling after byte2 and byte1
  49. * after byte0.
  50. */
  51. writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x0F0); /* data0 writelvl init ratio */
  52. writel(0x0, DDRPHY_CONFIG_BASE + 0x0F4); /* */
  53. writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x194); /* data1 writelvl init ratio */
  54. writel(0x0, DDRPHY_CONFIG_BASE + 0x198); /* */
  55. writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x238); /* data2 writelvl init ratio */
  56. writel(0x0, DDRPHY_CONFIG_BASE + 0x23c); /* */
  57. writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x2dc); /* data3 writelvl init ratio */
  58. writel(0x0, DDRPHY_CONFIG_BASE + 0x2e0); /* */
  59. writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x0FC); /* data0 gatelvl init ratio */
  60. writel(0x0, DDRPHY_CONFIG_BASE + 0x100);
  61. writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x1A0); /* data1 gatelvl init ratio */
  62. writel(0x0, DDRPHY_CONFIG_BASE + 0x1A4);
  63. writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x244); /* data2 gatelvl init ratio */
  64. writel(0x0, DDRPHY_CONFIG_BASE + 0x248);
  65. writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x2E8); /* data3 gatelvl init ratio */
  66. writel(0x0, DDRPHY_CONFIG_BASE + 0x2EC);
  67. writel(0x5, DDRPHY_CONFIG_BASE + 0x00C); /* cmd0 io config - output impedance of pad */
  68. writel(0x5, DDRPHY_CONFIG_BASE + 0x010); /* cmd0 io clk config - output impedance of pad */
  69. writel(0x5, DDRPHY_CONFIG_BASE + 0x040); /* cmd1 io config - output impedance of pad */
  70. writel(0x5, DDRPHY_CONFIG_BASE + 0x044); /* cmd1 io clk config - output impedance of pad */
  71. writel(0x5, DDRPHY_CONFIG_BASE + 0x074); /* cmd2 io config - output impedance of pad */
  72. writel(0x5, DDRPHY_CONFIG_BASE + 0x078); /* cmd2 io clk config - output impedance of pad */
  73. writel(0x4, DDRPHY_CONFIG_BASE + 0x0A8); /* data0 io config - output impedance of pad */
  74. writel(0x4, DDRPHY_CONFIG_BASE + 0x0AC); /* data0 io clk config - output impedance of pad */
  75. writel(0x4, DDRPHY_CONFIG_BASE + 0x14C); /* data1 io config - output impedance of pa */
  76. writel(0x4, DDRPHY_CONFIG_BASE + 0x150); /* data1 io clk config - output impedance of pad */
  77. writel(0x4, DDRPHY_CONFIG_BASE + 0x1F0); /* data2 io config - output impedance of pa */
  78. writel(0x4, DDRPHY_CONFIG_BASE + 0x1F4); /* data2 io clk config - output impedance of pad */
  79. writel(0x4, DDRPHY_CONFIG_BASE + 0x294); /* data3 io config - output impedance of pa */
  80. writel(0x4, DDRPHY_CONFIG_BASE + 0x298); /* data3 io clk config - output impedance of pad */
  81. }
  82. static void ddr3_sw_levelling(const struct ddr_data *data, int emif)
  83. {
  84. /* Set the correct value to DDR_VTP_CTRL_0 */
  85. writel(0x6, (DDRPHY_CONFIG_BASE + 0x358));
  86. writel(data->datafwsratio0, (DDRPHY_CONFIG_BASE + 0x108));
  87. writel(data->datafwsratio0, (DDRPHY_CONFIG_BASE + 0x1AC));
  88. writel(data->datafwsratio0, (DDRPHY_CONFIG_BASE + 0x250));
  89. writel(data->datafwsratio0, (DDRPHY_CONFIG_BASE + 0x2F4));
  90. writel(data->datawdsratio0, (DDRPHY_CONFIG_BASE + 0x0DC));
  91. writel(data->datawdsratio0, (DDRPHY_CONFIG_BASE + 0x180));
  92. writel(data->datawdsratio0, (DDRPHY_CONFIG_BASE + 0x224));
  93. writel(data->datawdsratio0, (DDRPHY_CONFIG_BASE + 0x2C8));
  94. writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x120));
  95. writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x1C4));
  96. writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x268));
  97. writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x30C));
  98. writel(data->datardsratio0, (DDRPHY_CONFIG_BASE + 0x0C8));
  99. writel(data->datardsratio0, (DDRPHY_CONFIG_BASE + 0x16C));
  100. writel(data->datardsratio0, (DDRPHY_CONFIG_BASE + 0x210));
  101. writel(data->datardsratio0, (DDRPHY_CONFIG_BASE + 0x2B4));
  102. }
  103. static struct dmm_lisa_map_regs *hw_lisa_map_regs =
  104. (struct dmm_lisa_map_regs *)DMM_BASE;
  105. #define DMM_PAT_BASE_ADDR (DMM_BASE + 0x420)
  106. void config_dmm(const struct dmm_lisa_map_regs *regs)
  107. {
  108. writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
  109. writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
  110. writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
  111. writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
  112. writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3);
  113. writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2);
  114. writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1);
  115. writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0);
  116. /* Enable Tiled Access */
  117. writel(0x80000000, DMM_PAT_BASE_ADDR);
  118. }
  119. void config_ddr(const struct ddr_data *data, const struct cmd_control *ctrl,
  120. const struct emif_regs *regs,
  121. const struct dmm_lisa_map_regs *lisa_regs, int nrs)
  122. {
  123. int i;
  124. enable_emif_clocks();
  125. for (i = 0; i < nrs; i++)
  126. ddr_init_settings(ctrl, i);
  127. enable_dmm_clocks();
  128. /* Program the DMM to for non-interleaved configuration */
  129. config_dmm(lisa_regs);
  130. /* Program EMIF CFG Registers */
  131. for (i = 0; i < nrs; i++) {
  132. set_sdram_timings(regs, i);
  133. config_sdram(regs, i);
  134. }
  135. udelay(1000);
  136. for (i = 0; i < nrs; i++)
  137. ddr3_sw_levelling(data, i);
  138. udelay(50000); /* Some delay needed */
  139. }