board.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. *
  4. * Common board functions for OMAP3 based boards.
  5. *
  6. * (C) Copyright 2004-2008
  7. * Texas Instruments, <www.ti.com>
  8. *
  9. * Author :
  10. * Sunil Kumar <sunilsaini05@gmail.com>
  11. * Shashi Ranjan <shashiranjanmca05@gmail.com>
  12. *
  13. * Derived from Beagle Board and 3430 SDP code by
  14. * Richard Woodruff <r-woodruff2@ti.com>
  15. * Syed Mohammed Khasim <khasim@ti.com>
  16. *
  17. */
  18. #include <common.h>
  19. #include <dm.h>
  20. #include <spl.h>
  21. #include <asm/io.h>
  22. #include <asm/arch/sys_proto.h>
  23. #include <asm/arch/mem.h>
  24. #include <asm/cache.h>
  25. #include <asm/armv7.h>
  26. #include <asm/gpio.h>
  27. #include <asm/omap_common.h>
  28. #include <linux/compiler.h>
  29. /* Declarations */
  30. extern omap3_sysinfo sysinfo;
  31. #ifndef CONFIG_SYS_L2CACHE_OFF
  32. static void omap3_invalidate_l2_cache_secure(void);
  33. #endif
  34. #ifdef CONFIG_DM_GPIO
  35. static const struct omap_gpio_platdata omap34xx_gpio[] = {
  36. { 0, OMAP34XX_GPIO1_BASE },
  37. { 1, OMAP34XX_GPIO2_BASE },
  38. { 2, OMAP34XX_GPIO3_BASE },
  39. { 3, OMAP34XX_GPIO4_BASE },
  40. { 4, OMAP34XX_GPIO5_BASE },
  41. { 5, OMAP34XX_GPIO6_BASE },
  42. };
  43. U_BOOT_DEVICES(omap34xx_gpios) = {
  44. { "gpio_omap", &omap34xx_gpio[0] },
  45. { "gpio_omap", &omap34xx_gpio[1] },
  46. { "gpio_omap", &omap34xx_gpio[2] },
  47. { "gpio_omap", &omap34xx_gpio[3] },
  48. { "gpio_omap", &omap34xx_gpio[4] },
  49. { "gpio_omap", &omap34xx_gpio[5] },
  50. };
  51. #else
  52. static const struct gpio_bank gpio_bank_34xx[6] = {
  53. { (void *)OMAP34XX_GPIO1_BASE },
  54. { (void *)OMAP34XX_GPIO2_BASE },
  55. { (void *)OMAP34XX_GPIO3_BASE },
  56. { (void *)OMAP34XX_GPIO4_BASE },
  57. { (void *)OMAP34XX_GPIO5_BASE },
  58. { (void *)OMAP34XX_GPIO6_BASE },
  59. };
  60. const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
  61. #endif
  62. /******************************************************************************
  63. * Routine: secure_unlock
  64. * Description: Setup security registers for access
  65. * (GP Device only)
  66. *****************************************************************************/
  67. void secure_unlock_mem(void)
  68. {
  69. struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM;
  70. struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM;
  71. struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM;
  72. struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM;
  73. struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE;
  74. /* Protection Module Register Target APE (PM_RT) */
  75. writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
  76. writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
  77. writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
  78. writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);
  79. writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
  80. writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
  81. writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);
  82. writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
  83. writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
  84. writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
  85. writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);
  86. /* IVA Changes */
  87. writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
  88. writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
  89. writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);
  90. /* SDRC region 0 public */
  91. writel(UNLOCK_1, &sms_base->rg_att0);
  92. }
  93. /******************************************************************************
  94. * Routine: secureworld_exit()
  95. * Description: If chip is EMU and boot type is external
  96. * configure secure registers and exit secure world
  97. * general use.
  98. *****************************************************************************/
  99. void secureworld_exit(void)
  100. {
  101. unsigned long i;
  102. /* configure non-secure access control register */
  103. __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
  104. /* enabling co-processor CP10 and CP11 accesses in NS world */
  105. __asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
  106. /*
  107. * allow allocation of locked TLBs and L2 lines in NS world
  108. * allow use of PLE registers in NS world also
  109. */
  110. __asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
  111. __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));
  112. /* Enable ASA in ACR register */
  113. __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
  114. __asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
  115. __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
  116. /* Exiting secure world */
  117. __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
  118. __asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
  119. __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
  120. }
  121. /******************************************************************************
  122. * Routine: try_unlock_sram()
  123. * Description: If chip is GP/EMU(special) type, unlock the SRAM for
  124. * general use.
  125. *****************************************************************************/
  126. void try_unlock_memory(void)
  127. {
  128. int mode;
  129. int in_sdram = is_running_in_sdram();
  130. /*
  131. * if GP device unlock device SRAM for general use
  132. * secure code breaks for Secure/Emulation device - HS/E/T
  133. */
  134. mode = get_device_type();
  135. if (mode == GP_DEVICE)
  136. secure_unlock_mem();
  137. /*
  138. * If device is EMU and boot is XIP external booting
  139. * Unlock firewalls and disable L2 and put chip
  140. * out of secure world
  141. *
  142. * Assuming memories are unlocked by the demon who put us in SDRAM
  143. */
  144. if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
  145. && (!in_sdram)) {
  146. secure_unlock_mem();
  147. secureworld_exit();
  148. }
  149. return;
  150. }
  151. void early_system_init(void)
  152. {
  153. hw_data_init();
  154. }
  155. /******************************************************************************
  156. * Routine: s_init
  157. * Description: Does early system init of muxing and clocks.
  158. * - Called path is with SRAM stack.
  159. *****************************************************************************/
  160. void s_init(void)
  161. {
  162. watchdog_init();
  163. early_system_init();
  164. try_unlock_memory();
  165. #ifndef CONFIG_SYS_L2CACHE_OFF
  166. /* Invalidate L2-cache from secure mode */
  167. omap3_invalidate_l2_cache_secure();
  168. #endif
  169. set_muxconf_regs();
  170. sdelay(100);
  171. prcm_init();
  172. per_clocks_enable();
  173. #ifdef CONFIG_USB_EHCI_OMAP
  174. ehci_clocks_enable();
  175. #endif
  176. }
  177. #ifdef CONFIG_SPL_BUILD
  178. void board_init_f(ulong dummy)
  179. {
  180. early_system_init();
  181. mem_init();
  182. /*
  183. * Save the boot parameters passed from romcode.
  184. * We cannot delay the saving further than this,
  185. * to prevent overwrites.
  186. */
  187. save_omap_boot_params();
  188. }
  189. #endif
  190. /*
  191. * Routine: misc_init_r
  192. * Description: A basic misc_init_r that just displays the die ID
  193. */
  194. int __weak misc_init_r(void)
  195. {
  196. omap_die_id_display();
  197. return 0;
  198. }
  199. /******************************************************************************
  200. * Routine: wait_for_command_complete
  201. * Description: Wait for posting to finish on watchdog
  202. *****************************************************************************/
  203. static void wait_for_command_complete(struct watchdog *wd_base)
  204. {
  205. int pending = 1;
  206. do {
  207. pending = readl(&wd_base->wwps);
  208. } while (pending);
  209. }
  210. /******************************************************************************
  211. * Routine: watchdog_init
  212. * Description: Shut down watch dogs
  213. *****************************************************************************/
  214. void watchdog_init(void)
  215. {
  216. struct watchdog *wd2_base = (struct watchdog *)WD2_BASE;
  217. struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
  218. /*
  219. * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
  220. * either taken care of by ROM (HS/EMU) or not accessible (GP).
  221. * We need to take care of WD2-MPU or take a PRCM reset. WD3
  222. * should not be running and does not generate a PRCM reset.
  223. */
  224. setbits_le32(&prcm_base->fclken_wkup, 0x20);
  225. setbits_le32(&prcm_base->iclken_wkup, 0x20);
  226. wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
  227. writel(WD_UNLOCK1, &wd2_base->wspr);
  228. wait_for_command_complete(wd2_base);
  229. writel(WD_UNLOCK2, &wd2_base->wspr);
  230. }
  231. /******************************************************************************
  232. * Dummy function to handle errors for EABI incompatibility
  233. *****************************************************************************/
  234. void abort(void)
  235. {
  236. }
  237. #if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD)
  238. /******************************************************************************
  239. * OMAP3 specific command to switch between NAND HW and SW ecc
  240. *****************************************************************************/
  241. static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
  242. {
  243. int hw, strength = 1;
  244. if (argc < 2 || argc > 3)
  245. goto usage;
  246. if (strncmp(argv[1], "hw", 2) == 0) {
  247. hw = 1;
  248. if (argc == 3) {
  249. if (strncmp(argv[2], "bch8", 4) == 0)
  250. strength = 8;
  251. else if (strncmp(argv[2], "bch16", 5) == 0)
  252. strength = 16;
  253. else if (strncmp(argv[2], "hamming", 7) != 0)
  254. goto usage;
  255. }
  256. } else if (strncmp(argv[1], "sw", 2) == 0) {
  257. hw = 0;
  258. if (argc == 3) {
  259. if (strncmp(argv[2], "bch8", 4) == 0)
  260. strength = 8;
  261. else if (strncmp(argv[2], "hamming", 7) != 0)
  262. goto usage;
  263. }
  264. } else {
  265. goto usage;
  266. }
  267. return -omap_nand_switch_ecc(hw, strength);
  268. usage:
  269. printf ("Usage: nandecc %s\n", cmdtp->usage);
  270. return 1;
  271. }
  272. U_BOOT_CMD(
  273. nandecc, 3, 1, do_switch_ecc,
  274. "switch OMAP3 NAND ECC calculation algorithm",
  275. "hw [hamming|bch8|bch16] - Switch between NAND hardware 1-bit hamming"
  276. " and 8-bit/16-bit BCH\n"
  277. " ecc calculation (second parameter may"
  278. " be omitted).\n"
  279. "nandecc sw - Switch to NAND software ecc algorithm."
  280. );
  281. #endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */
  282. #ifdef CONFIG_DISPLAY_BOARDINFO
  283. /**
  284. * Print board information
  285. */
  286. int checkboard (void)
  287. {
  288. char *mem_s ;
  289. if (is_mem_sdr())
  290. mem_s = "mSDR";
  291. else
  292. mem_s = "LPDDR";
  293. printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
  294. sysinfo.nand_string);
  295. return 0;
  296. }
  297. #endif /* CONFIG_DISPLAY_BOARDINFO */
  298. static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
  299. {
  300. u32 i, num_params = *parameters;
  301. u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA;
  302. /*
  303. * copy the parameters to an un-cached area to avoid coherency
  304. * issues
  305. */
  306. for (i = 0; i < num_params; i++) {
  307. __raw_writel(*parameters, sram_scratch_space);
  308. parameters++;
  309. sram_scratch_space++;
  310. }
  311. /* Now make the PPA call */
  312. do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
  313. }
  314. void __weak omap3_set_aux_cr_secure(u32 acr)
  315. {
  316. struct emu_hal_params emu_romcode_params;
  317. emu_romcode_params.num_params = 1;
  318. emu_romcode_params.param1 = acr;
  319. omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
  320. (u32 *)&emu_romcode_params);
  321. }
  322. void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
  323. u32 cpu_rev_comb, u32 cpu_variant,
  324. u32 cpu_rev)
  325. {
  326. if (get_device_type() == GP_DEVICE)
  327. omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_L2ACR, l2auxctrl);
  328. /* L2 Cache Auxiliary Control Register is not banked */
  329. }
  330. void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
  331. u32 cpu_variant, u32 cpu_rev)
  332. {
  333. /* Write ACR - affects secure banked bits */
  334. if (get_device_type() == GP_DEVICE)
  335. omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr);
  336. else
  337. omap3_set_aux_cr_secure(acr);
  338. /* Write ACR - affects non-secure banked bits - some erratas need it */
  339. asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
  340. }
  341. #ifndef CONFIG_SYS_L2CACHE_OFF
  342. static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
  343. {
  344. u32 acr;
  345. /* Read ACR */
  346. asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
  347. acr &= ~clear_bits;
  348. acr |= set_bits;
  349. v7_arch_cp15_set_acr(acr, 0, 0, 0, 0);
  350. }
  351. /* Invalidate the entire L2 cache from secure mode */
  352. static void omap3_invalidate_l2_cache_secure(void)
  353. {
  354. if (get_device_type() == GP_DEVICE) {
  355. omap_smc1(OMAP3_GP_ROMCODE_API_L2_INVAL, 0);
  356. } else {
  357. struct emu_hal_params emu_romcode_params;
  358. emu_romcode_params.num_params = 1;
  359. emu_romcode_params.param1 = 0;
  360. omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL,
  361. (u32 *)&emu_romcode_params);
  362. }
  363. }
  364. void v7_outer_cache_enable(void)
  365. {
  366. /*
  367. * Set L2EN
  368. * On some revisions L2EN bit is banked on some revisions it's not
  369. * No harm in setting both banked bits(in fact this is required
  370. * by an erratum)
  371. */
  372. omap3_update_aux_cr(0x2, 0);
  373. }
  374. void omap3_outer_cache_disable(void)
  375. {
  376. /*
  377. * Clear L2EN
  378. * On some revisions L2EN bit is banked on some revisions it's not
  379. * No harm in clearing both banked bits(in fact this is required
  380. * by an erratum)
  381. */
  382. omap3_update_aux_cr(0, 0x2);
  383. }
  384. #endif /* !CONFIG_SYS_L2CACHE_OFF */