rk3399.c 1.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2016 Rockchip Electronics Co., Ltd
  4. */
  5. #include <common.h>
  6. #include <asm/armv8/mmu.h>
  7. #include <asm/io.h>
  8. #include <asm/arch/hardware.h>
  9. DECLARE_GLOBAL_DATA_PTR;
  10. #define GRF_EMMCCORE_CON11 0xff77f02c
  11. static struct mm_region rk3399_mem_map[] = {
  12. {
  13. .virt = 0x0UL,
  14. .phys = 0x0UL,
  15. .size = 0xf8000000UL,
  16. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  17. PTE_BLOCK_INNER_SHARE
  18. }, {
  19. .virt = 0xf8000000UL,
  20. .phys = 0xf8000000UL,
  21. .size = 0x08000000UL,
  22. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  23. PTE_BLOCK_NON_SHARE |
  24. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  25. }, {
  26. /* List terminator */
  27. 0,
  28. }
  29. };
  30. struct mm_region *mem_map = rk3399_mem_map;
  31. int dram_init_banksize(void)
  32. {
  33. size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top);
  34. /* Reserve 0x200000 for ATF bl31 */
  35. gd->bd->bi_dram[0].start = 0x200000;
  36. gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start;
  37. return 0;
  38. }
  39. int arch_cpu_init(void)
  40. {
  41. /* We do some SoC one time setting here. */
  42. /* Emmc clock generator: disable the clock multipilier */
  43. rk_clrreg(GRF_EMMCCORE_CON11, 0x0ff);
  44. return 0;
  45. }