sdram_common.c 2.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <ram.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/sdram_common.h>
  10. #include <dm/uclass-internal.h>
  11. DECLARE_GLOBAL_DATA_PTR;
  12. size_t rockchip_sdram_size(phys_addr_t reg)
  13. {
  14. u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4;
  15. size_t chipsize_mb = 0;
  16. size_t size_mb = 0;
  17. u32 ch;
  18. u32 sys_reg = readl(reg);
  19. u32 ch_num = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT)
  20. & SYS_REG_NUM_CH_MASK);
  21. debug("%s %x %x\n", __func__, (u32)reg, sys_reg);
  22. for (ch = 0; ch < ch_num; ch++) {
  23. rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) &
  24. SYS_REG_RANK_MASK);
  25. col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK);
  26. bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
  27. cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) &
  28. SYS_REG_CS0_ROW_MASK);
  29. cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) &
  30. SYS_REG_CS1_ROW_MASK);
  31. bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) &
  32. SYS_REG_BW_MASK));
  33. row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) &
  34. SYS_REG_ROW_3_4_MASK;
  35. chipsize_mb = (1 << (cs0_row + col + bk + bw - 20));
  36. if (rank > 1)
  37. chipsize_mb += chipsize_mb >> (cs0_row - cs1_row);
  38. if (row_3_4)
  39. chipsize_mb = chipsize_mb * 3 / 4;
  40. size_mb += chipsize_mb;
  41. debug("rank %d col %d bk %d cs0_row %d bw %d row_3_4 %d\n",
  42. rank, col, bk, cs0_row, bw, row_3_4);
  43. }
  44. return (size_t)size_mb << 20;
  45. }
  46. int dram_init(void)
  47. {
  48. struct ram_info ram;
  49. struct udevice *dev;
  50. int ret;
  51. ret = uclass_get_device(UCLASS_RAM, 0, &dev);
  52. if (ret) {
  53. debug("DRAM init failed: %d\n", ret);
  54. return ret;
  55. }
  56. ret = ram_get_info(dev, &ram);
  57. if (ret) {
  58. debug("Cannot get DRAM size: %d\n", ret);
  59. return ret;
  60. }
  61. gd->ram_size = ram.size;
  62. debug("SDRAM base=%lx, size=%lx\n",
  63. (unsigned long)ram.base, (unsigned long)ram.size);
  64. return 0;
  65. }
  66. ulong board_get_usable_ram_top(ulong total_size)
  67. {
  68. unsigned long top = CONFIG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE;
  69. return (gd->ram_top > top) ? top : gd->ram_top;
  70. }