reset_manager_s10.h 3.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0
  2. *
  3. * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
  4. *
  5. */
  6. #ifndef _RESET_MANAGER_S10_
  7. #define _RESET_MANAGER_S10_
  8. void reset_cpu(ulong addr);
  9. void reset_deassert_peripherals_handoff(void);
  10. void socfpga_bridges_reset(int enable);
  11. void socfpga_per_reset(u32 reset, int set);
  12. void socfpga_per_reset_all(void);
  13. struct socfpga_reset_manager {
  14. u32 status;
  15. u32 mpu_rst_stat;
  16. u32 misc_stat;
  17. u32 padding1;
  18. u32 hdsk_en;
  19. u32 hdsk_req;
  20. u32 hdsk_ack;
  21. u32 hdsk_stall;
  22. u32 mpumodrst;
  23. u32 per0modrst;
  24. u32 per1modrst;
  25. u32 brgmodrst;
  26. u32 padding2;
  27. u32 cold_mod_reset;
  28. u32 padding3;
  29. u32 dbg_mod_reset;
  30. u32 tap_mod_reset;
  31. u32 padding4;
  32. u32 padding5;
  33. u32 brg_warm_mask;
  34. u32 padding6[3];
  35. u32 tst_stat;
  36. u32 padding7;
  37. u32 hdsk_timeout;
  38. u32 mpul2flushtimeout;
  39. u32 dbghdsktimeout;
  40. };
  41. #define RSTMGR_MPUMODRST_CORE0 0
  42. #define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00
  43. #define RSTMGR_BRGMODRST_DDRSCH_MASK 0X00000040
  44. /*
  45. * Define a reset identifier, from which a permodrst bank ID
  46. * and reset ID can be extracted using the subsequent macros
  47. * RSTMGR_RESET() and RSTMGR_BANK().
  48. */
  49. #define RSTMGR_BANK_OFFSET 8
  50. #define RSTMGR_BANK_MASK 0x7
  51. #define RSTMGR_RESET_OFFSET 0
  52. #define RSTMGR_RESET_MASK 0x1f
  53. #define RSTMGR_DEFINE(_bank, _offset) \
  54. ((_bank) << RSTMGR_BANK_OFFSET) | ((_offset) << RSTMGR_RESET_OFFSET)
  55. /* Extract reset ID from the reset identifier. */
  56. #define RSTMGR_RESET(_reset) \
  57. (((_reset) >> RSTMGR_RESET_OFFSET) & RSTMGR_RESET_MASK)
  58. /* Extract bank ID from the reset identifier. */
  59. #define RSTMGR_BANK(_reset) \
  60. (((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK)
  61. /*
  62. * SocFPGA Stratix10 reset IDs, bank mapping is as follows:
  63. * 0 ... mpumodrst
  64. * 1 ... per0modrst
  65. * 2 ... per1modrst
  66. * 3 ... brgmodrst
  67. */
  68. #define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0)
  69. #define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1)
  70. #define RSTMGR_EMAC2 RSTMGR_DEFINE(1, 2)
  71. #define RSTMGR_USB0 RSTMGR_DEFINE(1, 3)
  72. #define RSTMGR_USB1 RSTMGR_DEFINE(1, 4)
  73. #define RSTMGR_NAND RSTMGR_DEFINE(1, 5)
  74. #define RSTMGR_SDMMC RSTMGR_DEFINE(1, 7)
  75. #define RSTMGR_EMAC0_OCP RSTMGR_DEFINE(1, 8)
  76. #define RSTMGR_EMAC1_OCP RSTMGR_DEFINE(1, 9)
  77. #define RSTMGR_EMAC2_OCP RSTMGR_DEFINE(1, 10)
  78. #define RSTMGR_USB0_OCP RSTMGR_DEFINE(1, 11)
  79. #define RSTMGR_USB1_OCP RSTMGR_DEFINE(1, 12)
  80. #define RSTMGR_NAND_OCP RSTMGR_DEFINE(1, 13)
  81. #define RSTMGR_SDMMC_OCP RSTMGR_DEFINE(1, 15)
  82. #define RSTMGR_DMA RSTMGR_DEFINE(1, 16)
  83. #define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 17)
  84. #define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 18)
  85. #define RSTMGR_L4WD0 RSTMGR_DEFINE(2, 0)
  86. #define RSTMGR_L4WD1 RSTMGR_DEFINE(2, 1)
  87. #define RSTMGR_L4WD2 RSTMGR_DEFINE(2, 2)
  88. #define RSTMGR_L4WD3 RSTMGR_DEFINE(2, 3)
  89. #define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(2, 4)
  90. #define RSTMGR_I2C0 RSTMGR_DEFINE(2, 8)
  91. #define RSTMGR_I2C1 RSTMGR_DEFINE(2, 9)
  92. #define RSTMGR_I2C2 RSTMGR_DEFINE(2, 10)
  93. #define RSTMGR_I2C3 RSTMGR_DEFINE(2, 11)
  94. #define RSTMGR_I2C4 RSTMGR_DEFINE(2, 12)
  95. #define RSTMGR_UART0 RSTMGR_DEFINE(2, 16)
  96. #define RSTMGR_UART1 RSTMGR_DEFINE(2, 17)
  97. #define RSTMGR_GPIO0 RSTMGR_DEFINE(2, 24)
  98. #define RSTMGR_GPIO1 RSTMGR_DEFINE(2, 25)
  99. #define RSTMGR_SDR RSTMGR_DEFINE(3, 6)
  100. void socfpga_emac_manage_reset(const unsigned int of_reset_id, u32 state);
  101. /* Create a human-readable reference to SoCFPGA reset. */
  102. #define SOCFPGA_RESET(_name) RSTMGR_##_name
  103. #endif /* _RESET_MANAGER_S10_ */