cpu_init.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2007-2011 Freescale Semiconductor, Inc.
  4. *
  5. * (C) Copyright 2003 Motorola Inc.
  6. * Modified by Xianghua Xiao, X.Xiao@motorola.com
  7. *
  8. * (C) Copyright 2000
  9. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  10. */
  11. #include <common.h>
  12. #include <watchdog.h>
  13. #include <asm/processor.h>
  14. #include <ioports.h>
  15. #include <sata.h>
  16. #include <fm_eth.h>
  17. #include <asm/io.h>
  18. #include <asm/cache.h>
  19. #include <asm/mmu.h>
  20. #include <fsl_errata.h>
  21. #include <asm/fsl_law.h>
  22. #include <asm/fsl_serdes.h>
  23. #include <asm/fsl_srio.h>
  24. #ifdef CONFIG_FSL_CORENET
  25. #include <asm/fsl_portals.h>
  26. #include <asm/fsl_liodn.h>
  27. #include <fsl_qbman.h>
  28. #endif
  29. #include <fsl_usb.h>
  30. #include <hwconfig.h>
  31. #include <linux/compiler.h>
  32. #include "mp.h"
  33. #ifdef CONFIG_CHAIN_OF_TRUST
  34. #include <fsl_validate.h>
  35. #endif
  36. #ifdef CONFIG_FSL_CAAM
  37. #include <fsl_sec.h>
  38. #endif
  39. #if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET)
  40. #include <asm/fsl_pamu.h>
  41. #include <fsl_secboot_err.h>
  42. #endif
  43. #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
  44. #include <nand.h>
  45. #include <errno.h>
  46. #endif
  47. #ifndef CONFIG_ARCH_QEMU_E500
  48. #include <fsl_ddr.h>
  49. #endif
  50. #include "../../../../drivers/ata/fsl_sata.h"
  51. #ifdef CONFIG_U_QE
  52. #include <fsl_qe.h>
  53. #endif
  54. #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
  55. /*
  56. * For deriving usb clock from 100MHz sysclk, reference divisor is set
  57. * to a value of 5, which gives an intermediate value 20(100/5). The
  58. * multiplication factor integer is set to 24, which when multiplied to
  59. * above intermediate value provides clock for usb ip.
  60. */
  61. void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy)
  62. {
  63. sys_info_t sysinfo;
  64. get_sys_info(&sysinfo);
  65. if (sysinfo.diff_sysclk == 1) {
  66. clrbits_be32(&usb_phy->pllprg[1],
  67. CONFIG_SYS_FSL_USB_PLLPRG2_MFI);
  68. setbits_be32(&usb_phy->pllprg[1],
  69. CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK |
  70. CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK |
  71. CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN);
  72. }
  73. }
  74. #endif
  75. #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
  76. void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
  77. {
  78. #ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
  79. u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg);
  80. /* Increase Disconnect Threshold by 50mV */
  81. xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
  82. INC_DCNT_THRESHOLD_50MV;
  83. /* Enable programming of USB High speed Disconnect threshold */
  84. xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
  85. out_be32(&usb_phy->port1.xcvrprg, xcvrprg);
  86. xcvrprg = in_be32(&usb_phy->port2.xcvrprg);
  87. /* Increase Disconnect Threshold by 50mV */
  88. xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
  89. INC_DCNT_THRESHOLD_50MV;
  90. /* Enable programming of USB High speed Disconnect threshold */
  91. xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
  92. out_be32(&usb_phy->port2.xcvrprg, xcvrprg);
  93. #else
  94. u32 temp = 0;
  95. u32 status = in_be32(&usb_phy->status1);
  96. u32 squelch_prog_rd_0_2 =
  97. (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0)
  98. & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
  99. u32 squelch_prog_rd_3_5 =
  100. (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3)
  101. & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
  102. setbits_be32(&usb_phy->config1,
  103. CONFIG_SYS_FSL_USB_HS_DISCNCT_INC);
  104. setbits_be32(&usb_phy->config2,
  105. CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
  106. temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
  107. out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
  108. temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
  109. out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
  110. #endif
  111. }
  112. #endif
  113. #if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
  114. extern qe_iop_conf_t qe_iop_conf_tab[];
  115. extern void qe_config_iopin(u8 port, u8 pin, int dir,
  116. int open_drain, int assign);
  117. extern void qe_init(uint qe_base);
  118. extern void qe_reset(void);
  119. static void config_qe_ioports(void)
  120. {
  121. u8 port, pin;
  122. int dir, open_drain, assign;
  123. int i;
  124. for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
  125. port = qe_iop_conf_tab[i].port;
  126. pin = qe_iop_conf_tab[i].pin;
  127. dir = qe_iop_conf_tab[i].dir;
  128. open_drain = qe_iop_conf_tab[i].open_drain;
  129. assign = qe_iop_conf_tab[i].assign;
  130. qe_config_iopin(port, pin, dir, open_drain, assign);
  131. }
  132. }
  133. #endif
  134. #ifdef CONFIG_CPM2
  135. void config_8560_ioports (volatile ccsr_cpm_t * cpm)
  136. {
  137. int portnum;
  138. for (portnum = 0; portnum < 4; portnum++) {
  139. uint pmsk = 0,
  140. ppar = 0,
  141. psor = 0,
  142. pdir = 0,
  143. podr = 0,
  144. pdat = 0;
  145. iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
  146. iop_conf_t *eiopc = iopc + 32;
  147. uint msk = 1;
  148. /*
  149. * NOTE:
  150. * index 0 refers to pin 31,
  151. * index 31 refers to pin 0
  152. */
  153. while (iopc < eiopc) {
  154. if (iopc->conf) {
  155. pmsk |= msk;
  156. if (iopc->ppar)
  157. ppar |= msk;
  158. if (iopc->psor)
  159. psor |= msk;
  160. if (iopc->pdir)
  161. pdir |= msk;
  162. if (iopc->podr)
  163. podr |= msk;
  164. if (iopc->pdat)
  165. pdat |= msk;
  166. }
  167. msk <<= 1;
  168. iopc++;
  169. }
  170. if (pmsk != 0) {
  171. volatile ioport_t *iop = ioport_addr (cpm, portnum);
  172. uint tpmsk = ~pmsk;
  173. /*
  174. * the (somewhat confused) paragraph at the
  175. * bottom of page 35-5 warns that there might
  176. * be "unknown behaviour" when programming
  177. * PSORx and PDIRx, if PPARx = 1, so I
  178. * decided this meant I had to disable the
  179. * dedicated function first, and enable it
  180. * last.
  181. */
  182. iop->ppar &= tpmsk;
  183. iop->psor = (iop->psor & tpmsk) | psor;
  184. iop->podr = (iop->podr & tpmsk) | podr;
  185. iop->pdat = (iop->pdat & tpmsk) | pdat;
  186. iop->pdir = (iop->pdir & tpmsk) | pdir;
  187. iop->ppar |= ppar;
  188. }
  189. }
  190. }
  191. #endif
  192. #ifdef CONFIG_SYS_FSL_CPC
  193. #if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F)
  194. void disable_cpc_sram(void)
  195. {
  196. int i;
  197. cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
  198. for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
  199. if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
  200. /* find and disable LAW of SRAM */
  201. struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
  202. if (law.index == -1) {
  203. printf("\nFatal error happened\n");
  204. return;
  205. }
  206. disable_law(law.index);
  207. clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
  208. out_be32(&cpc->cpccsr0, 0);
  209. out_be32(&cpc->cpcsrcr0, 0);
  210. }
  211. }
  212. }
  213. #endif
  214. #if defined(T1040_TDM_QUIRK_CCSR_BASE)
  215. #ifdef CONFIG_POST
  216. #error POST memory test cannot be enabled with TDM
  217. #endif
  218. static void enable_tdm_law(void)
  219. {
  220. int ret;
  221. char buffer[HWCONFIG_BUFFER_SIZE] = {0};
  222. int tdm_hwconfig_enabled = 0;
  223. /*
  224. * Extract hwconfig from environment since environment
  225. * is not setup properly yet. Search for tdm entry in
  226. * hwconfig.
  227. */
  228. ret = env_get_f("hwconfig", buffer, sizeof(buffer));
  229. if (ret > 0) {
  230. tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
  231. /* If tdm is defined in hwconfig, set law for tdm workaround */
  232. if (tdm_hwconfig_enabled)
  233. set_next_law(T1040_TDM_QUIRK_CCSR_BASE, LAW_SIZE_16M,
  234. LAW_TRGT_IF_CCSR);
  235. }
  236. }
  237. #endif
  238. void enable_cpc(void)
  239. {
  240. int i;
  241. int ret;
  242. u32 size = 0;
  243. u32 cpccfg0;
  244. char buffer[HWCONFIG_BUFFER_SIZE];
  245. char cpc_subarg[16];
  246. bool have_hwconfig = false;
  247. int cpc_args = 0;
  248. cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
  249. /* Extract hwconfig from environment */
  250. ret = env_get_f("hwconfig", buffer, sizeof(buffer));
  251. if (ret > 0) {
  252. /*
  253. * If "en_cpc" is not defined in hwconfig then by default all
  254. * cpcs are enable. If this config is defined then individual
  255. * cpcs which have to be enabled should also be defined.
  256. * e.g en_cpc:cpc1,cpc2;
  257. */
  258. if (hwconfig_f("en_cpc", buffer))
  259. have_hwconfig = true;
  260. }
  261. for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
  262. if (have_hwconfig) {
  263. sprintf(cpc_subarg, "cpc%u", i + 1);
  264. cpc_args = hwconfig_sub_f("en_cpc", cpc_subarg, buffer);
  265. if (cpc_args == 0)
  266. continue;
  267. }
  268. cpccfg0 = in_be32(&cpc->cpccfg0);
  269. size += CPC_CFG0_SZ_K(cpccfg0);
  270. #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
  271. setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
  272. #endif
  273. #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
  274. setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
  275. #endif
  276. #ifdef CONFIG_SYS_FSL_ERRATUM_A006593
  277. setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21));
  278. #endif
  279. #ifdef CONFIG_SYS_FSL_ERRATUM_A006379
  280. if (has_erratum_a006379()) {
  281. setbits_be32(&cpc->cpchdbcr0,
  282. CPC_HDBCR0_SPLRU_LEVEL_EN);
  283. }
  284. #endif
  285. out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
  286. /* Read back to sync write */
  287. in_be32(&cpc->cpccsr0);
  288. }
  289. puts("Corenet Platform Cache: ");
  290. print_size(size * 1024, " enabled\n");
  291. }
  292. static void invalidate_cpc(void)
  293. {
  294. int i;
  295. cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
  296. for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
  297. /* skip CPC when it used as all SRAM */
  298. if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
  299. continue;
  300. /* Flash invalidate the CPC and clear all the locks */
  301. out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
  302. while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
  303. ;
  304. }
  305. }
  306. #else
  307. #define enable_cpc()
  308. #define invalidate_cpc()
  309. #define disable_cpc_sram()
  310. #endif /* CONFIG_SYS_FSL_CPC */
  311. /*
  312. * Breathe some life into the CPU...
  313. *
  314. * Set up the memory map
  315. * initialize a bunch of registers
  316. */
  317. #ifdef CONFIG_FSL_CORENET
  318. static void corenet_tb_init(void)
  319. {
  320. volatile ccsr_rcpm_t *rcpm =
  321. (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
  322. volatile ccsr_pic_t *pic =
  323. (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
  324. u32 whoami = in_be32(&pic->whoami);
  325. /* Enable the timebase register for this core */
  326. out_be32(&rcpm->ctbenrl, (1 << whoami));
  327. }
  328. #endif
  329. #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
  330. void fsl_erratum_a007212_workaround(void)
  331. {
  332. ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  333. u32 ddr_pll_ratio;
  334. u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
  335. u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28);
  336. u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80);
  337. #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
  338. u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40);
  339. u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48);
  340. #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
  341. u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60);
  342. u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68);
  343. #endif
  344. #endif
  345. /*
  346. * Even this workaround applies to selected version of SoCs, it is
  347. * safe to apply to all versions, with the limitation of odd ratios.
  348. * If RCW has disabled DDR PLL, we have to apply this workaround,
  349. * otherwise DDR will not work.
  350. */
  351. ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
  352. FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) &
  353. FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
  354. /* check if RCW sets ratio to 0, required by this workaround */
  355. if (ddr_pll_ratio != 0)
  356. return;
  357. ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
  358. FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
  359. FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
  360. /* check if reserved bits have the desired ratio */
  361. if (ddr_pll_ratio == 0) {
  362. printf("Error: Unknown DDR PLL ratio!\n");
  363. return;
  364. }
  365. ddr_pll_ratio >>= 1;
  366. setbits_be32(plldadcr1, 0x02000001);
  367. #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
  368. setbits_be32(plldadcr2, 0x02000001);
  369. #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
  370. setbits_be32(plldadcr3, 0x02000001);
  371. #endif
  372. #endif
  373. setbits_be32(dpdovrcr4, 0xe0000000);
  374. out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1));
  375. #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
  376. out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1));
  377. #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
  378. out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1));
  379. #endif
  380. #endif
  381. udelay(100);
  382. clrbits_be32(plldadcr1, 0x02000001);
  383. #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
  384. clrbits_be32(plldadcr2, 0x02000001);
  385. #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
  386. clrbits_be32(plldadcr3, 0x02000001);
  387. #endif
  388. #endif
  389. clrbits_be32(dpdovrcr4, 0xe0000000);
  390. }
  391. #endif
  392. ulong cpu_init_f(void)
  393. {
  394. extern void m8560_cpm_reset (void);
  395. #ifdef CONFIG_SYS_DCSRBAR_PHYS
  396. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  397. #endif
  398. #if defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SYS_RAMBOOT)
  399. struct law_entry law;
  400. #endif
  401. #ifdef CONFIG_ARCH_MPC8548
  402. ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
  403. uint svr = get_svr();
  404. /*
  405. * CPU2 errata workaround: A core hang possible while executing
  406. * a msync instruction and a snoopable transaction from an I/O
  407. * master tagged to make quick forward progress is present.
  408. * Fixed in silicon rev 2.1.
  409. */
  410. if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
  411. out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
  412. #endif
  413. disable_tlb(14);
  414. disable_tlb(15);
  415. #if defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SYS_RAMBOOT)
  416. /* Disable the LAW created for NOR flash by the PBI commands */
  417. law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
  418. if (law.index != -1)
  419. disable_law(law.index);
  420. #if defined(CONFIG_SYS_CPC_REINIT_F)
  421. disable_cpc_sram();
  422. #endif
  423. #endif
  424. #ifdef CONFIG_CPM2
  425. config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
  426. #endif
  427. init_early_memctl_regs();
  428. #if defined(CONFIG_CPM2)
  429. m8560_cpm_reset();
  430. #endif
  431. #if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
  432. /* Config QE ioports */
  433. config_qe_ioports();
  434. #endif
  435. #if defined(CONFIG_FSL_DMA)
  436. dma_init();
  437. #endif
  438. #ifdef CONFIG_FSL_CORENET
  439. corenet_tb_init();
  440. #endif
  441. init_used_tlb_cams();
  442. /* Invalidate the CPC before DDR gets enabled */
  443. invalidate_cpc();
  444. #ifdef CONFIG_SYS_DCSRBAR_PHYS
  445. /* set DCSRCR so that DCSR space is 1G */
  446. setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
  447. in_be32(&gur->dcsrcr);
  448. #endif
  449. #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
  450. fsl_erratum_a007212_workaround();
  451. #endif
  452. return 0;
  453. }
  454. /* Implement a dummy function for those platforms w/o SERDES */
  455. static void __fsl_serdes__init(void)
  456. {
  457. return ;
  458. }
  459. __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
  460. #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
  461. int enable_cluster_l2(void)
  462. {
  463. int i = 0;
  464. u32 cluster, svr = get_svr();
  465. ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  466. struct ccsr_cluster_l2 __iomem *l2cache;
  467. /* only the L2 of first cluster should be enabled as expected on T4080,
  468. * but there is no EOC in the first cluster as HW sake, so return here
  469. * to skip enabling L2 cache of the 2nd cluster.
  470. */
  471. if (SVR_SOC_VER(svr) == SVR_T4080)
  472. return 0;
  473. cluster = in_be32(&gur->tp_cluster[i].lower);
  474. if (cluster & TP_CLUSTER_EOC)
  475. return 0;
  476. /* The first cache has already been set up, so skip it */
  477. i++;
  478. /* Look through the remaining clusters, and set up their caches */
  479. do {
  480. int j, cluster_valid = 0;
  481. l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
  482. cluster = in_be32(&gur->tp_cluster[i].lower);
  483. /* check that at least one core/accel is enabled in cluster */
  484. for (j = 0; j < 4; j++) {
  485. u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK;
  486. u32 type = in_be32(&gur->tp_ityp[idx]);
  487. if ((type & TP_ITYP_AV) &&
  488. TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC)
  489. cluster_valid = 1;
  490. }
  491. if (cluster_valid) {
  492. /* set stash ID to (cluster) * 2 + 32 + 1 */
  493. clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
  494. printf("enable l2 for cluster %d %p\n", i, l2cache);
  495. out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
  496. while ((in_be32(&l2cache->l2csr0)
  497. & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
  498. ;
  499. out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE);
  500. }
  501. i++;
  502. } while (!(cluster & TP_CLUSTER_EOC));
  503. return 0;
  504. }
  505. #endif
  506. /*
  507. * Initialize L2 as cache.
  508. */
  509. int l2cache_init(void)
  510. {
  511. __maybe_unused u32 svr = get_svr();
  512. #ifdef CONFIG_L2_CACHE
  513. ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
  514. #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
  515. struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
  516. #endif
  517. puts ("L2: ");
  518. #if defined(CONFIG_L2_CACHE)
  519. volatile uint cache_ctl;
  520. uint ver;
  521. u32 l2siz_field;
  522. ver = SVR_SOC_VER(svr);
  523. asm("msync;isync");
  524. cache_ctl = l2cache->l2ctl;
  525. #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
  526. if (cache_ctl & MPC85xx_L2CTL_L2E) {
  527. /* Clear L2 SRAM memory-mapped base address */
  528. out_be32(&l2cache->l2srbar0, 0x0);
  529. out_be32(&l2cache->l2srbar1, 0x0);
  530. /* set MBECCDIS=0, SBECCDIS=0 */
  531. clrbits_be32(&l2cache->l2errdis,
  532. (MPC85xx_L2ERRDIS_MBECC |
  533. MPC85xx_L2ERRDIS_SBECC));
  534. /* set L2E=0, L2SRAM=0 */
  535. clrbits_be32(&l2cache->l2ctl,
  536. (MPC85xx_L2CTL_L2E |
  537. MPC85xx_L2CTL_L2SRAM_ENTIRE));
  538. }
  539. #endif
  540. l2siz_field = (cache_ctl >> 28) & 0x3;
  541. switch (l2siz_field) {
  542. case 0x0:
  543. printf(" unknown size (0x%08x)\n", cache_ctl);
  544. return -1;
  545. break;
  546. case 0x1:
  547. if (ver == SVR_8540 || ver == SVR_8560 ||
  548. ver == SVR_8541 || ver == SVR_8555) {
  549. puts("128 KiB ");
  550. /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */
  551. cache_ctl = 0xc4000000;
  552. } else {
  553. puts("256 KiB ");
  554. cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
  555. }
  556. break;
  557. case 0x2:
  558. if (ver == SVR_8540 || ver == SVR_8560 ||
  559. ver == SVR_8541 || ver == SVR_8555) {
  560. puts("256 KiB ");
  561. /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */
  562. cache_ctl = 0xc8000000;
  563. } else {
  564. puts("512 KiB ");
  565. /* set L2E=1, L2I=1, & L2SRAM=0 */
  566. cache_ctl = 0xc0000000;
  567. }
  568. break;
  569. case 0x3:
  570. puts("1024 KiB ");
  571. /* set L2E=1, L2I=1, & L2SRAM=0 */
  572. cache_ctl = 0xc0000000;
  573. break;
  574. }
  575. if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
  576. puts("already enabled");
  577. #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
  578. u32 l2srbar = l2cache->l2srbar0;
  579. if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
  580. && l2srbar >= CONFIG_SYS_FLASH_BASE) {
  581. l2srbar = CONFIG_SYS_INIT_L2_ADDR;
  582. l2cache->l2srbar0 = l2srbar;
  583. printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
  584. }
  585. #endif /* CONFIG_SYS_INIT_L2_ADDR */
  586. puts("\n");
  587. } else {
  588. asm("msync;isync");
  589. l2cache->l2ctl = cache_ctl; /* invalidate & enable */
  590. asm("msync;isync");
  591. puts("enabled\n");
  592. }
  593. #elif defined(CONFIG_BACKSIDE_L2_CACHE)
  594. if (SVR_SOC_VER(svr) == SVR_P2040) {
  595. puts("N/A\n");
  596. goto skip_l2;
  597. }
  598. u32 l2cfg0 = mfspr(SPRN_L2CFG0);
  599. /* invalidate the L2 cache */
  600. mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
  601. while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
  602. ;
  603. #ifdef CONFIG_SYS_CACHE_STASHING
  604. /* set stash id to (coreID) * 2 + 32 + L2 (1) */
  605. mtspr(SPRN_L2CSR1, (32 + 1));
  606. #endif
  607. /* enable the cache */
  608. mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
  609. if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
  610. while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
  611. ;
  612. print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n");
  613. }
  614. skip_l2:
  615. #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
  616. if (l2cache->l2csr0 & L2CSR0_L2E)
  617. print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024,
  618. " enabled\n");
  619. enable_cluster_l2();
  620. #else
  621. puts("disabled\n");
  622. #endif
  623. return 0;
  624. }
  625. /*
  626. *
  627. * The newer 8548, etc, parts have twice as much cache, but
  628. * use the same bit-encoding as the older 8555, etc, parts.
  629. *
  630. */
  631. int cpu_init_r(void)
  632. {
  633. __maybe_unused u32 svr = get_svr();
  634. #ifdef CONFIG_SYS_LBC_LCRR
  635. fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
  636. #endif
  637. #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
  638. extern int spin_table_compat;
  639. const char *spin;
  640. #endif
  641. #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
  642. ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
  643. #endif
  644. #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
  645. defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
  646. /*
  647. * CPU22 and NMG_CPU_A011 share the same workaround.
  648. * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
  649. * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
  650. * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
  651. * fixed in 2.0. NMG_CPU_A011 is activated by default and can
  652. * be disabled by hwconfig with syntax:
  653. *
  654. * fsl_cpu_a011:disable
  655. */
  656. extern int enable_cpu_a011_workaround;
  657. #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
  658. enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
  659. #else
  660. char buffer[HWCONFIG_BUFFER_SIZE];
  661. char *buf = NULL;
  662. int n, res;
  663. n = env_get_f("hwconfig", buffer, sizeof(buffer));
  664. if (n > 0)
  665. buf = buffer;
  666. res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
  667. if (res > 0) {
  668. enable_cpu_a011_workaround = 0;
  669. } else {
  670. if (n >= HWCONFIG_BUFFER_SIZE) {
  671. printf("fsl_cpu_a011 was not found. hwconfig variable "
  672. "may be too long\n");
  673. }
  674. enable_cpu_a011_workaround =
  675. (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
  676. (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
  677. }
  678. #endif
  679. if (enable_cpu_a011_workaround) {
  680. flush_dcache();
  681. mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
  682. sync();
  683. }
  684. #endif
  685. #ifdef CONFIG_SYS_FSL_ERRATUM_A007907
  686. flush_dcache();
  687. mtspr(L1CSR2, (mfspr(L1CSR2) & ~L1CSR2_DCSTASHID));
  688. sync();
  689. #endif
  690. #ifdef CONFIG_SYS_FSL_ERRATUM_A005812
  691. /*
  692. * A-005812 workaround sets bit 32 of SPR 976 for SoCs running
  693. * in write shadow mode. Checking DCWS before setting SPR 976.
  694. */
  695. if (mfspr(L1CSR2) & L1CSR2_DCWS)
  696. mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000));
  697. #endif
  698. #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
  699. spin = env_get("spin_table_compat");
  700. if (spin && (*spin == 'n'))
  701. spin_table_compat = 0;
  702. else
  703. spin_table_compat = 1;
  704. #endif
  705. #ifdef CONFIG_FSL_CORENET
  706. set_liodns();
  707. #ifdef CONFIG_SYS_DPAA_QBMAN
  708. setup_qbman_portals();
  709. #endif
  710. #endif
  711. l2cache_init();
  712. #if defined(CONFIG_RAMBOOT_PBL)
  713. disable_cpc_sram();
  714. #endif
  715. enable_cpc();
  716. #if defined(T1040_TDM_QUIRK_CCSR_BASE)
  717. enable_tdm_law();
  718. #endif
  719. #ifndef CONFIG_SYS_FSL_NO_SERDES
  720. /* needs to be in ram since code uses global static vars */
  721. fsl_serdes_init();
  722. #endif
  723. #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
  724. #define MCFGR_AXIPIPE 0x000000f0
  725. if (IS_SVR_REV(svr, 1, 0))
  726. sec_clrbits32(&sec->mcfgr, MCFGR_AXIPIPE);
  727. #endif
  728. #ifdef CONFIG_SYS_FSL_ERRATUM_A005871
  729. if (IS_SVR_REV(svr, 1, 0)) {
  730. int i;
  731. __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c;
  732. for (i = 0; i < 12; i++) {
  733. p += i + (i > 5 ? 11 : 0);
  734. out_be32(p, 0x2);
  735. }
  736. p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108;
  737. out_be32(p, 0x34);
  738. }
  739. #endif
  740. #ifdef CONFIG_SYS_SRIO
  741. srio_init();
  742. #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
  743. char *s = env_get("bootmaster");
  744. if (s) {
  745. if (!strcmp(s, "SRIO1")) {
  746. srio_boot_master(1);
  747. srio_boot_master_release_slave(1);
  748. }
  749. if (!strcmp(s, "SRIO2")) {
  750. srio_boot_master(2);
  751. srio_boot_master_release_slave(2);
  752. }
  753. }
  754. #endif
  755. #endif
  756. #if defined(CONFIG_MP)
  757. setup_mp();
  758. #endif
  759. #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
  760. {
  761. if (SVR_MAJ(svr) < 3) {
  762. void *p;
  763. p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
  764. setbits_be32(p, 1 << (31 - 14));
  765. }
  766. }
  767. #endif
  768. #ifdef CONFIG_SYS_LBC_LCRR
  769. /*
  770. * Modify the CLKDIV field of LCRR register to improve the writing
  771. * speed for NOR flash.
  772. */
  773. clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
  774. __raw_readl(&lbc->lcrr);
  775. isync();
  776. #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
  777. udelay(100);
  778. #endif
  779. #endif
  780. #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
  781. {
  782. struct ccsr_usb_phy __iomem *usb_phy1 =
  783. (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
  784. #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
  785. if (has_erratum_a006261())
  786. fsl_erratum_a006261_workaround(usb_phy1);
  787. #endif
  788. out_be32(&usb_phy1->usb_enable_override,
  789. CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
  790. }
  791. #endif
  792. #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
  793. {
  794. struct ccsr_usb_phy __iomem *usb_phy2 =
  795. (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
  796. #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
  797. if (has_erratum_a006261())
  798. fsl_erratum_a006261_workaround(usb_phy2);
  799. #endif
  800. out_be32(&usb_phy2->usb_enable_override,
  801. CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
  802. }
  803. #endif
  804. #ifdef CONFIG_SYS_FSL_ERRATUM_USB14
  805. /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal
  806. * multi-bit ECC errors which has impact on performance, so software
  807. * should disable all ECC reporting from USB1 and USB2.
  808. */
  809. if (IS_SVR_REV(get_svr(), 1, 0)) {
  810. struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *)
  811. (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET);
  812. setbits_be32(&dcfg->ecccr1,
  813. (DCSR_DCFG_ECC_DISABLE_USB1 |
  814. DCSR_DCFG_ECC_DISABLE_USB2));
  815. }
  816. #endif
  817. #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
  818. struct ccsr_usb_phy __iomem *usb_phy =
  819. (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
  820. setbits_be32(&usb_phy->pllprg[1],
  821. CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
  822. CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
  823. CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
  824. CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
  825. #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
  826. usb_single_source_clk_configure(usb_phy);
  827. #endif
  828. setbits_be32(&usb_phy->port1.ctrl,
  829. CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
  830. setbits_be32(&usb_phy->port1.drvvbuscfg,
  831. CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
  832. setbits_be32(&usb_phy->port1.pwrfltcfg,
  833. CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
  834. setbits_be32(&usb_phy->port2.ctrl,
  835. CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
  836. setbits_be32(&usb_phy->port2.drvvbuscfg,
  837. CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
  838. setbits_be32(&usb_phy->port2.pwrfltcfg,
  839. CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
  840. #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
  841. if (has_erratum_a006261())
  842. fsl_erratum_a006261_workaround(usb_phy);
  843. #endif
  844. #endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */
  845. #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
  846. erratum_a009942_check_cpo();
  847. #endif
  848. #ifdef CONFIG_FMAN_ENET
  849. fman_enet_init();
  850. #endif
  851. #if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET)
  852. if (pamu_init() < 0)
  853. fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT);
  854. #endif
  855. #ifdef CONFIG_FSL_CAAM
  856. sec_init();
  857. #if defined(CONFIG_ARCH_C29X)
  858. if ((SVR_SOC_VER(svr) == SVR_C292) ||
  859. (SVR_SOC_VER(svr) == SVR_C293))
  860. sec_init_idx(1);
  861. if (SVR_SOC_VER(svr) == SVR_C293)
  862. sec_init_idx(2);
  863. #endif
  864. #endif
  865. #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_SYS_FSL_ERRATUM_SATA_A001)
  866. /*
  867. * For P1022/1013 Rev1.0 silicon, after power on SATA host
  868. * controller is configured in legacy mode instead of the
  869. * expected enterprise mode. Software needs to clear bit[28]
  870. * of HControl register to change to enterprise mode from
  871. * legacy mode. We assume that the controller is offline.
  872. */
  873. if (IS_SVR_REV(svr, 1, 0) &&
  874. ((SVR_SOC_VER(svr) == SVR_P1022) ||
  875. (SVR_SOC_VER(svr) == SVR_P1013))) {
  876. fsl_sata_reg_t *reg;
  877. /* first SATA controller */
  878. reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
  879. clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
  880. /* second SATA controller */
  881. reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
  882. clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
  883. }
  884. #endif
  885. init_used_tlb_cams();
  886. return 0;
  887. }
  888. void arch_preboot_os(void)
  889. {
  890. u32 msr;
  891. /*
  892. * We are changing interrupt offsets and are about to boot the OS so
  893. * we need to make sure we disable all async interrupts. EE is already
  894. * disabled by the time we get called.
  895. */
  896. msr = mfmsr();
  897. msr &= ~(MSR_ME|MSR_CE);
  898. mtmsr(msr);
  899. }
  900. #if defined(CONFIG_SATA) && defined(CONFIG_FSL_SATA)
  901. int sata_initialize(void)
  902. {
  903. if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2))
  904. return __sata_initialize();
  905. return 1;
  906. }
  907. #endif
  908. void cpu_secondary_init_r(void)
  909. {
  910. #ifdef CONFIG_U_QE
  911. uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */
  912. #elif defined CONFIG_QE
  913. uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
  914. #endif
  915. #ifdef CONFIG_QE
  916. qe_init(qe_base);
  917. qe_reset();
  918. #endif
  919. }
  920. #ifdef CONFIG_BOARD_LATE_INIT
  921. int board_late_init(void)
  922. {
  923. #ifdef CONFIG_CHAIN_OF_TRUST
  924. fsl_setenv_chain_of_trust();
  925. #endif
  926. return 0;
  927. }
  928. #endif