inside-secure-safexcel.txt 1.5 KB

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  1. Inside Secure SafeXcel cryptographic engine
  2. Required properties:
  3. - compatible: Should be "inside-secure,safexcel-eip197b",
  4. "inside-secure,safexcel-eip197d" or
  5. "inside-secure,safexcel-eip97ies".
  6. - reg: Base physical address of the engine and length of memory mapped region.
  7. - interrupts: Interrupt numbers for the rings and engine.
  8. - interrupt-names: Should be "ring0", "ring1", "ring2", "ring3", "eip", "mem".
  9. Optional properties:
  10. - clocks: Reference to the crypto engine clocks, the second clock is
  11. needed for the Armada 7K/8K SoCs.
  12. - clock-names: mandatory if there is a second clock, in this case the
  13. name must be "core" for the first clock and "reg" for
  14. the second one.
  15. Backward compatibility:
  16. Two compatibles are kept for backward compatibility, but shouldn't be used for
  17. new submissions:
  18. - "inside-secure,safexcel-eip197" is equivalent to
  19. "inside-secure,safexcel-eip197b".
  20. - "inside-secure,safexcel-eip97" is equivalent to
  21. "inside-secure,safexcel-eip97ies".
  22. Example:
  23. crypto: crypto@800000 {
  24. compatible = "inside-secure,safexcel-eip197b";
  25. reg = <0x800000 0x200000>;
  26. interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
  27. <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
  28. <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
  29. <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
  30. <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
  31. <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
  32. interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3",
  33. "eip";
  34. clocks = <&cpm_syscon0 1 26>;
  35. };