sifive,plic-1.0.0.txt 2.6 KB

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  1. SiFive Platform-Level Interrupt Controller (PLIC)
  2. -------------------------------------------------
  3. SiFive SOCs include an implementation of the Platform-Level Interrupt Controller
  4. (PLIC) high-level specification in the RISC-V Privileged Architecture
  5. specification. The PLIC connects all external interrupts in the system to all
  6. hart contexts in the system, via the external interrupt source in each hart.
  7. A hart context is a privilege mode in a hardware execution thread. For example,
  8. in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
  9. privilege modes per hart; machine mode and supervisor mode.
  10. Each interrupt can be enabled on per-context basis. Any context can claim
  11. a pending enabled interrupt and then release it once it has been handled.
  12. Each interrupt has a configurable priority. Higher priority interrupts are
  13. serviced first. Each context can specify a priority threshold. Interrupts
  14. with priority below this threshold will not cause the PLIC to raise its
  15. interrupt line leading to the context.
  16. While the PLIC supports both edge-triggered and level-triggered interrupts,
  17. interrupt handlers are oblivious to this distinction and therefore it is not
  18. specified in the PLIC device-tree binding.
  19. While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
  20. "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
  21. contains a specific memory layout, which is documented in chapter 8 of the
  22. SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
  23. Required properties:
  24. - compatible : "sifive,plic-1.0.0" and a string identifying the actual
  25. detailed implementation in case that specific bugs need to be worked around.
  26. - #address-cells : should be <0> or more.
  27. - #interrupt-cells : should be <1> or more.
  28. - interrupt-controller : Identifies the node as an interrupt controller.
  29. - reg : Should contain 1 register range (address and length).
  30. - interrupts-extended : Specifies which contexts are connected to the PLIC,
  31. with "-1" specifying that a context is not present. Each node pointed
  32. to should be a riscv,cpu-intc node, which has a riscv node as parent.
  33. - riscv,ndev: Specifies how many external interrupts are supported by
  34. this controller.
  35. Example:
  36. plic: interrupt-controller@c000000 {
  37. #address-cells = <0>;
  38. #interrupt-cells = <1>;
  39. compatible = "sifive,plic-1.0.0", "sifive,fu540-c000-plic";
  40. interrupt-controller;
  41. interrupts-extended = <
  42. &cpu0-intc 11
  43. &cpu1-intc 11 &cpu1-intc 9
  44. &cpu2-intc 11 &cpu2-intc 9
  45. &cpu3-intc 11 &cpu3-intc 9
  46. &cpu4-intc 11 &cpu4-intc 9>;
  47. reg = <0xc000000 0x4000000>;
  48. riscv,ndev = <10>;
  49. };