axis,artpec6-pcie.txt 1.9 KB

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  1. * Axis ARTPEC-6 PCIe interface
  2. This PCIe host controller is based on the Synopsys DesignWare PCIe IP
  3. and thus inherits all the common properties defined in designware-pcie.txt.
  4. Required properties:
  5. - compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode;
  6. "axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode;
  7. "axis,artpec7-pcie", "snps,dw-pcie" for ARTPEC-7 in RC mode;
  8. "axis,artpec7-pcie-ep", "snps,dw-pcie" for ARTPEC-7 in EP mode;
  9. - reg: base addresses and lengths of the PCIe controller (DBI),
  10. the PHY controller, and configuration address space.
  11. - reg-names: Must include the following entries:
  12. - "dbi"
  13. - "phy"
  14. - "config"
  15. - interrupts: A list of interrupt outputs of the controller. Must contain an
  16. entry for each entry in the interrupt-names property.
  17. - interrupt-names: Must include the following entries:
  18. - "msi": The interrupt that is asserted when an MSI is received
  19. - axis,syscon-pcie: A phandle pointing to the ARTPEC-6 system controller,
  20. used to enable and control the Synopsys IP.
  21. Example:
  22. pcie@f8050000 {
  23. compatible = "axis,artpec6-pcie", "snps,dw-pcie";
  24. reg = <0xf8050000 0x2000
  25. 0xf8040000 0x1000
  26. 0xc0000000 0x2000>;
  27. reg-names = "dbi", "phy", "config";
  28. #address-cells = <3>;
  29. #size-cells = <2>;
  30. device_type = "pci";
  31. /* downstream I/O */
  32. ranges = <0x81000000 0 0 0xc0002000 0 0x00010000
  33. /* non-prefetchable memory */
  34. 0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>;
  35. num-lanes = <2>;
  36. bus-range = <0x00 0xff>;
  37. interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
  38. interrupt-names = "msi";
  39. #interrupt-cells = <1>;
  40. interrupt-map-mask = <0 0 0 0x7>;
  41. interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
  42. <0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
  43. <0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
  44. <0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
  45. axis,syscon-pcie = <&syscon>;
  46. };