pwm-mediatek.txt 1.5 KB

12345678910111213141516171819202122232425262728293031323334353637383940
  1. MediaTek PWM controller
  2. Required properties:
  3. - compatible: should be "mediatek,<name>-pwm":
  4. - "mediatek,mt2712-pwm": found on mt2712 SoC.
  5. - "mediatek,mt7622-pwm": found on mt7622 SoC.
  6. - "mediatek,mt7623-pwm": found on mt7623 SoC.
  7. - "mediatek,mt7628-pwm": found on mt7628 SoC.
  8. - reg: physical base address and length of the controller's registers.
  9. - #pwm-cells: must be 2. See pwm.txt in this directory for a description of
  10. the cell format.
  11. - clocks: phandle and clock specifier of the PWM reference clock.
  12. - clock-names: must contain the following, except for MT7628 which
  13. has no clocks
  14. - "top": the top clock generator
  15. - "main": clock used by the PWM core
  16. - "pwm1-8": the eight per PWM clocks for mt2712
  17. - "pwm1-6": the six per PWM clocks for mt7622
  18. - "pwm1-5": the five per PWM clocks for mt7623
  19. - pinctrl-names: Must contain a "default" entry.
  20. - pinctrl-0: One property must exist for each entry in pinctrl-names.
  21. See pinctrl/pinctrl-bindings.txt for details of the property values.
  22. Example:
  23. pwm0: pwm@11006000 {
  24. compatible = "mediatek,mt7623-pwm";
  25. reg = <0 0x11006000 0 0x1000>;
  26. #pwm-cells = <2>;
  27. clocks = <&topckgen CLK_TOP_PWM_SEL>,
  28. <&pericfg CLK_PERI_PWM>,
  29. <&pericfg CLK_PERI_PWM1>,
  30. <&pericfg CLK_PERI_PWM2>,
  31. <&pericfg CLK_PERI_PWM3>,
  32. <&pericfg CLK_PERI_PWM4>,
  33. <&pericfg CLK_PERI_PWM5>;
  34. clock-names = "top", "main", "pwm1", "pwm2",
  35. "pwm3", "pwm4", "pwm5";
  36. pinctrl-names = "default";
  37. pinctrl-0 = <&pwm0_pins>;
  38. };