spi-bus.txt 4.1 KB

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  1. SPI (Serial Peripheral Interface) busses
  2. SPI busses can be described with a node for the SPI controller device
  3. and a set of child nodes for each SPI slave on the bus. The system's SPI
  4. controller may be described for use in SPI master mode or in SPI slave mode,
  5. but not for both at the same time.
  6. The SPI controller node requires the following properties:
  7. - compatible - Name of SPI bus controller following generic names
  8. recommended practice.
  9. In master mode, the SPI controller node requires the following additional
  10. properties:
  11. - #address-cells - number of cells required to define a chip select
  12. address on the SPI bus.
  13. - #size-cells - should be zero.
  14. In slave mode, the SPI controller node requires one additional property:
  15. - spi-slave - Empty property.
  16. No other properties are required in the SPI bus node. It is assumed
  17. that a driver for an SPI bus device will understand that it is an SPI bus.
  18. However, the binding does not attempt to define the specific method for
  19. assigning chip select numbers. Since SPI chip select configuration is
  20. flexible and non-standardized, it is left out of this binding with the
  21. assumption that board specific platform code will be used to manage
  22. chip selects. Individual drivers can define additional properties to
  23. support describing the chip select layout.
  24. Optional properties (master mode only):
  25. - cs-gpios - gpios chip select.
  26. - num-cs - total number of chipselects.
  27. If cs-gpios is used the number of chip selects will be increased automatically
  28. with max(cs-gpios > hw cs).
  29. So if for example the controller has 2 CS lines, and the cs-gpios
  30. property looks like this:
  31. cs-gpios = <&gpio1 0 0>, <0>, <&gpio1 1 0>, <&gpio1 2 0>;
  32. Then it should be configured so that num_chipselect = 4 with the
  33. following mapping:
  34. cs0 : &gpio1 0 0
  35. cs1 : native
  36. cs2 : &gpio1 1 0
  37. cs3 : &gpio1 2 0
  38. SPI slave nodes must be children of the SPI controller node.
  39. In master mode, one or more slave nodes (up to the number of chip selects) can
  40. be present. Required properties are:
  41. - compatible - Name of SPI device following generic names recommended
  42. practice.
  43. - reg - Chip select address of device.
  44. - spi-max-frequency - Maximum SPI clocking speed of device in Hz.
  45. In slave mode, the (single) slave node is optional.
  46. If present, it must be called "slave". Required properties are:
  47. - compatible - Name of SPI device following generic names recommended
  48. practice.
  49. All slave nodes can contain the following optional properties:
  50. - spi-cpol - Empty property indicating device requires inverse clock
  51. polarity (CPOL) mode.
  52. - spi-cpha - Empty property indicating device requires shifted clock
  53. phase (CPHA) mode.
  54. - spi-cs-high - Empty property indicating device requires chip select
  55. active high.
  56. - spi-3wire - Empty property indicating device requires 3-wire mode.
  57. - spi-lsb-first - Empty property indicating device requires LSB first mode.
  58. - spi-tx-bus-width - The bus width (number of data wires) that is used for MOSI.
  59. Defaults to 1 if not present.
  60. - spi-rx-bus-width - The bus width (number of data wires) that is used for MISO.
  61. Defaults to 1 if not present.
  62. - spi-rx-delay-us - Microsecond delay after a read transfer.
  63. - spi-tx-delay-us - Microsecond delay after a write transfer.
  64. Some SPI controllers and devices support Dual and Quad SPI transfer mode.
  65. It allows data in the SPI system to be transferred using 2 wires (DUAL) or 4
  66. wires (QUAD).
  67. Now the value that spi-tx-bus-width and spi-rx-bus-width can receive is
  68. only 1 (SINGLE), 2 (DUAL) and 4 (QUAD).
  69. Dual/Quad mode is not allowed when 3-wire mode is used.
  70. If a gpio chipselect is used for the SPI slave the gpio number will be passed
  71. via the SPI master node cs-gpios property.
  72. SPI example for an MPC5200 SPI bus:
  73. spi@f00 {
  74. #address-cells = <1>;
  75. #size-cells = <0>;
  76. compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
  77. reg = <0xf00 0x20>;
  78. interrupts = <2 13 0 2 14 0>;
  79. interrupt-parent = <&mpc5200_pic>;
  80. ethernet-switch@0 {
  81. compatible = "micrel,ks8995m";
  82. spi-max-frequency = <1000000>;
  83. reg = <0>;
  84. };
  85. codec@1 {
  86. compatible = "ti,tlv320aic26";
  87. spi-max-frequency = <100000>;
  88. reg = <1>;
  89. };
  90. };