spi-meson.txt 1.7 KB

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  1. Amlogic Meson SPI controllers
  2. * SPIFC (SPI Flash Controller)
  3. The Meson SPIFC is a controller optimized for communication with SPI
  4. NOR memories, without DMA support and a 64-byte unified transmit /
  5. receive buffer.
  6. Required properties:
  7. - compatible: should be "amlogic,meson6-spifc" or "amlogic,meson-gxbb-spifc"
  8. - reg: physical base address and length of the controller registers
  9. - clocks: phandle of the input clock for the baud rate generator
  10. - #address-cells: should be 1
  11. - #size-cells: should be 0
  12. spi@c1108c80 {
  13. compatible = "amlogic,meson6-spifc";
  14. reg = <0xc1108c80 0x80>;
  15. clocks = <&clk81>;
  16. #address-cells = <1>;
  17. #size-cells = <0>;
  18. };
  19. * SPICC (SPI Communication Controller)
  20. The Meson SPICC is generic SPI controller for general purpose Full-Duplex
  21. communications with dedicated 16 words RX/TX PIO FIFOs.
  22. Required properties:
  23. - compatible: should be:
  24. "amlogic,meson-gx-spicc" on Amlogic GX and compatible SoCs.
  25. "amlogic,meson-axg-spicc" on Amlogic AXG and compatible SoCs
  26. - reg: physical base address and length of the controller registers
  27. - interrupts: The interrupt specifier
  28. - clock-names: Must contain "core"
  29. - clocks: phandle of the input clock for the baud rate generator
  30. - #address-cells: should be 1
  31. - #size-cells: should be 0
  32. Optional properties:
  33. - resets: phandle of the internal reset line
  34. See ../spi/spi-bus.txt for more details on SPI bus master and slave devices
  35. required and optional properties.
  36. Example :
  37. spi@c1108d80 {
  38. compatible = "amlogic,meson-gx-spicc";
  39. reg = <0xc1108d80 0x80>;
  40. interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
  41. clock-names = "core";
  42. clocks = <&clk81>;
  43. #address-cells = <1>;
  44. #size-cells = <0>;
  45. };