dwc3.txt 5.5 KB

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  1. synopsys DWC3 CORE
  2. DWC3- USB3 CONTROLLER. Complies to the generic USB binding properties
  3. as described in 'usb/generic.txt'
  4. Required properties:
  5. - compatible: must be "snps,dwc3"
  6. - reg : Address and length of the register set for the device
  7. - interrupts: Interrupts used by the dwc3 controller.
  8. - clock-names: should contain "ref", "bus_early", "suspend"
  9. - clocks: list of phandle and clock specifier pairs corresponding to
  10. entries in the clock-names property.
  11. Exception for clocks:
  12. clocks are optional if the parent node (i.e. glue-layer) is compatible to
  13. one of the following:
  14. "amlogic,meson-axg-dwc3"
  15. "amlogic,meson-gxl-dwc3"
  16. "cavium,octeon-7130-usb-uctl"
  17. "qcom,dwc3"
  18. "samsung,exynos5250-dwusb3"
  19. "samsung,exynos7-dwusb3"
  20. "sprd,sc9860-dwc3"
  21. "st,stih407-dwc3"
  22. "ti,am437x-dwc3"
  23. "ti,dwc3"
  24. "ti,keystone-dwc3"
  25. "rockchip,rk3399-dwc3"
  26. "xlnx,zynqmp-dwc3"
  27. Optional properties:
  28. - usb-phy : array of phandle for the PHY device. The first element
  29. in the array is expected to be a handle to the USB2/HS PHY and
  30. the second element is expected to be a handle to the USB3/SS PHY
  31. - phys: from the *Generic PHY* bindings
  32. - phy-names: from the *Generic PHY* bindings; supported names are "usb2-phy"
  33. or "usb3-phy".
  34. - resets: a single pair of phandle and reset specifier
  35. - snps,usb3_lpm_capable: determines if platform is USB3 LPM capable
  36. - snps,disable_scramble_quirk: true when SW should disable data scrambling.
  37. Only really useful for FPGA builds.
  38. - snps,has-lpm-erratum: true when DWC3 was configured with LPM Erratum enabled
  39. - snps,lpm-nyet-threshold: LPM NYET threshold
  40. - snps,u2exit_lfps_quirk: set if we want to enable u2exit lfps quirk
  41. - snps,u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
  42. - snps,req_p1p2p3_quirk: when set, the core will always request for
  43. P1/P2/P3 transition sequence.
  44. - snps,del_p1p2p3_quirk: when set core will delay P1/P2/P3 until a certain
  45. amount of 8B10B errors occur.
  46. - snps,del_phy_power_chg_quirk: when set core will delay PHY power change
  47. from P0 to P1/P2/P3.
  48. - snps,lfps_filter_quirk: when set core will filter LFPS reception.
  49. - snps,rx_detect_poll_quirk: when set core will disable a 400us delay to start
  50. Polling LFPS after RX.Detect.
  51. - snps,tx_de_emphasis_quirk: when set core will set Tx de-emphasis value.
  52. - snps,tx_de_emphasis: the value driven to the PHY is controlled by the
  53. LTSSM during USB3 Compliance mode.
  54. - snps,dis_u3_susphy_quirk: when set core will disable USB3 suspend phy.
  55. - snps,dis_u2_susphy_quirk: when set core will disable USB2 suspend phy.
  56. - snps,dis_enblslpm_quirk: when set clears the enblslpm in GUSB2PHYCFG,
  57. disabling the suspend signal to the PHY.
  58. - snps,dis_rxdet_inp3_quirk: when set core will disable receiver detection
  59. in PHY P3 power state.
  60. - snps,dis-u2-freeclk-exists-quirk: when set, clear the u2_freeclk_exists
  61. in GUSB2PHYCFG, specify that USB2 PHY doesn't provide
  62. a free-running PHY clock.
  63. - snps,dis-del-phy-power-chg-quirk: when set core will change PHY power
  64. from P0 to P1/P2/P3 without delay.
  65. - snps,dis-tx-ipgap-linecheck-quirk: when set, disable u2mac linestate check
  66. during HS transmit.
  67. - snps,parkmode-disable-ss-quirk: when set, all SuperSpeed bus instances in
  68. park mode are disabled.
  69. - snps,dis_metastability_quirk: when set, disable metastability workaround.
  70. CAUTION: use only if you are absolutely sure of it.
  71. - snps,is-utmi-l1-suspend: true when DWC3 asserts output signal
  72. utmi_l1_suspend_n, false when asserts utmi_sleep_n
  73. - snps,hird-threshold: HIRD threshold
  74. - snps,hsphy_interface: High-Speed PHY interface selection between "utmi" for
  75. UTMI+ and "ulpi" for ULPI when the DWC_USB3_HSPHY_INTERFACE has value 3.
  76. - snps,quirk-frame-length-adjustment: Value for GFLADJ_30MHZ field of GFLADJ
  77. register for post-silicon frame length adjustment when the
  78. fladj_30mhz_sdbnd signal is invalid or incorrect.
  79. - snps,rx-thr-num-pkt-prd: periodic ESS RX packet threshold count - host mode
  80. only. Set this and rx-max-burst-prd to a valid,
  81. non-zero value 1-16 (DWC_usb31 programming guide
  82. section 1.2.4) to enable periodic ESS RX threshold.
  83. - snps,rx-max-burst-prd: max periodic ESS RX burst size - host mode only. Set
  84. this and rx-thr-num-pkt-prd to a valid, non-zero value
  85. 1-16 (DWC_usb31 programming guide section 1.2.4) to
  86. enable periodic ESS RX threshold.
  87. - snps,tx-thr-num-pkt-prd: periodic ESS TX packet threshold count - host mode
  88. only. Set this and tx-max-burst-prd to a valid,
  89. non-zero value 1-16 (DWC_usb31 programming guide
  90. section 1.2.3) to enable periodic ESS TX threshold.
  91. - snps,tx-max-burst-prd: max periodic ESS TX burst size - host mode only. Set
  92. this and tx-thr-num-pkt-prd to a valid, non-zero value
  93. 1-16 (DWC_usb31 programming guide section 1.2.3) to
  94. enable periodic ESS TX threshold.
  95. - <DEPRECATED> tx-fifo-resize: determines if the FIFO *has* to be reallocated.
  96. - snps,incr-burst-type-adjustment: Value for INCR burst type of GSBUSCFG0
  97. register, undefined length INCR burst type enable and INCRx type.
  98. When just one value, which means INCRX burst mode enabled. When
  99. more than one value, which means undefined length INCR burst type
  100. enabled. The values can be 1, 4, 8, 16, 32, 64, 128 and 256.
  101. - in addition all properties from usb-xhci.txt from the current directory are
  102. supported as well
  103. This is usually a subnode to DWC3 glue to which it is connected.
  104. dwc3@4a030000 {
  105. compatible = "snps,dwc3";
  106. reg = <0x4a030000 0xcfff>;
  107. interrupts = <0 92 4>
  108. usb-phy = <&usb2_phy>, <&usb3,phy>;
  109. snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
  110. };