core_polaris.c 4.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * linux/arch/alpha/kernel/core_polaris.c
  4. *
  5. * POLARIS chip-specific code
  6. */
  7. #define __EXTERN_INLINE inline
  8. #include <asm/io.h>
  9. #include <asm/core_polaris.h>
  10. #undef __EXTERN_INLINE
  11. #include <linux/types.h>
  12. #include <linux/pci.h>
  13. #include <linux/sched.h>
  14. #include <linux/init.h>
  15. #include <asm/ptrace.h>
  16. #include "proto.h"
  17. #include "pci_impl.h"
  18. /*
  19. * BIOS32-style PCI interface:
  20. */
  21. #define DEBUG_CONFIG 0
  22. #if DEBUG_CONFIG
  23. # define DBG_CFG(args) printk args
  24. #else
  25. # define DBG_CFG(args)
  26. #endif
  27. /*
  28. * Given a bus, device, and function number, compute resulting
  29. * configuration space address. This is fairly straightforward
  30. * on POLARIS, since the chip itself generates Type 0 or Type 1
  31. * cycles automatically depending on the bus number (Bus 0 is
  32. * hardwired to Type 0, all others are Type 1. Peer bridges
  33. * are not supported).
  34. *
  35. * All types:
  36. *
  37. * 3 3 3 3|3 3 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
  38. * 9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
  39. * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  40. * |1|1|1|1|1|0|0|1|1|1|1|1|1|1|1|0|B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|x|x|
  41. * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  42. *
  43. * 23:16 bus number (8 bits = 128 possible buses)
  44. * 15:11 Device number (5 bits)
  45. * 10:8 function number
  46. * 7:2 register number
  47. *
  48. * Notes:
  49. * The function number selects which function of a multi-function device
  50. * (e.g., scsi and ethernet).
  51. *
  52. * The register selects a DWORD (32 bit) register offset. Hence it
  53. * doesn't get shifted by 2 bits as we want to "drop" the bottom two
  54. * bits.
  55. */
  56. static int
  57. mk_conf_addr(struct pci_bus *pbus, unsigned int device_fn, int where,
  58. unsigned long *pci_addr, u8 *type1)
  59. {
  60. u8 bus = pbus->number;
  61. *type1 = (bus == 0) ? 0 : 1;
  62. *pci_addr = (bus << 16) | (device_fn << 8) | (where) |
  63. POLARIS_DENSE_CONFIG_BASE;
  64. DBG_CFG(("mk_conf_addr(bus=%d ,device_fn=0x%x, where=0x%x,"
  65. " returning address 0x%p\n"
  66. bus, device_fn, where, *pci_addr));
  67. return 0;
  68. }
  69. static int
  70. polaris_read_config(struct pci_bus *bus, unsigned int devfn, int where,
  71. int size, u32 *value)
  72. {
  73. unsigned long addr;
  74. unsigned char type1;
  75. if (mk_conf_addr(bus, devfn, where, &addr, &type1))
  76. return PCIBIOS_DEVICE_NOT_FOUND;
  77. switch (size) {
  78. case 1:
  79. *value = __kernel_ldbu(*(vucp)addr);
  80. break;
  81. case 2:
  82. *value = __kernel_ldwu(*(vusp)addr);
  83. break;
  84. case 4:
  85. *value = *(vuip)addr;
  86. break;
  87. }
  88. return PCIBIOS_SUCCESSFUL;
  89. }
  90. static int
  91. polaris_write_config(struct pci_bus *bus, unsigned int devfn, int where,
  92. int size, u32 value)
  93. {
  94. unsigned long addr;
  95. unsigned char type1;
  96. if (mk_conf_addr(bus, devfn, where, &addr, &type1))
  97. return PCIBIOS_DEVICE_NOT_FOUND;
  98. switch (size) {
  99. case 1:
  100. __kernel_stb(value, *(vucp)addr);
  101. mb();
  102. __kernel_ldbu(*(vucp)addr);
  103. break;
  104. case 2:
  105. __kernel_stw(value, *(vusp)addr);
  106. mb();
  107. __kernel_ldwu(*(vusp)addr);
  108. break;
  109. case 4:
  110. *(vuip)addr = value;
  111. mb();
  112. *(vuip)addr;
  113. break;
  114. }
  115. return PCIBIOS_SUCCESSFUL;
  116. }
  117. struct pci_ops polaris_pci_ops =
  118. {
  119. .read = polaris_read_config,
  120. .write = polaris_write_config,
  121. };
  122. void __init
  123. polaris_init_arch(void)
  124. {
  125. struct pci_controller *hose;
  126. /* May need to initialize error reporting (see PCICTL0/1), but
  127. * for now assume that the firmware has done the right thing
  128. * already.
  129. */
  130. #if 0
  131. printk("polaris_init_arch(): trusting firmware for setup\n");
  132. #endif
  133. /*
  134. * Create our single hose.
  135. */
  136. pci_isa_hose = hose = alloc_pci_controller();
  137. hose->io_space = &ioport_resource;
  138. hose->mem_space = &iomem_resource;
  139. hose->index = 0;
  140. hose->sparse_mem_base = 0;
  141. hose->dense_mem_base = POLARIS_DENSE_MEM_BASE - IDENT_ADDR;
  142. hose->sparse_io_base = 0;
  143. hose->dense_io_base = POLARIS_DENSE_IO_BASE - IDENT_ADDR;
  144. hose->sg_isa = hose->sg_pci = NULL;
  145. /* The I/O window is fixed at 2G @ 2G. */
  146. __direct_map_base = 0x80000000;
  147. __direct_map_size = 0x80000000;
  148. }
  149. static inline void
  150. polaris_pci_clr_err(void)
  151. {
  152. *(vusp)POLARIS_W_STATUS;
  153. /* Write 1's to settable bits to clear errors */
  154. *(vusp)POLARIS_W_STATUS = 0x7800;
  155. mb();
  156. *(vusp)POLARIS_W_STATUS;
  157. }
  158. void
  159. polaris_machine_check(unsigned long vector, unsigned long la_ptr)
  160. {
  161. /* Clear the error before any reporting. */
  162. mb();
  163. mb();
  164. draina();
  165. polaris_pci_clr_err();
  166. wrmces(0x7);
  167. mb();
  168. process_mcheck_info(vector, la_ptr, "POLARIS",
  169. mcheck_expected(0));
  170. }